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Access our network NOW!!! FREE Windows Software!! Complete Easy System.!! Automatic Update!! Full UNLIMITED Internet Access for $19.96 ,Chat, Forums, Classified ,Usenet Business forums , Family forums,Online games!! and more!! BETTER THAN Prodigy , ComuServe and America Online!! For more Info: Log on my BBS (312)247-9051 and download the file "pwr1.txt" BUT HURRY UP before it is too late!!!Article: 3751
I'm looking for references to implementations of signed-digit arithmetic circuits on FPGA's. I'm especially interested in circuits for addition, subtraction and absolute value of SD numbers. Thanks in advance, -Arrigo BenedettiArticle: 3752
Hello of France, I need information on the hardware programmation of the Mach130 FPGA of AMD. On AMD WWW server ,i found the data sheet but nothing on how to made the hardware for programme it. (Sorry for my english) thanksArticle: 3753
Does anyone have an experience in designing a VME hardware interface (slave + IT) using CPLD from Xilinx (9500 series) ? Propagation delays offered by these chips sound good but I wonder if the complexity would fit. Thank you for any information concerning this subject. RegisArticle: 3754
Are we going to start posting job listings to these newsgroups?Article: 3755
Hi, we have some problems configuring a XC4006 device with ATT17128F EEPROMs. Some times it will work, other times there will be an frame error indicated by INIT pull low after a few milli seconds. Downloading the design from the PC will work all the time. We have sampled the data at the DIN pin from the device and the result is: the frame error is correct. Some "0" are missing. The data in the ATT17128 was programmed by SPRINT and also read-back - correct. Who can help us? scanning the newsgroup Walter Lang -- Dipl.-Ing. Walter Lang Universitaet-GH Siegen FB12 Elektrotechnik und Informatik Fachgruppe Technische Informatik Hoelderlinstr. 3 D - 57068 Siegen Phone: +49 271 740 3210 FAX: +49 271 740 3344 E-Mail: lang@ti.et-inf.uni-siegen.de WWW: www.ti.et-inf.uni-siegen.deArticle: 3756
The word "Better" is unclear. Certainly, it is in the eye of the beholder. A simple way to configure XC3xxxA Parts is in Master mode. (use Pull downs on M0-M2, so when u want, u can pull them up for use with an xChecker Cable). However, a with a few additional discretes, a cheeper (Financially & Real Estate wise) method could be implemened, namely configuration Master-Slave daisy chain. Be sure to study the State Diagram provided in the databook, CAREFULLY. U can use the xChecker cable to configure daisy-chains, however, two items of interest are brought to mind: 1) ALL in the chain must be configured SLAVE mode (M2 M1 M0 == 1 1 1). 2) Only the first in the chain can be read back. This is only my opinion based on my little experience. Nothing Gauranteed HereArticle: 3757
I am looking for input for a good book for someone who is starting to
learn about FPGA's. A friend
told me about a book he saw in Barnes & Noble - he didn't get the title
but said it was published this year, gave a good overview of FPGA's and
compared different applications, etc. Any ideas or suggestions for
other books?
Any help is appreciated!
--
Regards, | INTERNET: jellsworth@vnet.ibm.com
Janet | IBMnet: ellsworj@edamail.fishkill.ibm.com
| PHONE: (914) 892-4359
------------------------------------------------------------
"......Life has funny, funny way....of sneaking up on you..." - A.
Morissette
Article: 3758Been There Done That! A clue is to look at your Vcc ramp up time. Why, I don't know. My experience is that this flakey behavior is related Vcc ramp up. Hot Insertion worked 100%, xChecker worked 100%, Xilinx worked 100%. I simply removed ATT as a second source to the xilinx.Article: 3759
In Article <31F7B3F1.433C@ti.et-inf.uni-siegen.de> Operator writes: >Hi, >we have some problems configuring a XC4006 device >with ATT17128F EEPROMs. There is an Atmel equivalent part. Has anyone any experience good or bad with these? Jeremy.Article: 3760
Anton Scherer wrote: > > We have two altera-designs we want to fit into xilinx devices. > The first design is in Altera-HDL (.tdf-files) and the other design is > written with PD-Shell (one .pds-file). > We are working with Mentor Graphics Tools, Maxplus2 Version 6 and XACTstep 5.2 on Sun Sparc > Station (SunOS 4.1.3). > I tried to write an EDIF-netlist with the altera-tool (.edo) > and to read it in the Synthesis-Tool of Mentor Graphics. But I had some problems with > the Altera delay-Cells in the edif-out-netlist. > > Is there a apropriate way to "translate" the altera-design to xilinx. > I heard that there is a way with Exemplar but we do not have Exemplar. > > Anton Scherer > Microswiss-Zentrum Nord-Sued > Switzerland Yes, Exemplar should be able to handle this. It is pretty good at conversions from one format to another. -- ############################################################################ # # # Dave Matthews djm@papillonres.com # # # # Papillon Research Corp. Providing Full Product Development # # (formerly Chrysalis Research Corp.) including: # # 52 Domino Dr., Concord, MA 01742 * System Architecture # # Phone - (508)371-9115 * ASIC and FPGA Design # # Fax - (508)371-9175 * VHDL/Verilog Modeling & Synthesis # # * EMI - EMC Consulting Services # # # # (Chrysalis Research Corp. is not affiliated with Chrysalis Symbolic # # Design, Inc.) # #####################Article: 3761
Hello,
I am looking for information on the topic of
"fault tolerance with programmable logic" (as I am
writing a paper on this subject for a class).
I am interested in 'how' fault tolerant designs
are implemented, how specially-made fault tolerant
programmable devices are used, special fault
tolerant considerations for programmable devices,
and other such related material.
I would appreciate pointers to any resources
of which you are aware -- {if they are on-line (i.e. on
the web), then these would be very useful!}
Thank you,
Edward Leventhal
===================================================================
= Edward Leventhal =
= Electrical Design Engineer =
= Omitron, Inc., 6411 Ivy Lane, Suite 600, Greenbelt, MD 20770 =
= Phone: (301)474-1700 Fax: (301)345-4594 =
= e-mail: ed.leventhal@omitron.com =
===================================================================
Article: 3762
I purchased a copy of Lattice's ISP starter kit, and I am just toying with
programming teh 2032 part. I got a PLCC adapter that I've plugged into
my breadboard, and have wired up the programming cable. The programming
software ('Daisy Chain Download') that came with the kit recognizes the
chip, and says it succesfully programmed it, but that it cannot verify
it because the security fuse is set. But, when I generated the fuse map
(.JED file) I told it to not set the security fuse. My design does not
appear to be in the device from my simple tests.
Any ideas? Am I just destroying the signals by running it on a breadboard?
(In case you coudln't tell, I'm not a real hardware guy, I mostly do software.
I find digital logic fascinating, though, and I wanted to try it out...)
-Matt
Article: 3763AT&T flash serial proms observed to fail to configure reliably at powerup. I have had the exact same experience with AT&T serial proms. They work fine if the power supply comes up fast, and don't configure if it comes up slow. I still use then for development. I have a power plug on the board I pull and put back to make the power come on fast. This works great. For delivery, I will not use them. The power supply environment isn't well enough controlled for me to depend on it. I don't get a kick out of going to a delivered box and swapping to non-flash serial proms to make power-up more reliable. I wonder if a power-up chip could be used to re-configure the xilinx chips so that these AT&T Flash parts could be used in delivered boards. LawrenceArticle: 3764
ANNOUNCING SETANTA ED - THE HDL EDITOR FOR ENGINEERS As part of their recent work with Electronic Design Automation (EDA) tools, VHDL System Solutions have developed a high quality HDL (Hardware Decription Language) Editor, called Setanta ED. It supports both VHDL and Verilog languages. A 45-day evaluation copy of the product may be downloaded from the following site. http://www.vhdl.com.au This is a PC-based productivity tool incorporating many features including dozens of synthesizable models, automatic testbench generation and keyword template expansion.Article: 3765
In article <4tav6m$4lb@transfer.stratus.com>, Matt Cross
<mcross@sw.stratus.com> writes
>I purchased a copy of Lattice's ISP starter kit, and I am just toying with
>programming teh 2032 part. I got a PLCC adapter that I've plugged into
>my breadboard, and have wired up the programming cable. The programming
>software ('Daisy Chain Download') that came with the kit recognizes the
>chip, and says it succesfully programmed it, but that it cannot verify
>it because the security fuse is set. But, when I generated the fuse map
>(.JED file) I told it to not set the security fuse. My design does not
>appear to be in the device from my simple tests.
>
>Any ideas? Am I just destroying the signals by running it on a breadboard?
>
>(In case you coudln't tell, I'm not a real hardware guy, I mostly do software.
> I find digital logic fascinating, though, and I wanted to try it out...)
>
> -Matt
>
>
The first circuit I built didn't include the .01uF capacitor between
!ispEN and ground which caused the verification to fail.
I've used the 2032 with a home made PLCC to DIL adaptor on a breadboard
OK.
Does the PLD function OK, with the validation failing?
Have you tried using another 2032 or possible a 1016?
Off topic:
Has anybody managaged to order the free CD from lattice, with the pDS
software on?
I would like to hear from any hobbiest who have used any FPGA's
especially the MPA series.
Cheers
Nigel@tennyson.demon.co.uk
Article: 3766Walter Lang (Operator) wrote: > > Hi, > we have some problems configuring a XC4006 device > with ATT17128F EEPROMs. Some times it will work, > other times there will be an frame error indicated > by INIT pull low after a few milli seconds. I have had trouble with ATT1736 serial PROMs when configuring either the ATT 3000 or Xilinx 3000 FPGAs. I have tried them several times in the past several years by getting samples from different distributors. I asked AT&T reps but they didn't seem interested so I don't use ATT 17XXs anymore. Maybe the guys from LUCENT will be more responsive. For now I use only Xilinx parts (OTP only) in production and have never had a problem. I also use the Atmel 1765 parts for prototype as they are reprogrammable. These seem to work fine too. I would allow these for production but they don't make the smaller 1736 part. Regards, TARArticle: 3767
On Thu, 25 Jul 1996, Janet Ellsworth wrote: > I am looking for input for a good book for someone who is starting to > learn about FPGA's. A friend > told me about a book he saw in Barnes & Noble - he didn't get the title > but said it was published this year, gave a good overview of FPGA's and > compared different applications, etc. Any ideas or suggestions for > other books? Hi Janet, have a look at the WWW servers of such companies like Actel, Altera, AT&T, XILINX etc. Most of them will have data sheets in .pdf format about their FPGA products. If you understand the basics of logic design I think there is no problem to use these data sheets instead of (expensive) books. The data sheets offer you a very detailed overview about the FPGA logic cells, the IO capabilities and the interconnect resources. Of course, no one describes the limitations of the products 8-). E-regards --------------------------- Rainer Scharnow (amigo@bintec.de) BinTec Commmunications GmbH ---------------------------Article: 3768
In article <DuyrBs.7v5@world.std.com> jcooley@world.std.com (John Cooley) writes:
>
> ..................... Please reply *on* or *before* this Thursday,
> July 25th (three days from now) to "jcooley@world.std.com" so I can get
> this quickly tabulated and written up.
> - John Cooley
>
You seem to have an overly optimistic expectation of news propagation times.
We get our news feed from BBN Planet and your message didn't get to our
site until 27 July at 0144, although it appears to have been posted on 22
July at about 2121.
It may be that BBN is just a particularly unreliable source for a news
feed. I notice that there are significant numbers of articles that I get
through my home Internet provider that NEVER show up here at work. I can't
successfully correlate the missing articles with anything else, though.
pete peterson
rep@genrad.com
+1-508-287-7478 (GenRad); +1-508-256-5829 (Home: Chelmsford, MA)
+1-508-287-7007 (FAX)
Article: 3769Dear ASIC/FPGA Designers, hereby we would like to introduce the "A Survey on Design Errors" WWW-server: http://www.lis.e-technik.tu-muenchen.de/DEP/ and invite all of you to visit it. This server is installed to collect the opinions of ASIC and/or FPGA designers regarding the concept of design errors and problems they can cause. Our final goal is to develop special technology extensions and synthesis algorithms that allow the designers to correct their mistakes even after chip fabrication. (This capability is named Correctability) These mistakes are principally those design errors that are made during the design development steps and have not been found in verification phases. In order to get more familiar with this subject, you can refer to: "Modeling of VHDL Design Errors and Methods for their Correctability", M.R. Movahedin, P. Kindsmüeller, W. Stechele, VHDL International Users' Forum, Spring 1996 (VIUF'96). or get its postscript version from the server. This survey will help us to find out what kind of design errors have to be concentrated more on, and which imaginable ones are less important. We appriciate your efforts in filling out this questionnaire, and will send you a copy of the processed results, if you provide us with an E-mail address. Thank you for taking time to visit and fill out the survey Institute for Integrated Circuits Technical University of Munich Munich, Germany For any question or further information, feel free to drop us a message: M_Movahedin@lis.e-technik.tu-muenchen.de ############################################################################## The survey includes two groups of questions: In the first group, some general questions about your experiences in ASIC/FPGA design and the concept of design errors are asked. The second part of the questionnaire concentrates on a (V)HDL design error model. This model is mainly based on the usually used synthesizable subset of VHDL, but you can answer the questions, even if you are a Verilog user. This model deals mainly with the mistakes made during the development of the design HDL description, and are propagated to gate level by a synthesizer, resulting in a flawed chip. In view of the fact that a quite complete simulation and/or verification of a large design takes a long time and is practically impossible , those flaws could not be detected before chip fabrication and only after the chip takes effect in the whole system, they would be detected by observing the system malfunctions. Thus, a redesign, i.e. rewriting the HDL description and correcting its mistakes, will be necessary to achieve to a flawless chip. The answer to the question why these errors have happened and not detected in verification phases is beyond this questionnaire, and depends strongly on the designers' design methodology. But it can not be forgotten that no one can claim that his/her design is quite error free. The VLSI history shows that even large powerful companies have designed and fabricated flawed microprocessors and their mistakes are first detected after a very long while.Article: 3770
Gordon McGregor wrote: > > I could not find any information in the Xilinx databook to support the > assertion that the data in a flip-flop is cleared if the cell that > contains it is being reconfigured. Certainly the Atmel devices allows > a cell's logic to be modified while retaining the state of the > flip-flop in the cell. I would be interested if anyone could clarify > the point that the XC6200 would clear the register state when the > remainder of the CLB was being modified. > Hopefully this will clarify these points: The register is not cleared automatically when the cell is reconfigured. It continues to do whatever it is configured for. It will continue to be clocked (if that is what has been configured) and will continue to clock in data. It is possible to set the Register Protect (RP) bit associated with any particular register to protect the register from changes on its D-input which may be happening while the rest of the cell is being re- configured. The clock to the registers may also be stopped to prevent changes. The register is only cleared if its CLR input is asserted, although even this will have no effect if the RP bit is set. Asserting the XC6200 Reset_ pin will always clear the registers.Article: 3771
I am using the Cypress 7C382A device, and currently program on a Cypress programming unit. The unit appearst to be a re-labeled Dataio Chipsite, with only Cypress numbers supported. As - is, the LOF files take 20 minutes to load with approx. 20 minutes to program each device afterwards. My group is now starting to uses hundreds of these devices, and production is now limited by the programming time. I originally thought this would be solved by going to a distributer for pre-programmed devices - but they appear to be just as slow in delivery leading me to suspect they use the same mule of a programmer unit. Is there a bulk programmer that can do multiple devices? If so, who do I contact to arrange a fast lease or purchase. Do the manufacturers out there support preprogrammed devices? Will the Quicklogic equivalent tools support the Cypress device? Thanks for any help. You can post replies to the newsgroup or email me at dana@xetron.comArticle: 3772
Hello, I've got a 35K embedded array design I want to target for an fgpa. There are two clock domains which split apart fairly nicely. I'd like to use one part total though. Are there devices dense enough to fit 35K gates plus 1k bits of RAM? The methodology is verilog/Synopsys. thanks, -Larry -------------------------------------------------------------- Larry Getzin Email: lgetzin@thoreau.nsc.com National Semiconductor Corp. 333 Western Avenue MS 10-26 South Portland, Maine 04106 --------------------------------------------------------------Article: 3773
Arrigo Benedetti wrote:
>
> I'm looking for references to implementations of signed-digit arithmetic
> circuits on FPGA's. I'm especially interested in circuits for
> addition, subtraction and absolute value of SD numbers.
>
> Thanks in advance,
>
> -Arrigo Benedetti
Ciao
I think that the best introduction to "Signed-digit arithmetic" is
in "COMPUTER ARITHMETIC:PRINCIPLES ARCHITECTURE AND DESIGN" KAI HWANG
John Wiley and Sons 1979.
In:
[1] N. Takagi "Studies on hardware algorithms operations with a redundant binary representations".
PhD Dissertation, Department of Information Science, Faculty of Engineering, University of Kyoto,
August, 1987.
[2] D. Timmermann, B.J. Hosticka "Overflow effects in redundant binary number systems", Electronic
Letters Vol. 29, n°5, 1993
you can find useful hints to implementation of efficient SD adders.
Bye
Pasquale Corsonello
Dept. of Electronic Computer Science and System
University of Calabria
87036 - Arcavacata di Rende (CS)
ITALY
fax:+39 984 494713
email:pascor@ccusc1.uncial.it
corsone@nwdeis1.unical.it
Article: 3774
In article <qKWR+DAAxi+xEwJ4@tennyson.demon.co.uk>
nigel@tennyson.demon.co.uk "Nigel Burrows" writes:
[deleted]
> Off topic:
> Has anybody managaged to order the free CD from lattice, with the pDS
> software on?
I've just ordered it by filling in the order form on the Lattice Web
site. I think it has Synario, not the PDS, for the smaller devices, on
it.
Leon
--
Leon Heller, G1HSM | "Do not adjust your mind, there is
E-mail leon@lfheller.demon.co.uk | a fault in reality": on a wall
Phone: +44 (0)1734 471424 | many years ago in Oxford.
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Compare FPGA features and resources
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