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The latest version of synplicity (6.11) optimizes your global reset out if you connect it to a constant...which is sort of what you want. The problem is when it does that it loses the initial state information and initializes all the FF's to '0'. At least it is kind enough to give a warning when that happens, although the first time it happened to me I missed it and wound up wasting a day trying to figure out why it didn't work in the lab. To fix it, you need to put a syn_keep attribute on the global reset net so that the initial values get retained in the compile. Andy Peters wrote: > > Peter Lang wrote: > > > > Hi, > > I think I must decribe my problem more precise: > > I only want that an CLB Register FF inits to one after the configuration of > > the FPGA is > > done. I dont want to use expilicit asynchron set lines to do this. > > GSR does exactly that. Write your code to set the flops upon assertion > of the async reset. You can tie the async reset pin in the deasserted > state if you'll never use it. GSR is asserted automatically at the end > of configuration and uses the same net as your reset pin. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt." -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27326
If you want to have access to the global reset or global tristate (ie you have a reset pin), you need to use the startup block to tell the tools to hook your reset input to the global reset network. erika_uk@my-deja.com wrote: > > Hi, > > Thanks ray for the reply > Now i am bit confused...so what is the need for the startup block which > has been recommended by xilinx to reset the design > ( well at least for a non virtex type Fpga ). > > regards > > --Erika > > In article <3A156E05.94B4D346@andraka.com>, > Ray Andraka <ray@andraka.com> wrote: > > Erika, > > > > My newreader didn't get your original post. The flip-flops are all > at the > > initial value at the end of reconfiguration (generally '0' unless > explicity set > > to '1' by an init="S", although the FDS, FDSE etc have that init='S' > already on > > them). This is basically as if the global reset was applied even > though you > > don't have the start-up block in your design. So in answer to your > question, > > yes the flip-flops do get set to a known state by configuration, and > no you > > don't need an explicit reset signal to do it. Note that even though > this > > methodology works well and is one I subscribe to, it is likely to get > any ASCI > > designers reviewing your design to scream and jump up and down. > > > > erika_uk@my-deja.com wrote: > > > > > > ooh experts, any input here ? > > > ray, where are you hidding !!!!??? > > > > > > In article <8usdpl$qbl$1@nnrp1.deja.com>, > > > erika_uk@my-deja.com wrote: > > > > I forget to add, is there any prefixed from where i can drive it ? > > > > > > > > In article <8usd7d$pqh$1@nnrp1.deja.com>, > > > > erika_uk@my-deja.com wrote: > > > > > hey, > > > > > > > > > > just basic question. will the reset pulse be > > > generated "automatically" > > > > > after configuration? can i use this pulse to clear some counters > > > > > synchrnously. i don't want to infer the startup because of... > (the > > > > > famous story) > > > > > > > > > > thanks > > > > > > > > > > --Erika > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > > Before you buy. > > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > Before you buy. > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27327
Ray Andraka wrote: > Erika, > > My newreader didn't get your original post. The flip-flops are all at the > initial value at the end of reconfiguration (generally '0' unless explicity set > to '1' by an init="S", although the FDS, FDSE etc have that init='S' already on > them). This is basically as if the global reset was applied even though you > don't have the start-up block in your design. So in answer to your question, > yes the flip-flops do get set to a known state by configuration, and no you > don't need an explicit reset signal to do it. Note that even though this > methodology works well and is one I subscribe to, it is likely to get any ASCI > designers reviewing your design to scream and jump up and down. > Does instantiating a start-up block and then tying its reset input inactive actually disable the global reset ? If so then this should be right way to go if the FPGA is evetually to become an ASIC.Article: 27328
John Larkin wrote: > > We recently made a small change to one of the FPGAs, and it wouldn't > configure. It turns out that the older .RBT files had 283,424 config > bits, and the new ones (from F3.1 software) have 283,432. > Check out Xilinx answer database record 7318; it looks like releases 2.1i SP2 and later pad the 4000 series bitstreams by an extra byte to fix a JTAG startup problem. Brian Davis Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27329
While I could make quite a few comments on this, I think I will just give you the link: http://www.xilinx.com/prs_rls/xilinxwin.htm Philip Philip Freidin FliptronicsArticle: 27330
On Fri, 17 Nov 2000 19:58:22 -0800, Philip Freidin <philip@fliptronics.com> wrote: > >While I could make quite a few comments on this, >I think I will just give you the link: > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > >Philip > >Philip Freidin >Fliptronics Tpd = 7 years? JohnArticle: 27331
Hello, I'm trying to let Virtex-E to communicate using EPP mode with PC's Parallel Port, but I failed in the recent days. I can't build a circuit suitable for their own electric characteristic. Would anyone share his experience to me? Thanks! Info: Parallel Port input is TTL level, but pull-high internally. Output port is open-drain TTL level. Bi-directional port is TTL level. Virtex-E can tolerant 5V with an external 100ohm resistor. Thanks again!Article: 27332
Tough question.
Where I work we use both Xilinx and Altera in a PC NT environment. We use
the latest tools and parts from both companies.
The general consensus for the APEX and VIRTEX families is that both tool
sets as are easy to use and the parts work great.
Five years ago, a lot of engineers thought Altera had the edge. Prior to
Altera's APEX family, Xilinx had the edge.
The software changes about every six months to follow the FPGA technology
advances....
I recently finished a XCV300E design that ran 50 MHz system and 100 MHz
external ZBT SSRAM speeds without any
tool or part problems.
So I would choose based on the following:
1. Number of free copies of software you can obtain from the companies for
your students.
2. OR -- just choose Xilinx! I have stock in the company, and your
students would probably really want to PPR
using the new VIRTEX II parts.
-Bill-
"Rex Fisher" <fisherr@ricks.edu> wrote in message
news:8v4fs0$8ji$1@acs2.byu.edu...
> I teach an introductory-level digital logic course at a junior college. I
> have been using PALs, such as the 16V8 to introduce students to
programmable
> logic. The architecure is simple to understand and the CUPL programming
> language is easy to learn.
>
> I would like to expand this topic to include CPLDs and FPGAs. I am not an
> expert on these devices and must learn them for myself first. Most of the
> textbooks I have looked at use either the Altera or Xilinx software. The
> capabilities of the actual hardware I would use for the class is not as
> important as the usability of the software, because the circuits would not
> be very large or complicated. Evaluation boards that can be used for lab
> projects are available from both companies. The main idea is to get some
> exposure to the design tools and process.
>
> Which software product do you experts think would be the easiest to learn
> and use in an introductory digital circuits course?
>
> Thanks!
>
>
>
>
>
Article: 27333Why not use the Xilinx Webpack? -it will allow your students to use both CPLDs and Spartan-II and Virtex 300E FPGAs - and it's free! Mark. Rex Fisher <fisherr@ricks.edu> wrote in message news:8v4fs0$8ji$1@acs2.byu.edu... > I teach an introductory-level digital logic course at a junior college. I > have been using PALs, such as the 16V8 to introduce students to programmable > logic. The architecure is simple to understand and the CUPL programming > language is easy to learn. > > I would like to expand this topic to include CPLDs and FPGAs. I am not an > expert on these devices and must learn them for myself first. Most of the > textbooks I have looked at use either the Altera or Xilinx software. The > capabilities of the actual hardware I would use for the class is not as > important as the usability of the software, because the circuits would not > be very large or complicated. Evaluation boards that can be used for lab > projects are available from both companies. The main idea is to get some > exposure to the design tools and process. > > Which software product do you experts think would be the easiest to learn > and use in an introductory digital circuits course? > > Thanks! > > > > >Article: 27334
Here are the numbers of 4-, 5-, and 6-bit error patterns that go undetected by the three 16-bit CRCs I mentioned, for each of three message sizes N (in ***bits***): N errors BCH(255,239) CRC-16 CRC-CCITT 48 4 0 140 48 5 19 0 0 6 167 2035 450 76 4 0 625 138 5 284 0 0 6 3395 24503 7205 255 4 0 14755 5280 5 134946 0 0 6 5622750 12213464 11005158 These numbers are based on enumerating all possible error patterns. The first time I did it, it took 11 days on an 8MHz Compaq portable (Turbo Pascal). None of these admit two bit patterns, as long as the number of bits is limited to 255 for BCH(255,239) 32,767 for CRC-16 and CCITT The standards detect all odd-bit error patterns (as would the extended BCH code, which I did not evaluate). Based on these numbers, I estimated the probability of undetected error for two BEPs p. For the estimate, I assumed the fraction of undetected error patterns was 2^-16 for all patterns with 7 or more bits in error. p N BCH(255,239) CRC-16 CRC-CCITT 1.3e-03 48 6.78e-14 3.78e-10 1.29e-10 76 9.77e-13 1.63e-09 3.59e-10 255 3.82e-10 3.04e-08 1.09e-08 1.0e-04 48 2.22e-16 1.42e-14 5.00e-15 76 3.36e-16 6.24e-14 1.40e-13 255 2.38e-15 1.44e-12 5.16e-13 The exponents occurring with nonzero (=1) coefficients in the generator polynomial for BCH(255,239) are 16,14,13,11,10,9,8,6,5,1,0. -Dan On Fri, 17 Nov 2000 06:56:44 GMT, Dan Kotlow <dank@micrologic.com> wrote: > >Here's what I think I know: > >If I recall correctly, the standards CRC-16 and CRC-CCITT are good up >to 32,768 BITS (including the CRC itself). > >For shorter messages (up to 255 BITS) , one can use the (16-bit) >generator polynomial of the code BCH(255,239). This detects ANY four >bits in error. It also has a much better weight distribution (# of >undetected 5-bit errors, 6-bit errors, etc.) than the standards, when >within its length limits. > >To this, you can add an overall parity bit and get an extra bit of >detection in a 256 bit packet (still only 239 data bits). > >I'll look up my figures at the office tomorrow (and the polynomial) >and post again. > >-Dan >Article: 27335
I have used Altera's LPM_RAM_DQ core RAM's many times without too much hassle, but for this design I get a strange result: The design is targeted for 10K30 which supports 6 EAB blocks each 2K bits. My design as a RAM of 768 x 16. This should map to 3 x (2 x (256x8)) EABS - 12288 bits. When compiling using Max 9.6 the correct number of bits are identified, the depth is 768 x 16 but the tool cannot fit the device as it reports that 8 EABS are required. The EABS are only used for the RAM. It is the only EAB reported in the fitter file. Any suggestions? The 10 bit address vector with an integer range 0 to 767 also leads to a to a simulation error using Modelsim (although theoretically this is correct). The address to the ram is an integer of range 0 to 767. The address from the test bench (a uP's bus) is a std_logic_vector(19 downto 0). The mapping for the ram is RamAddr <= to_integer(BusAddr(9 downto 0)); AnthonyArticle: 27336
Philip Freidin <philip@fliptronics.com> writes: > While I could make quite a few comments on this, > I think I will just give you the link: > > > http://www.xilinx.com/prs_rls/xilinxwin.htm I'm sure this is all in the society's best interest. After all, that's what patents are for. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27337
Rex,
Perhaps your students will learn a valuable real world lesson from
Mark -- after all of the arguments are heard about how great a certain
vendor's tools are, most of the time the decision boils down to cost!
-Simon Ramirez, Consultant
Synchronous Design, Inc.
********************************************************************
"Mark Harvey" <mark.harvey@iol.it> wrote in message
news:8bqR5.81326$BF.2913634@news.infostrada.it...
> Why not use the Xilinx Webpack? -it will allow your students to use both
> CPLDs and Spartan-II and Virtex 300E FPGAs - and it's free!
>
>
> Mark.
>
> Rex Fisher <fisherr@ricks.edu> wrote in message
> news:8v4fs0$8ji$1@acs2.byu.edu...
> > I teach an introductory-level digital logic course at a junior college.
I
> > have been using PALs, such as the 16V8 to introduce students to
> programmable
> > logic. The architecure is simple to understand and the CUPL programming
> > language is easy to learn.
> >
> > I would like to expand this topic to include CPLDs and FPGAs. I am not
an
> > expert on these devices and must learn them for myself first. Most of
the
> > textbooks I have looked at use either the Altera or Xilinx software.
The
> > capabilities of the actual hardware I would use for the class is not as
> > important as the usability of the software, because the circuits would
not
> > be very large or complicated. Evaluation boards that can be used for
lab
> > projects are available from both companies. The main idea is to get
some
> > exposure to the design tools and process.
> >
> > Which software product do you experts think would be the easiest to
learn
> > and use in an introductory digital circuits course?
> >
> > Thanks!
> >
> >
> >
> >
> >
>
>
>
Article: 27338Also try looking a Quicklogic PCI FPGA. Has a PCI hard core and OTP, I am looking at these devices now. <cadmanager@my-deja.com> wrote in message news:8v3j7e$klk$1@nnrp1.deja.com... > To use onboard FPGA with PCI bus, YOU MUST have 1 device that work on > PCI POWER ON. > > It means many solutions: > > 1: got a specific PCI compliant interface device > 2: got A OTP FPGA (like ACTEL) who's got a PCI IP or customer PCI > interface > 3: got FPGA whith EEPROM (like FLEX10K) " " " > > So, then, all others FPGA on your card, could be programmed across PCI > bus. > > Yes it's possible to configure the PCI interface FPGA during POWER ON > of PCI bus. Just look for the maximum configuration time of the FPGA, > and compare whith PCI Boot Delay. > > Best regards > > > In article <3A1536C3.9407534D@rsd.rsd.de>, > Wolfgang Kufer <wolfgang.kufer@rsd.rsd.de> wrote: > > Hi All, > > > > I want to use an FPGA as PCI target. > > > > What are the possibilities of configuring this device? > > Must I use an onboard flash/eeprom device as configuration memory or > is > > there any way to download the configuration data via the pci bus? > > > > At what time during boot the pci target must be ready or is it > possible > > to reconfigure the target during runtime? > > > > Thanks, Wolfgang > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27339
There is a Xilinx document on this, I think it is implemented in 3 CLBs. Try searching Xilinx web site for "Manchester Decoder", I believe it appeared in the "XCELL" journal. Cameron. "Hal Murray" <murray@pa.dec.com> wrote in message news:8un25e$b3s@src-news.pa.dec.com... > > > Anyone know of a text that shows a decoder of Manchester encoded data? > > I don't know of a good/simple text. If you have access to a good > technical bookstore, you might try browsing. I'd look in the index. > It might be called Biphase rather than Manchester. > > > What speed are you running at? > > If you can easily get a 10X clock, then you can build a small > state machine to watch for transitions. A bit of fiddling around > with paper and pencil should be enough for you to work it out. Just ignore > the transitions between bit cells and watch for a transition near the middle > of a bit cell. When you find one, reset the timing and send out a > 0 or 1. > > If you have a fast data stream, you probably want to use an external > chip with a PLL to do the clock recovery. > > > You can push the speed some by decoding 2 (or more) bits in parallel. > You need a high speed clock at the front end and the state machine > gets more complicated. > > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27340
comp.arch.fpga re: manchester decoder Many thanks for the suggestions for data on decoding Manchester bit streams. The article in Xcell was particularly helpful. HulArticle: 27341
I think that synthesizer tries to create RAM slices with maximum address range for each of ones. Each slice has to occupy power of 2 address space. Nearest cover value for 768 is 1024. In your case synthesizer creates 8 slices with 1024 bits in each. To avoid this you should instantiate 3 modules with 256x16 size each and create additional decoder for higher 2 address bits. Regards, Valery Serebrianski, Boston University Physics Department In article <3a163942.0@news1.mweb.co.za>, "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za> wrote: > I have used Altera's LPM_RAM_DQ core RAM's many times without too much > hassle, but for this design I get a strange result: > > The design is targeted for 10K30 which supports 6 EAB blocks each 2K bits. > My design as a RAM of 768 x 16. This should map to 3 x (2 x (256x8)) EABS - > 12288 bits. > When compiling using Max 9.6 the correct number of bits are identified, the > depth is 768 x 16 but the tool cannot fit the device as it reports that 8 > EABS are required. The EABS are only used for the RAM. It is the only EAB > reported in the fitter file. Any suggestions? > > The 10 bit address vector with an integer range 0 to 767 also leads to a to > a simulation error using Modelsim (although theoretically this is correct). > The address to the ram is an integer of range 0 to 767. The address from the > test bench (a uP's bus) is a std_logic_vector(19 downto 0). The mapping for > the ram is RamAddr <= to_integer(BusAddr(9 downto 0)); > > Anthony > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27342
Some additional comments. More effective way is to use two RAM blocks - 512x16 and 256x16. Highest address bit will serve as block select. Of course you have to use multiplexer for output data from RAM blocks. In that case it will be 16x2 -> 16 bits. That's the reason for using maximum address range for each RAM slice :-) Valery Serebrianski, Boston University Physics Department In article <8v65gh$jn7$1@nnrp1.deja.com>, serebr@my-deja.com wrote: > I think that synthesizer tries to create RAM slices with maximum > address range for each of ones. Each slice has to occupy power of 2 > address space. Nearest cover value for 768 is 1024. > In your case synthesizer creates 8 slices with 1024 bits in each. > To avoid this you should instantiate 3 modules with 256x16 size each > and create additional decoder for higher 2 address bits. > > Regards, > Valery Serebrianski, > Boston University Physics Department > > In article <3a163942.0@news1.mweb.co.za>, > "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za> wrote: > > I have used Altera's LPM_RAM_DQ core RAM's many times without too much > > hassle, but for this design I get a strange result: > > > > The design is targeted for 10K30 which supports 6 EAB blocks each 2K > bits. > > My design as a RAM of 768 x 16. This should map to 3 x (2 x (256x8)) > EABS - > > 12288 bits. > > When compiling using Max 9.6 the correct number of bits are > identified, the > > depth is 768 x 16 but the tool cannot fit the device as it reports > that 8 > > EABS are required. The EABS are only used for the RAM. It is the only > EAB > > reported in the fitter file. Any suggestions? > > > > The 10 bit address vector with an integer range 0 to 767 also leads > to a to > > a simulation error using Modelsim (although theoretically this is > correct). > > The address to the ram is an integer of range 0 to 767. The address > from the > > test bench (a uP's bus) is a std_logic_vector(19 downto 0). The > mapping for > > the ram is RamAddr <= to_integer(BusAddr(9 downto 0)); > > > > Anthony > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27343
Zhen Luo wrote: > > Hi, guys > > I am writing my thesis now and one of my reviewers had a different view > about FPGA clock rate. I felt FPGA could not achieve the general-purpose > processor like clock rate (> 1GHz right now) because FPGA's structure and > its components (like SRAM-based look-up table, programmable wiring > switchbox) are just not fit for high clock rate. My reviewer pointed out > that FPGAs couldn't achieve the general-purpose processor like clock rate > because they had to be cost-effective. If Xilinx had a foundry like intel > did and they would go all for the clock speed, they could make it to the > similar range. I think there is some truth in it, but I still don't think > FPGA could be that fast even if they do so. Lets face it when you use 16 or more transistors to emulate a 2 input nand gate, timing really slows any way you define it. My own informal view is that Processors will become more like the current FPGA model. Quick but limited complex logic (As a hardwired building block) with long interconnect times. This I think is where hardware design is going. > I would really like to hear your thoughts on this. Meanwhile, I also have a > question, why is the I/O clock rate of Xilinx chips much slower than their > internal clock rate? Would that finally become the bottleneck for improving > the overall clock rate for FPGA applications? I think this true on all FPGA's.I think most people prefer shower I/O where possible as gives fewer headaches in design. Ground Bounce is one think that comes mind. > Also, since the clock rate on FPGA varies between applications, let's just > assume that we have a design that is highly pipelinable, like an > array-multiplier. > Are the control signals pipelined locally too? > -- Zhen Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 27344
What about the green mountain 68hc11 core? I don't know enough about what you are doing to say for sure if it will help you but the cost was right (Free) and it seems to work fairly well. I have one just about set to synthesize a complete system using Xilinx tools. (COREGEN and Foundation 2.1i). For a relative amateur it only took me about a couple of 8 hour days (actual total time spread out over a couple of weeks) to get it up and running (almost... I have a minor bus contention issue to resolve.) Good luck. "S. Ramirez" wrote: > I just found out that Synopsis wants $80K for a one year license of > their Mot 5307 or 8260 instruction set model! I consider this an ARM and a > leg!! > My client will never go for this. I guess I'm back to just simulating > the FPGAs and memories on the board, unless one of you out there knows of a > cheaper alternative. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > ******************************************************************** > > Does anyone here know of sources for microprocessor Verilog or VHDL > > behavioral models? > > I am doing a board level simulation that involves FPGAs, memories, > > peanut components, and a Mot ColdFire microprocessor. I checked with Mot > > about providing a C behavioral model or an encrypted Verilog/VHDL > behavioral > > model, and they referred me to the Big S -- Synopsis. This means that it > > will cost an ARM and a leg, and I'm not talking about an ARM processor! > > Does anyone know of alternatives? > > -Simon Ramirez, Consultant > > Synchronous Design, Inc.Article: 27345
Used to be a company called LMSI that made a hardware modeller, where one mounted the uut part on a prototype board, and stimulus was sent to the part from the simulator, and a response from the part was sent back to the simulator. This company was bought by Logic Modeling, which was then bought by the big S. I would presume that the cost of the hardware has come way down, but is still most likely 5-6 figures, but perhaps the cost could be spread over several designs which used different processors/chips. BTW, back then, it was difficult to use with dynamic parts, but with a lot more parts fully static, perhaps this is no longer an issue. Good luck in your search! In article <3A170C00.B1F02D0F@egr.msu.edu>, Terry Hicks <hicksthe@egr.msu.edu> wrote: > What about the green mountain 68hc11 core? I don't know enough about what you > are doing to say for sure if it will help you but the cost was right (Free) and > it seems to work fairly well. I have one just about set to synthesize a > complete system using Xilinx tools. (COREGEN and Foundation 2.1i). For a > relative amateur it only took me about a couple of 8 hour days (actual total > time spread out over a couple of weeks) to get it up and running (almost... I > have a minor bus contention issue to resolve.) Good luck. > > "S. Ramirez" wrote: > > > I just found out that Synopsis wants $80K for a one year license of > > their Mot 5307 or 8260 instruction set model! I consider this an ARM and a > > leg!! > > My client will never go for this. I guess I'm back to just simulating > > the FPGAs and memories on the board, unless one of you out there knows of a > > cheaper alternative. > > -Simon Ramirez, Consultant > > Synchronous Design, Inc. > > > > ******************************************************************** > > > Does anyone here know of sources for microprocessor Verilog or VHDL > > > behavioral models? > > > I am doing a board level simulation that involves FPGAs, memories, > > > peanut components, and a Mot ColdFire microprocessor. I checked with Mot > > > about providing a C behavioral model or an encrypted Verilog/VHDL > > behavioral > > > model, and they referred me to the Big S -- Synopsis. This means that it > > > will cost an ARM and a leg, and I'm not talking about an ARM processor! > > > Does anyone know of alternatives? > > > -Simon Ramirez, Consultant > > > Synchronous Design, Inc. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27346
Greg Neff wrote:
>
> In article <8uuvue$8iq$1@news.utdallas.edu>,
> V Ram <ipickledthefigsmyeslf@mrbourns.com> wrote:
> (snip)
> Anyone
> > use ViewDraw?
>
> Yes, we use ViewDraw. I have been told that you can mix VHDL and
> schematics with ViewLogic, but I have never tried it. You probably
> need to generate an EDIF netlist out of the synthesis tool, and build a
> schematic symbol wrapper for the netlist.
Hi Greg,
I *think* you can do that with Viewlogic if you have the fancier
simulator that can mix the VHDL and the Viewlogic netlists. I don't
have that license, just regular Viewsim, so I'm not sure, haven't
actually tried it myself. Here's what it says in the help file:
In addition to stand alone VHDL analysis
and simulation, Workview Office also supplies
ViewSim the Workview Office gate-level digital
simulator and VCS for Windows. You use ViewSim
to simulate schematic-based digital designs.
VCS for Windows is the Workview Office Verilog
simulator. You use VCS to simulate Verilog designs.
You can use each of these simulators independent
of each other or you can use them in conjunction
with one another, this is Workview Office Digital
Fusion. With Digital Fusion you can concurrently
simulate designs containing any combination of
Verilog, VHDL, and/or logic primitives.
rk
Article: 27347> Just look for the maximum configuration time of the FPGA, > and compare whith PCI Boot Delay. Be careful with that. There is no spec for this in the 2.1 spec. Even though the later spec has this number defined, keep in mind that if you are in a standard PC, the BIOS doesn't go through PCI configuration until after BIST and other BIOS boot code, which typically delays the configuration process by than 5 seconds even on the fastest machines. Easily enough time to configure even a very large FPGA.Article: 27348
Here's a spec'smanship issue... Reference the Virtex-E Rev 1.7 spec. Page 2 claims the XCV2000E has 43,200 Logic Cells. Now, go to page 6, where they clearly define a logic cell (LC) as: "An LC includes a 4-input function generator, carry logic, and a storage element." OK, so that should mean that there are 43,200 storage elements in the XCV2000E part...well, there aren't. There are 38,400. Why the 4,800 difference? Well, it appears the people who figure out the number of 'logic cells' don't read the definitions of what a logic cell is. Apparently, they considered each 'slice' (which is two logic cells) to contain 2.25 logic cells, NOT two...because of the "Additional Logic" as described in Figure 5 on page 7. The calculated 19,200 slices times 2.25, which happens to equal 43,200. Therefore, each of their 'logic cells' does not contain a 'storage element' as claimed in the spec.Article: 27349
Hello! I have a few questions regarding synthesizing VHDL... Is there a website or document that describes what parts of VHDL are/aren't synthesizable? I have the Designer's Guide to VHDL (Ashenden) but I have no clue how synthesizable his code is... Typically the code I've written is simple enough that is has synthesized(MaxPlus II & FPGA Express), but I might want to use variables or do a few other things and I don't know what's suggested or not. My biggest complaint about Ashenden's book is that he doesn't really give you clues as to what design method(s) you should take if you want your designs to be synthesizable. Any hints, tips, website or recommended books would be nice to know about. Really any website that has code that *has* been synthesized would be fantastic. I know about the Leon SPARC core and the Hamburgh VHDL archive but lots of the models there aren't synthesizable. Thanks, V Ram.
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