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Hi Ian, I appreciate your commments on fpga security. I am a student at uni and find this very interesting as these considerations are never mentioned at university. I also am aware that xilinx suggest programming the device in circuit and using a backup battery to permanently keep alive the configuration. I can see that this approach is only useful if the device is not to be reconfigured for different functions, but is htere any other problems that may arise. Cheers, Cameron Watt Ian McLaren wrote: > John, > > On Feb 6, John Larkin <jjlarkin@worldnet.att.net> wrote: > >>I think I've invented a neat circuit for a specialized digital PLL, and > >>of course I want to keep it proprietary. So if I make a product using a > >>Xilinx FPGA, the config bitstream can't be hidden from a competitor who > >>gets his greedy hands on one. I assume that an outright copy is a > >>copyright violation, so I'm not too worried about that. So here's the > >>issue: Is it feasible that someone could decompile the stream and > >>recover the circuit CONCEPT? Are there any tools to help them do this? > >>Would it be easy, or an enormous task? > > Pretty much every FPGA designer faces the same problem at one time or > another, I think. My understanding is that it's very difficult to > decompile the Xilinx bitstream (unless one expends a huge amount of > resources, which is not worth it unless it's a very high volume / high > profit design in which case *you* could afford to use ASICs to protect > it!). I would be more worried about unscrupulous competitors creating a > direct copy and using it in their products. Nailing transgressors on a > copyright violation can be costly and time-consuming (it's similar to > the situation with patents, but perhaps harder to document). If you sell > one device to an unscrupulous organization and they copy the design for > in-house use, you may never find out about it and you lose potential > sales. > > My attempts to solve the problem have involved making the parts VERY > hard to copy. I design and build low-volume scientific instruments, > usually connected to a PC via the parallel port. I have successfully > used the following methods to prevent copying: > > A) Put a CPLD (I usually use a Xilinx XC95108) on the same board, with a > few lines connected to the FPGA --- in my case, the data bus passes > through the CPLD on its way to the host PC. Implement a non-trivial > state machine in the CPLD, and a matching one in the FPGA. Use this as > an XOR mask for switching data (and even control signals, but be > careful) entering and leaving the FPGA. Because the two state machines > track, everything still works OK because it's XORed twice by the same > mask and every path switch is corrected in the other chip. If your > competition tries to figure out the FPGA structure, or builds a copy, > they will get garbage unless they can also replicate the CPLD, which is > MUCH harder. Reverse engineering a chip whose data and control lines > seem to wander among the pins at random will drive them to the brink of > insanity. > > B) Put a Dallas DS2401 Silicon Serial Number chip next to the FPGA, and > have the latter read the 64-bit ID number after configuration. Use this > as a data or control line XOR mask as above, with a matching XOR mask as > part of the design. Once again, anyone copying the chip design will get > garbage unless they have the SSN also. This also IDs the board as well, > since Dallas guarantees that no two parts give the same 64-bit ID > number. This DOES require that each FPGA be programmed slightly > differently (it could be done as a RAM or ROM initialization value), so > only works really well for low volume products. It also pays to hide > the SSN chip to confuse the opposition, since otherwise they can read > the 64-bit ID and possibly emulate it. A DS2401P (TSOC package) fits > quite nicely under a PLCC FPGAsocket (if your FPGA design can possibly > stand using a socket, that is), or else you can hide it under a > convenient soldered-in component and they'll never guess it's there if > the traces are also well-disguised.... > > C) ID the board using either a DS2401 as above, or a CPLD with a few > macrocells programmed as an ID number, and match this with your > software. If you are loading the FPGA via an embedded microprocessor or > a host PC, the running software can require the ID number to agree. This > means that even if they copy the FPGA bitstream, the software that uses > the FPGA will not run without the correct ID. > > Please feel free to contact me via E-mail if you would like more details > of any of the above methods. There IS a limit to what I will reveal in a > public forum! > > If Xilinx et al would just put a small CPLD array on every FPGA die, > this problem could be solved using the above methods but without needing > a companion chip. > > Hope this has been of some interest to you, > > Regards, > > Ian McLaren > President > McLaren Research > Mountain View, CA 94043 > imclaren@california.com > > -----------== Posted via Newsfeeds.Com, Uncensored Usenet News ==---------- > http://www.newsfeeds.com/ The Largest Usenet Servers in the World! > -----------== Over 66,000 Groups, Plus a Dedicated Binaries Server ==----------Article: 14901
Hello, I am using FPGA express to implement vhdl macros. These macros are inserted in a schematic via "create macro from xnf netlist" option. The problem is that for every macro that including a global reset Express infer a STARTUP (XC4000 have one STARTUP only) . I think that it can be avoided creating a top level vhdl including all the macros, but I want independent macros . Are there any other options to avoid GSR infer? TIA -- =================================================================== Sergio A. Cuenca Asensi Dept. Tecnologia Informatica y Computacion (TIC) Escuela Politecnica Superior, Campus de San Vicente Universidad de Alicante Ap. Correos 99, E-03080 ALICANTE ESPAŅA (SPAIN) email : sergio@dtic.ua.es Phone : +34 96 590 39 34 Fax : +34 96 590 39 02 ===================================================================Article: 14902
DesignPRO (www.designpr.com) is an engineering design organization, specializing in Telecom Solutions in Silicon. DesignPRO offers a complete spectrum of product development services, including system design, chip and board specification, FPGA and ASIC design and verification, PCB design and manufacturing, DSP coding, firmware and software development, and hardware and software integration testing. DesignPRO specializes in digital design for communication applications, with experience and reusable blocks in the following areas: · SONET - OC3, OC12, OC48 (ATM and Packet over SONET); · High speed access products, xDSL, T1/E1, Cable Modem; · ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), Ethernet, PCI, VME; · Wireless - CDMA, GPS, LMDS, PCS. Our specialty is FPGA and ASIC development and we provide a full turnkey design service using industry leading design tools that incorporate support for multiple vendors. This service is strengthened by design methodologies that have been developed as a result of many years of experience. These design practices ensure a consistent style that maximizes readability and reusability. Our library of internally generated cores often provides the critical value of cutting the time to market, while reducing the risks associated with new designs. DesignPRO's impressive list of customers includes some of the most reputable communications companies in the world, including Nortel Networks, Newbridge Networks, Ascend Communications, Motorola, Applied Micro Circuits, Arris Interactive and Tundra Semiconductor. For additional information, visit our website at www.designpr.com Andrew Bunsick General Manager DesignPRO Inc. abunsick@designpr.com (613) 596-5030Article: 14903
Zhen Luo ha scritto nel messaggio <36D37DA4.83506E8F@ee.princeton.edu>... >Hi, > >I read the following article on EE times today. What do you think about >it? I think the problems they mention in this article have always been >there, but it seems that this is the first time people really use the >word "dark future" for programmable logic. What do you think? ... long article saying, more or less, that the communications and networking companies are leaving FPGAs looking for the higher speed and lower cost of ASICs, at least for high performance (speed) and high volume (cost) products. The article also says that the comm and net industries would like to include FPGA blocks in their ASICs My comment is simply that as soon as a product matures, going from programmable solutions to "hard" solutions is simply natural. But other not-so-mature markets will arise, replacing the ones that are leaving the FPGA approach now. Getting FPGA blocks built into standard ASICs is not easy: usually the enormous need for connectivity of an FPGA imposes many levels of metal interconnections on the chip (5 or 6 levels, if I remember well, in 10k parts from Altera). This is usually in contrast with ASICs, that normally go for 2 or 3 levels to keep costs down. So, trying to build an FPGA block in a 2-metal ASIC would yeld a very poor FPGA, while using 5 metals for an ASIC would yeld an expensive ASIC. So I think that a "true FPGA" in an ASIC will remain a dream for a long time to come... Just my 0.02 Euro. Aldo Mozzi aldo at protec dot itArticle: 14904
Well, most of the stuff said in the article was known before. It was never an intent to replace ASICs with FPGAs. All FPGA vendors have always stressed that the main strength is in time-to-market which makes FPGAs useful in prototyping and early stages of production. On a long run ASIC pays off, but it is tough to know in advance which product will live sufficiently long. The main place for FPGAs is in R&D labs and early-stage/low-volune production and it will stay this way unless the run-time reconfigurable computing gets onto the main stream when things might change dramatically. Ilija Hadzic University of PennsylvaniaArticle: 14905
Hopefully a simple question: I'm trying to develop an fpga_shell synthesis script for a XC40150XV using Synopsis 1998.08 FPGA compiler (Solaris) and Alliance 1.5i SP1. The synlibs utility doesn't seem to support the XV parts. What are the correct target and link libraries to use? There are no xprim*xv.db files in $XILINX/synopsys/libraries/syn directory. There is a $XILINX/xc4000xv directory with reasonable looking files. I reinstalled Alliance from scratch last night being careful to select XV parts. When the CAE CD installed, it reported support for XV during the install. What's up? I can target a 4085, but can't target anything bigger? What's the trick? I've been all over the Xilinx and Synopsys pages with no luck. Thanks in advance, Brian Schott bschott@isi.eduArticle: 14906
Hi, 2 years ago, I have done a project using a FPGA (XC4002A). All work fine and I presently looking to put my .bit in a serial ROM. Presently, I download each time the .bit file using the serial port. But, I have to format the .bit to a .hex file accepted by the ROM programmer. My problem is that new Xilinx software don't support XC4002A and I am not able to transform my .bit to a .hex file. Anyone can help me??? Steve Vallerand svallera@gel.ulaval.caArticle: 14907
Hi all, Does anybody knows any way that to do compilation in batch mode in maxplus2? Thanks in advance JasonArticle: 14908
It seems to me that the marketplace is beginning to call time on the classic FPGA architecture. Every year process technology lets chip vendors put more 'stuff' on a chip but every 5 to 10 years this scaling changes the character of this systems which are being implemented enough so that the entire architecture needs to be re-evaluated. It happened with PAL's and PAL derivatives - after a while just putting on more product terms or macro-cells did not help. Now its starting to happen to FPGA's: just adding more LUT's and more wires is not going to do it any more. That does not mean that the FPGA vendors are going to lose money immediately: in fact they may well do better than ever as the technology gets into the mature phase. My view is that the architecture will split off in two ways to take advantage of the potential of the process technology: 1. ASIC's with FPGA blocks. This lets customers build a high volume solution with the level of programmability required by their market. High volume products need programmable logic but they can't afford single chip FPGA's. The question is can the FPGA vendors own this market or will the FPGA get reduced to just another core. 2. Specialist computing. Computing will always eat as much silicon as you can throw at it. This is the place where an FPGA vendor can sell catalog parts. And there are real advantages to custom computing. But there is a big problem: you cannot compete in this market with classic FPGA's. You have to build something new which has some features of an FPGA and lots of features from conventional processors and you have to redefine the company to sell compute power, not programmable ASIC's. The question is whether the FPGA companies are entrepreneurial enough to risk today's business addressing the opportunities. If they do not they will be left with a 'cash cow' product in a shrinking market. Tom Kean.Article: 14909
Evan Speight <espeight@rice.edu> wrote: : Hello, I am using Xilinx's Design Manager M1.4.12. : Can somebody explain to me the Place and Route Report output? : (Should PAR be the sum of Place and Route or not?) : Thank you in advance, : Bill Balabanos balab@rice.edu : ---------------------------------------------------------------------------- : -------------- : Sample output: : Total REAL time to Placer completion: 12 secs : Total CPU time to Placer completion: 8 secs : ... : Total REAL time to Router completion: 17 secs : Total CPU time to Router completion: 13 secs : ... : Total REAL time to PAR completion: 19 secs : Total CPU time to PAR completion: 14 secs The times listed are elapsed times from the start of the PAR run. Time to router completion includes placer time if it was run, which in this case it was. We are probably going to change the router time to just list time spent in the router. Then the PAR time will be the sum of the two (plus design load, report generation, etc.) Carl Stern XilinxArticle: 14910
Any folks run into any JTAG gotchas with pulling up the tdi and tclk pins?Article: 14911
Mr. Bunsick, As you were getting the flavor of comp.arch.fpga by reading the news for a few days, did you notice a lot of purely commercial ads? I think not. It should be obvious that this is a technical news group for giving and receiving technical help. Your article did neither. It's just a long ad and I hope it backfires. Don't you realize just about everyone in comp.arch.fpga is a business that could easily post a similar ad for their company? How useful would the group be then? Please keep your blatant, ads with no hint of redeeming technical content to some other medium. Dave Decker Diablo Research Co. LLC ___________________________________________________ "Andrew Bunsick" <abunsick@designpr.com> wrote: >DesignPRO (www.designpr.com) is an engineering design >organization, specializing in Telecom Solutions in Silicon. >DesignPRO offers a complete spectrum of product >development services, including system design, chip and >board specification, FPGA and ASIC design and verification, >PCB design and manufacturing, DSP coding, firmware and >software development, and hardware and software integration >testing. > >DesignPRO specializes in digital design for communication applications, >with experience and reusable blocks in the following areas: > >· SONET - OC3, OC12, OC48 (ATM and Packet over SONET); >· High speed access products, xDSL, T1/E1, Cable Modem; >· ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), > Ethernet, PCI, VME; >· Wireless - CDMA, GPS, LMDS, PCS. > >Our specialty is FPGA and ASIC development and we provide a full >turnkey design service using industry leading design tools that >incorporate support for multiple vendors. This service is >strengthened by design methodologies that have been developed >as a result of many years of experience. These design practices >ensure a consistent style that maximizes readability and >reusability. Our library of internally generated cores often >provides the critical value of cutting the time to market, while >reducing the risks associated with new designs. > >DesignPRO's impressive list of customers includes some of the most >reputable communications companies in the world, including Nortel >Networks, Newbridge Networks, Ascend Communications, Motorola, >Applied Micro Circuits, Arris Interactive and Tundra Semiconductor. > >For additional information, visit our website at www.designpr.com > >Andrew Bunsick >General Manager >DesignPRO Inc. >abunsick@designpr.com >(613) 596-5030 > > Dave Decker Diablo Research Co. LLC Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 14912
We are looking to buy some of these Motorola FPGA's (160PQFP) . If you have surplus stock please contact Michal @ 212-9625404Article: 14913
In article <36D488CD.4A305863@zoran.com>, Jason Chan <jason@zoran.com> wrote: > Hi all, > Does anybody knows any way that to do compilation in batch mode in > maxplus2? > > Thanks in advance > Jason > > For Maxplus2 version 8.2 or higher there is a dos command you can call to compile your FPGA (place & route). What you need is to do is go to the dos prompt and directory where your .acf and design files are stored. In the maxplus installation directory is a file called maxplus2.exe which is the command line version. Check if your path includes the maxplus directory. In your design directory type c:\projects> maxplus2 -h > maxplus2.txt to compile, need chip.acf and chip.edf of tdf/vhd > maxplus2 -compile chip To create programming files (As converting the SOF) you will need the .fcf file > maxplus2 -convert -rbf "chipv1.rbf" chip Hope this helps. Bert de Jong Xyratex e-mail : bjong@my-dejanews.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14914
Jim wrote in message <36D4AA69.E95CB74@erols.com>... >Any folks run into any JTAG gotchas with pulling up the >tdi and tclk pins? The only problems I've experienced have been with the /TRST pin, which seems to be interpreted differently by different devices. Some like it pulled up when the JTAG port isn't being used, some like it pulled down. Can lead to operational inconsistencies. Mike H.Article: 14915
Hi I am trying to learn to use the ABEL HDL language included with the Xilinx Foundations Base package. Xilinx tech support tells me that the only documentation on this language is in the help files included with the software. I am new to HDL and am having trouble getting started with this. Does anyone know where I can learn more about this language and is it worth using, or should I pay to get the VHDL upgrade? I have been experementing with the state machine editor and looking at the ABEL code it generates. I have not been able to get a registered output to hold its value when the machine enters a new state. Xilinx tells me to define all the outputs in every state. Is this true? According to one of their tutorials, designs coded in VHDL will hold the outputs. Its hard to believe that VHDL will hold the values and ABEL won't.Article: 14916
Sorry, I don't know of any place on the web but there is a book on using ABEL in programmable logic designs. See http://www.optimagic.com/books.html#Abel for more information. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Don Brouse wrote in message <7b3pc1$kl7$1@news1.fast.net>... >Hi >I am trying to learn to use the ABEL HDL language included with the Xilinx >Foundations Base package. Xilinx tech support tells me that the only >documentation on this language is in the help files included with the >software. I am new to HDL and am having trouble getting started with this. > >Does anyone know where I can learn more about this language and is it worth >using, or should I pay to get the VHDL upgrade? > >I have been experementing with the state machine editor and looking at the >ABEL code it generates. I have not been able to get a registered output to >hold its value when the machine enters a new state. Xilinx tells me to >define all the outputs in every state. Is this true? According to one of >their tutorials, designs coded in VHDL will hold the outputs. Its hard to >believe that VHDL will hold the values and ABEL won't. > >Article: 14917
"Don Brouse" <dcbrouse@yahoo.com> wrote: >Hi >I am trying to learn to use the ABEL HDL language included with the Xilinx >Foundations Base package. Xilinx tech support tells me that the only >documentation on this language is in the help files included with the >software. I am new to HDL and am having trouble getting started with this. > >Does anyone know where I can learn more about this language and is it worth >using, or should I pay to get the VHDL upgrade? > >I have been experementing with the state machine editor and looking at the >ABEL code it generates. I have not been able to get a registered output to >hold its value when the machine enters a new state. Xilinx tells me to >define all the outputs in every state. Is this true? According to one of >their tutorials, designs coded in VHDL will hold the outputs. Its hard to >believe that VHDL will hold the values and ABEL won't. > > Hi, I use ABEL extensively, and have for years. I like it. It is possible to get a state machine to hold it's outputs. It would be somewhat worthless if it didn't. Could you either post your code, or send it to me via email? I would be glad to look at it, and see if I can spot your problem. I enjoy designing state machiones with abel. I think it is a very elegant way to design synchronous systems, and fits the architecture of an FPGA very well. Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://www.devili.iki.fi/cpm PRIMARY US MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm SECONDARY US MIRROR AT : http://CPM.INTERFUN.NETArticle: 14918
Don, I used to use XABEL as it came from Xilinx. It's ability to hold its outputs is one reason I switched to ABEL from CUPL. I'm trying to remember how I did it. Seems to me that you have a choice of D or JK or RS flip flops for the registers, and if you choose JK or RS flip flops it preserves the states. I think JK is the way to go. I'll look it up in the old Xilinx XABEL book when I get to work and repost if necessary. Dave Decker Dave Decker Diablo Research Co. LLC Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 14919
>I am trying to learn to use the ABEL HDL language included with the Xilinx >Foundations Base package. Xilinx tech support tells me that the only >documentation on this language is in the help files included with the >software. I am new to HDL and am having trouble getting started with this. Do you have the "Practical Xilinx Designer Handbook?" It comes with the student version of Xilinx's tools, and its examples are in ABEL. It has a decent, concise summary of ABEL in one of its appendices. The author has since posted the same examples in VHDL on his web site, which is useful for people transitioning from ABEL to VHDL. >Does anyone know where I can learn more about this language and is it worth >using, or should I pay to get the VHDL upgrade? If you're going to be doing anything but the simplest of designs, I think it's quite worthwhile to learn VHDL. VHDL is a far more powerful language overall. It can be quite annoying initially (particularly due to its being a very strongly typed language), but I'll vote for "ugly and powerful" over "good looking and average" any day. VHDL doesn't really actually compete directly with ABEL -- it competes with Verilog. >I have been experementing with the state machine editor and looking at the >ABEL code it generates. I have not been able to get a registered output to >hold its value when the machine enters a new state. Xilinx tells me to >define all the outputs in every state. Is this true? Yes, it is. Well, at least last time I used ABEL -- which happened to be with Vantis CPLDs -- this was true. I believe more sophisticated ABEL users may have some tricks that can get ABEL to hold its registered outputs without your having to specify the output in every state, however. It probably involves specifying the flip flop type, however, which is something I prefer to let the synthesis tool decide. >According to one of >their tutorials, designs coded in VHDL will hold the outputs. True again. VHDL does extensive latch and register inference. Indeed, one of the things you need to watch out for in VHDL is not accidentally inferring latches that you didn't mean to. Some of the better synthesis tools such as Synplify provide warnings if an inferred latch looks suspicious. (The most common cause, at least for me, for undesired latch inference in VHDL is not specifying what an otherwise registered output is supposed to be during an asynchronous reset.) >Its hard to >believe that VHDL will hold the values and ABEL won't. You could probably argue it both ways. I certainly prefer VHDL's "hold your outputs -- even when you might not want me to" over ABEL's "don't hold your outputs -- unless I specifically tell you to." You also have to consider how old ABEL is. For its age, it's still remarkably usable for smaller designs. ---Joel KolstadArticle: 14920
Under Xilinx Foundation, I have a bunch of VHDL modules that have reset inputs. I use FPGA Express to synthesize them, and then use Xilinx's schematic editor to turn them into macros that are placed into the schematic (which principally ties all the VHDL modules together -- and no, I don't get "multiple startup block" errors :-) ). The macro symbols still have "reset" pins on them. In order to get GSR to reset the 'flops in the design, what should I do with the reset pins? If I leave them disconnected, Design Manager gives me warnings but does PAR correctly. If I ground them, the warnings go away. In both causes, as far as I can tell, in the actual FPGA all the 'flops do get reset at power-up. Any insight into the correct way to deal with the reset pins would be appreciated. Thank you. ---Joel Kolstad JKolstad@Electroglas.ComArticle: 14921
> I am trying to learn to use the ABEL HDL language included with the Xilinx > Foundations Base package. Xilinx tech support tells me that the only > documentation on this language is in the help files included with the > software. I am new to HDL and am having trouble getting started with this. In the help-file "reference" section you find a useful description of ABEL HDL including samples for better understanding > Does anyone know where I can learn more about this language and is it worth > using, or should I pay to get the VHDL upgrade? I have good experience with ABEL concerning GALs and CPLDs. There is a reference book from Synario (1MB) and from Xilinx (1,5MB), each about >200 pages in PDF. I dont remember the source, but could mail it to you > I have been experementing with the state machine editor and looking at the > ABEL code it generates. I have not been able to get a registered output to > hold its value when the machine enters a new state. Xilinx tells me to > define all the outputs in every state. Is this true? Hope to have understood your question right: Outputs are valid during the state, where you defined them with the "=" Operator. But you can also register the output with the ":=" operator NB: I dont know about the grafic state editor capabilities, as i always use the text editor Bertram -- Bertram Geiger, bgeiger@EUnet.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 14922
Don, Here's one point from one of my posts from Nov '95 which is no longer on DejaNews. After complaining about the fact that in CUPL, all outputs must either be 'persistant' or 'not persistant' I had this to say about ABEL back when I was up on this stuff: 5. Outputs can be persistent or transient on an output by output basis, although the syntax is obnoxious, like CUPL's. If you declare an output to be 'reg d' then its output will go true on the clock leaving the state that sets it, but it will return low on the state following that unless you keep setting it high. For this you use the out A := 1 syntax. If you want your output to be persistent and stay high until told to go low many states later, then you declare the output to be type reg_jk. Ah but you can't say A := 1. If you do, it will go high and never go low because this sets up an equation for the J input to the JK and none for the K. To make it work you have to say A.j = 1 to set the out put high, and A.k = 1 to set it low. Why can't someone do this right??????? Hope this helps Dave DeckerArticle: 14923
Re: First NASA/DoD Workshop on Evolvable Hardware, July 19 - 21, 1999, Jet Propulsion Laboratory To accommodate the requests for extensions of the submission deadline, the deadline is extended to March 10. Details of the workshop can be found at http://cism.jpl.nasa.gov/events/nasa_eh Jason Lohn EH'99 Co-chairArticle: 14924
I'm not sure what's included in the Foundation package, so please forgive me if the advice isn't helpful... When I'm in doubt as to whether or not the startup function has been properly implemented, I run EPIC. You should be able to find the startup block there. If your reset signal is wired to it, then you're in business. Your description confuses me a bit, though. Do you have a reset signal in the design? If so, why not connect it to all of your various reset inputs? Regards, Jamie Joel Kolstad wrote in message <7b424t$cl7$1@ffx2nh2.uu.net>... >Under Xilinx Foundation, I have a bunch of VHDL modules that have reset >inputs. I use FPGA Express to synthesize them, and then use Xilinx's >schematic editor to turn them into macros that are placed into the schematic >(which principally ties all the VHDL modules together -- and no, I don't get >"multiple startup block" errors :-) ). The macro symbols still have "reset" >pins on them. In order to get GSR to reset the 'flops in the design, what >should I do with the reset pins? > >If I leave them disconnected, Design Manager gives me warnings but does PAR >correctly. If I ground them, the warnings go away. In both causes, as far >as I can tell, in the actual FPGA all the 'flops do get reset at power-up. > >Any insight into the correct way to deal with the reset pins would be >appreciated. Thank you. > >---Joel Kolstad >JKolstad@Electroglas.Com
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