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In article <Pine.GSO.4.31.0104261729040.1447-100000@ux12.cso.uiuc.edu>,
vikram m n rao <vmrao@students.uiuc.edu> writes
<snip>
>"Dpm: Warning: Port 'rdin' has no net attached to it- no pad cells
>inserted at this port. (FPGA-PADMAP-2)
>
>And when I try to implement the design, I get the following ERROR:
>"ERROR:NgdHelpers:18 - Could not find NET "rdin" in design "newcnt3". NET
>entry is "NET rdin LOC=P28;"
>
>However, the input is described in my verilog file (along with 2 other
>inputs) as follows:
>"module top (clkin, data_out, reset, rdin); //BEGIN (TOP)
>parameter n = 17;
>input clkin;
>input reset;
>input rdin;"
>
>and in my UCF file as follows:
>"NET reset LOC = P44;
>NET clkin LOC=P13;
>NET rdin LOC=P28;"
>
>so I'm not exactly sure what the problem is, since the reset and clkin
>inputs worked just fine with no errors, but when I added rdin, I started
>getting this error, Any help would be greatly appreciated.
>
The trick is to look at the edif netlist and see if you can find rdin
there. If it *is* there, then I don't know what's happening. If it is
*not* there then
a) it's been renamed by the software
b) it's been optimised away by your synthesis tool, probably because you
are not using it,
kind regards
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
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Article: 30751This relates to my last problem (the error I'm getting in XILINX Foundation during synthesis which says "Warning: Port 'rdin' has no net attached to it - no pad cells inserted at this port (FPGA-PADMAP-2)"). And then when I try to implement the design, I get the following error: "ERROR:NgdHelpers:18 - Could not find NET "RDIN" in design "newcnt3". NET entry is "NET rdin LOC=P57;" I guess another basic question I have has to do with how I go about adding input ports that connect to I/O pins on the FPGA. For example, to use the clock on the XESS XS40 FPGA board I have, I consulted the schematics which indicated that pin 13 was connected to the on-board clock, so I just went into the user constraints file (UCF) and entered "NET clkin LOC=P13;" and then I included clkin in the port list of my top level verilog code, and indicated it was an input. This worked fine. Now I need to use an I/O pin on the FPGA- I need to use it as an input to read values off the pin. So, after consulting the schematics, I went into the UCF and entered "NET rdin LOC=P57;" I then went into my verilog code and defined rdin in the top level port list, and indicated it was an input. However, I get the error indicated above during synthesis. Some of you have suggested maybe the input was optimized out of the system by the synthesis tool, however I cannot determine this by looking at the synthesis report. Also, I DO NEED this input, so how can I make sure it synthesizes properly? VikArticle: 30752
Vik, Your synthesis program is optimizing rdin out of the design. The sysnthesis program can see that rdin has no effect on your ouput data_out and as an optimization it is removing it from the design. When it comes to implementing the design foundation tries to enforce the constraint "NET rdin LOC=P28" but cannot find rdin (since it has been removed). Viv "vikram m n rao" <vmrao@students.uiuc.edu> wrote in message news:Pine.GSO.4.31.0104261729040.1447-100000@ux12.cso.uiuc.edu... > > I am having a problem with my XESS XS40 board and making a UCF file in > XILINX Foundation. I've gotten my design to synthesize properly using 2 > input pins I described in my user constraints file (UCF), but when > I try to add another input pin, I get the following WARNING > during the synthesis phase: > "Dpm: Warning: Port 'rdin' has no net attached to it- no pad cells > inserted at this port. (FPGA-PADMAP-2) > > And when I try to implement the design, I get the following ERROR: > "ERROR:NgdHelpers:18 - Could not find NET "rdin" in design "newcnt3". NET > entry is "NET rdin LOC=P28;" > > However, the input is described in my verilog file (along with 2 other > inputs) as follows: > "module top (clkin, data_out, reset, rdin); file://BEGIN (TOP) > parameter n = 17; > input clkin; > input reset; > input rdin;" > > and in my UCF file as follows: > "NET reset LOC = P44; > NET clkin LOC=P13; > NET rdin LOC=P28;" > > so I'm not exactly sure what the problem is, since the reset and clkin > inputs worked just fine with no errors, but when I added rdin, I started > getting this error, Any help would be greatly appreciated. > > Vik >Article: 30753
FPGA place and route tools can output a netlist in VHDL or EDIF or Verilog and a SDF file which contains timing information such as propogation delays, setup and hold times for the items in the netlist. If you load these into you simulator you get a simulation with real delays. You are annotating delays back into your design. The spec for SDF allows for 2(minimum and maximum) or 3(minimum, typical and maximum) values for each time. Some FPGA tools output different values for min and max (Actel), some tools output 3 identical values (Xilinx). Why the Xilinx tool can't manage 2 or 3 values at one time I don't know, all the info is in the data base. Maybe those who wrote the software couldn't be bothered. Hope this helps Kate > -----Original Message----- > From: Tomasz Brychcy [SMTP:T.Brychcy@ime.pz.zgora.pl] > Posted At: 27 April 2001 07:38 > Posted To: fpga > Conversation: back annotation > Subject: back annotation > > Hello, > > What exactly does mean: back annotation?Could you explain me on any > example? > > Best regards > > Tomek > > T.Brychcy@ime.pz.zgora.pl > >Article: 30754
In article <Pine.GSO.4.31.0104270316000.12671-100000@ux12.cso.uiuc.edu>,
vikram m n rao <vmrao@students.uiuc.edu> writes
>
>This relates to my last problem (the error I'm getting in XILINX
>Foundation during synthesis which says "Warning: Port 'rdin' has no net
>attached to it - no pad cells inserted at this port (FPGA-PADMAP-2)").
>And then when I try to implement the design, I get the following error:
>"ERROR:NgdHelpers:18 - Could not find NET "RDIN" in design "newcnt3". NET
>entry is "NET rdin LOC=P57;"
>
>I guess another basic question I have has to do with how I go about
>adding input ports that connect to I/O pins on the FPGA.
>
>For example, to use the clock on the XESS XS40 FPGA board I have, I
>consulted the schematics which indicated that pin 13 was connected to the
>on-board clock, so I just went into the user constraints file (UCF) and
>entered "NET clkin LOC=P13;" and then I included clkin in the port list of
>my top level verilog code, and indicated it was an input. This worked
>fine.
>
>Now I need to use an I/O pin on the FPGA- I need to use it as an input to
>read values off the pin. So, after consulting the schematics, I went into
>the UCF and entered "NET rdin LOC=P57;" I then went into my verilog code
>and defined rdin in the top level port list, and indicated it was an
>input. However, I get the error indicated above during synthesis. Some of you
>have suggested maybe the input was optimized out of the system by the
>synthesis tool, however I cannot determine this by looking at the
>synthesis report. Also, I DO NEED this input, so how can I make sure it
>synthesizes properly?
>
>Vik
>
You need to make sure that rdin is really being used. Can you post your
code that you are synthesising? (i.e. VERILOG).
Regarding I/O buffers: most synthesis tools default to adding IO buffers
automatically. The problems people experience are normally the other way
round, i.e. if you synthesise two submodules of a design separately, you
need to make sure that the synthesis tool *does not* put pads in.
I still think rdin is not being used in your code. For instance, perhaps
you haven't written the code yet (i.e. you are doing top down design)?
Some synthesis tools have "preserve" attributes that you can apply to
stop signals being optimised away - you might be able to use this to
keep a signal.
regards
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 30755Hi all, I am using the XILINX Design Manager (v 3.3i) after synthesis with Leonardo and Synplify. The design entry is purely VHDL code and it does not contain neither latches nor warning messages during synthesis but when I run ngd2vhdl (in Design Manager) to generate a VHDL output file for post-synthesis simulation, I get warning messages as: WARNING:NetListWriters:117 - Signal Signal_Name(i) not found for signal bus Bus_Name(n downto 0). WARNING:NetListWriters:107 - Signal bus Bus_Name(n downto 0) is not reconstructed. Afterwards, I use Leapfrog for the simulation (with the SIMPRIM libraries) and the results are wrong (buses changing values each 0.1 NS, indetermined signals, etc...). I have been rewriting my VHDL code in order to have clear structures and optimized state machines. The signals not found in the ngd2vhdl are differents each time but the simulation results are always the same. Is this because of a mistake in my VHDL code, in the SIMPRIM libraries or the ngd2vhdl itself? Thank you in advance, Ivan. ____________________________________________________________ Ivan Garcia Alfonso Tel: +41 22 7679452 CERN, PS Division Fax: +41 22 7678510 CH-1211 Geneva 23 Switzerland ____________________________________________________________Article: 30756
Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: : I'm routing a Virtex-E part, and I find that I get different routing : results for a particular cost table depending on whether I use single : pass or multi pass (the -n MPPR option) on par. : Question: what does par do differently, so that it gets different : results even though the cost table is the same? This is indeed a bug that was found in PAR. There is a fix in SP8 for this. Given the same mapped ncd, the same constraints and the same placer cost table, PAR will produce the same result whether it was a single pass or an MPPR run. This should also be true across different platforms. : Which result should I believe? Neither should be incorrect. They are just different results. Carl SternArticle: 30757
Matt Billenstein wrote: > All, I have one register in my design that is clocked by a signal not on a > GCLK pin... Right now I run it through and IBUF, then a BUFG and then to > the register, but it gets routed all over the place in doing this. Is it > possible to just run the signal from the IBUF to this one register? The > tools don't seem to like it, I get errors during translate saying the signal > has an illegal connection... > > I'm using foundation 3.1i sp7 and VHDL design entry. This should work. A problem that I have had is the synthesis tool sees that the signal is a clock and assigns it to an IBUFG, but since the signal is not actually on an IBUFG you get errors. Using verilog and Synplify, you need to use the synthesis directive /* synthesis syn_noclockbuf=1*/ There must be something similar in VHDL. Unfortunately, I don't know what it is. Alan Nishioka alan@nishioka.comArticle: 30758
I guess my previous article were discarded by a new newsreader, sorry if you see this a third time... Facts and fantasies: DSP on modern Pentium 4 at 1.7GHz has about 13.8 GOPS computing power using MMX instructions - it's assumed only one *arithmetic* (vectored 8x8bit) instruction can be executed in a clock cycle. Similarly a modern FPGA, Altera's Mercury has 14400 Logic Elements, of which about 900 8-bit "instructions" can be composed assuming 50% utilizations. (Routing becomes perhaps too difficult). With 300MHz clock, the equivalent number of Meaningless OPS is about 270000, or 270GOPS. The ratio in benefit of FPGA is about 20:1. This is far from the 1000:1 claim in www.andraka.com/dsp.htm I'd still like to believe, this kind of acceleration can be achieved. And if not literatively, perhaps having other metrics - GOPS/buck, GOPS/power consumption etc. Or, can you imagine some specific problem, that could be benefit from FPGA acceleration even more - these are just my quick estimates without any complexity analysis: - DES (S-boxes) - motion block search using few levels of tones - modular exponentiation - Reed Solomon coding What else? Has anyone recently bought a high-end FPGA? Prices? What's a typical power consumption per calculational element per MHz? - you can buy a single P4@1.7 for $550. -- Problems 1) do NOT write a virus or a worm program "A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"Article: 30759
I have an XESS XS40 board, and I need to disable the microcontroller and RAM for my design. According to the XESS FAQ, "All you need to do is program the FPGA such that the RST pin of the microcontroller and the /CS pin of the RAM are pulled high. Since pins 36 and 65 on the FPGA are connected to the RST and /CS pins of the RAM/microcontroller, you just need to program the FPGA to set them hi. This will keep all their pins in the high impedance state." Someone at XESS explained to me how to go about this in VHDL: "In VHDL, you just output a logic 1 on these pins: uc_reset <= '1'; ce_n <= '1'; Then place the following pin assignments in your UCF file (I assume you are using an XS40 Board): NET uc_reset LOC=P36; NET ce_n LOC=P65; " So how do I go about doing this in Verilog? I need to have these 2 pins always high to disable the microcontroller and RAM. I tried defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and defined them as registers. I then inserted the following code to set them high: always @(posedge clkin) begin uc_reset <= 1; ce_n <= 1; end and I then set the registers to correspond to the appropriate pins in my UCF. But this doesn't seem to work, because I get the following error during the implementation phase: "ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol "ucdisable.PAD" (pad signal=ucdisable). No such site for this device. This may also indicate that a non-constrainable site (such as a VCC, GND, mode, configuration, or other special-purpose pin) has been used as a site name. ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol "ramdisable.PAD" (pad signal=ramdisable). No such site for this device. This may also indicate that a non-constrainable site (such as a VCC, GND, mode, configuration, or other special-purpose pin) has been used as a site name." Am I correct in my approach (defining these as hi @posedge of my main clock)? And it looks as if it will not let me set constraints on these pins, but I have verified (through pinouts and tech people at XESS) that those are the pins to set hi. Any ideas on how to go about this? VikArticle: 30760
Note that in my last post, the errors I was getting named the registers as 'ucdisable' and 'ramdisable' instead of 'uc_reset' and 'ce_n' This discrepancy was actually corrected in the code so it is not the source of the errors. VikArticle: 30761
vikram m n rao wrote: > I have an XESS XS40 board, and I need to disable the microcontroller and > RAM for my design. According to the XESS FAQ, "All you need to do is > program the FPGA such that the RST pin of the microcontroller and the /CS > pin of the RAM are pulled high. Since pins 36 and 65 on the FPGA are > connected to the RST and /CS pins of the RAM/microcontroller, you just > need to program the FPGA to set them hi. This will keep all their pins in > the high impedance state." > > Someone at XESS explained to me how to go about this in VHDL: > "In VHDL, you just output a logic 1 on these pins: > uc_reset <= '1'; > ce_n <= '1'; > Then place the following pin assignments in your UCF file (I assume you > are using an XS40 Board): > NET uc_reset LOC=P36; > NET ce_n LOC=P65; " > > So how do I go about doing this in Verilog? I need to have these 2 pins > always high to disable the microcontroller and RAM. I tried > defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and > defined them as registers. I then inserted the following code to set them > high: > > always @(posedge clkin) begin > uc_reset <= 1; > ce_n <= 1; > end > > and I then set the registers to correspond to the appropriate pins in my > UCF. But this doesn't seem to work, because I get the following error > during the implementation phase: > "ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol > "ucdisable.PAD" > (pad signal=ucdisable). No such site for this device. This may also > indicate that a non-constrainable site (such as a VCC, GND, mode, > configuration, or other special-purpose pin) has been used as a site > name. > ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol > "ramdisable.PAD" > (pad signal=ramdisable). No such site for this device. This may also > indicate that a non-constrainable site (such as a VCC, GND, mode, > configuration, or other special-purpose pin) has been used as a site > name." > > Am I correct in my approach (defining these as hi @posedge of my main > clock)? And it looks as if it will not let me set constraints on these > pins, but I have verified (through pinouts and tech people at XESS) that > those are the pins to set hi. Any ideas on how to go about this? > > Vik In verilog try: assign uc_reset = 1; assign ce_n = 1; Don't define them as registers, just as outputs. Since they are constant, they don't need to be registered on a clock. The error seems to be some sort of name conflict problem. Or it may be that the synthesizer is optimizing the register out and then having problems with the result. Alan Nishioka alan@nishioka.comArticle: 30762
Aki M Suihkonen wrote: > > I guess my previous article were discarded by a new > newsreader, sorry if you see this a third time... > > Facts and fantasies: > > DSP on modern Pentium 4 at 1.7GHz has about 13.8 GOPS > computing power using MMX instructions - it's assumed > only one *arithmetic* (vectored 8x8bit) instruction can be executed > in a clock cycle. This is a extremely optimistic assumption. In practice, even with hand written assembly code you would probably not get more than 1/5 of this processing power, this for numerous reasons : - insiffcient processor memory bandwidth - caches misses - control flow misprediction (x86 use speculative branch) - array pointer increments - Load/store instructions and pack/unpak to organize the data so that they can be correctly processed by the MMX FU. - etc ... Some time ago I read a article saying that even for regular and simple computations found in image or signal procssing the MMX benefits were somehow deceiving (speed-up only between 1.2 and 2 for most apps) > > Similarly a modern FPGA, Altera's Mercury has 14400 Logic Elements, Xilinx XCV3200 has 70.000 logic cells, and can reasonably runs at 150Mhz. If you iplement a regular archtecture you might reach 80-90% utilization > of which about 900 8-bit "instructions" can be composed assuming > 50% utilizations. (Routing becomes perhaps too difficult). > With 300MHz clock, the equivalent number of Meaningless OPS is > about 270000, or 270GOPS. The ratio in benefit of FPGA is about 20:1. Still not bad don't you think :)) ? > > This is far from the 1000:1 claim in www.andraka.com/dsp.htm Right, but you don't use a PIII 1.Ghz in an embedded system (which is the main market of high end FPGAs), generally one prefers a DSP or RISC micrcontroller with far less processog power (aroung 1-2 GOPS) Beside for some exotic processing or arithmetic, a CPU/DSP might require much more than a cycle to execute an 'operation', which might not be the case of an FPGA implementation (Galois fields arithmteics is probably a good example). > I'd still like to believe, this kind of acceleration can be achieved. So yes, such a speed-up might be possible to attain although it is probably an extreme case in favour of FGPAs > And if not literatively, perhaps having other metrics - > GOPS/buck, GOPS/power consumption etc. > > Or, can you imagine some specific problem, that could be benefit > from FPGA acceleration even more - > these are just my quick estimates without any complexity analysis: > > - DES (S-boxes) > - motion block search using few levels of tones > - modular exponentiation > - Reed Solomon coding > > What else? DNA sequence matching. > > Has anyone recently bought a high-end FPGA? Prices? Xilinx XCV2000 is around 2000$, not cheap :(( > What's a typical power consumption per calculational element per MHz? go and see http://www.xilinx.com/cgi-bin/powerweb.pl An admitted of thumb rule is that Asic are 10x more power efficient than FPGAs themselves 10x more poser efficient than DSPs/CPU, of course this greatly depends on the application > - you can buy a single P4@1.7 for $550. However again, you wouldn't use such a CPU in the context on an embedded system. > > -- > Problems 1) do NOT write a virus or a worm program > "A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"Article: 30763
> So how do I go about doing this in Verilog? I need to have these 2 pins
> always high to disable the microcontroller and RAM. I tried
> defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and
> defined them as registers. I then inserted the following code to set them
> high:
I'm not sure what problem you're having with your registers, but don't
bother with registers. Just drive the pins high or low. Here are excerpts
from the XSOC/xr16 Project Kit (www.fpgacpu.org/xsoc/), Verilog version,
which *disables* the XS40 MCU and *enables* the RAM:
/xsoc/xsocv/xsoc.v:
module xsoc(..., ram_ce_n, ..., res8031, ...);
...
output ram_ce_n; // active low external RAM chip enable
...
output res8031; // reset external 8031 MCU
...
assign ram_ce_n = 0;
assign res8031 = 1;
...
endmodule
/xsoc/xsocv/xsoc-05xl-13.ucf:
...
NET res8031 LOC = P36;
NET ram_ce_n LOC = P65;
...
Jan Gray, Gray Research LLC
Article: 30764First off - I'm not an expert on PCI so dont know how easy this could be, but... I was suggesting that writting to one on the registers (or a new one) or DMAing to your device local bus memory could be divirterted internaly to atualy write to your eeprom say. next re bout would just load this code. If you can talk to your device and send it information... then you can find away to dirvert the infomation to your configuration device!? If you add funtions to your device that are not standard - is that braking the rules? cyber_spook (PS I'm going to have a read of this PCI book I have in my bag, befor I post again.) Erik Widding wrote: > > "cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message > > news:3AE8879E.17752893@cyberspook.freeserve.co.uk... > > > maybe your FPGA could recive its code via a configuration device (EPC2 > > > or a PLD with a eeprom hanginging off it) and you could build in a > > > funtion of your pci fpga - maybe some set target memory that you could > > > load with new code that would realy get put in your configuration device > > > ready for your next reboot? > > > > > "Austin Franklin" <austin@dark87room.com> wrote in message > news:9caid1$8m6$1@nntp9.atl.mindspring.net... > > You are only 'allowed' one signal source/destination connected to (most) > > each PCI signal. You would have to use a bridge... Unless it's in an > > embedded system, you really don't want to break the rules. > > No need to use a bridge. One merely needs to have two sets of > configuration data on the card, and a mode to change from the first to the > second. > > Configuration number one will be non-volatile, and used to boot the card. > It > will contain a PCI core, and only three functions: > Say "hello" to BIOS for allocation of resources at boot. > Read/Write conguration memory two from PCI bus. > Kickstart configuration from memory number two. > > Configuration number two contains whatever you want it to, and could be > stored in a more volatile fashion, i.e. Parallel SRAM. I would boot from a > XC17xx prom, and use a small CPLD and an SRAM for the second config. > The only extra overhead that your additional configs will have to carry, is > the ability to kickstart configuration from the serial prom. > > Painless reconfigurable computing. If one will be constantly switching > between configurations, just make the SRAM larger, and give every config > the ability to tell the config controller which configuration to use for the > next kickstart. > > Config controller will fit a <$2 XC9536. No need for the JTAG port. No > bridge chip required. The SRAM/CPLD/XC17xx xolution is much cheaper > than those flash based config devices. And, best of all, no rules were > broken. > > Regards, > Erik Widding. > > -- > Birger Engineering, Inc. -------------------------------- 781.481.9233 > 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com > > > > > > cyber_spook > > > > > > mike wrote: > > > > > > > hi all, > > > > i want to configure my fpga on a pci card via the jtag pins > > > > on the pci connector, but i dont know how to access these pins. > > > > can you help me? > > > > mike > > > > > > >Article: 30765
Aki M Suihkonen wrote: > > I guess my previous article were discarded by a new > newsreader, sorry if you see this a third time... > > Facts and fantasies: > > DSP on modern Pentium 4 at 1.7GHz has about 13.8 GOPS > computing power using MMX instructions - it's assumed > only one *arithmetic* (vectored 8x8bit) instruction can be executed > in a clock cycle. > > Similarly a modern FPGA, Altera's Mercury has 14400 Logic Elements, > of which about 900 8-bit "instructions" can be composed assuming > 50% utilizations. (Routing becomes perhaps too difficult). > With 300MHz clock, the equivalent number of Meaningless OPS is > about 270000, or 270GOPS. The ratio in benefit of FPGA is about 20:1. > > This is far from the 1000:1 claim in www.andraka.com/dsp.htm This is the upper limit, which is only approached under very specific circumstances. I typically see values around 100:1 in the projects I work on. There are many hardware optimizations other than sheer parallelism that come together to get these processing gains. For some discussion of that, see my radar processor on a chip paper from the asilomar conference. In that case, each of the multipliers in the big filters (when divided out) works out to about 3CLBs. Of course, the real hardware doesn't have discrete multipliers, rather it uses serial ditributed arithmetic to take advantage of the FPGA structure. It really comes down to what your specific application is, as well as your skill as a hardware systems architect. Remember that many of the OPs in a microprocessor are needed to get the general purpose logic to do a specific task. Much of this overhead is eliminated in a custom hardware design. > > I'd still like to believe, this kind of acceleration can be achieved. > And if not literatively, perhaps having other metrics - > GOPS/buck, GOPS/power consumption etc. > > Or, can you imagine some specific problem, that could be benefit > from FPGA acceleration even more - > these are just my quick estimates without any complexity analysis: > > - DES (S-boxes) > - motion block search using few levels of tones > - modular exponentiation > - Reed Solomon coding > > What else? Digital radio, radar processing, image processing (feature extraction etc). How about a video processor example I recently did for a customer? A $15 (small quantities) spartanII-50 -5 running at a leisurely 66 mHz easily processes three fairly complex parallel video threads at the frame rate, where the prototype running on a 300MHz PPC (>$100) performed the same algorithm at 1/12th the frame rate. As a bonus, user interfaces and whatnot that would have needed some programmable logic anyway are rolled in. THe video processor portion of the design occupies less than 40% of the FPGA. By using more parallelism, one could easily increase the performance many times over (of course in this case it isn't necessary). > > Has anyone recently bought a high-end FPGA? Prices? What's > a typical power consumption per calculational element per MHz? > - you can buy a single P4@1.7 for $550. > The power for equivalent data rates in an FPGA seems to fall out at about 20% of the processor's power fairly consistently, using worst case power consumption numbers. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30766
Jan Gray wrote: > > So how do I go about doing this in Verilog? I need to have these 2 pins > > always high to disable the microcontroller and RAM. I tried > > defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and > > defined them as registers. I then inserted the following code to set them > > high: > > I'm not sure what problem you're having with your registers, but don't > bother with registers. Just drive the pins high or low. Here are excerpts > from the XSOC/xr16 Project Kit (www.fpgacpu.org/xsoc/), Verilog version, > which *disables* the XS40 MCU and *enables* the RAM: With the Xilinx Software you can not do this if these are the only Pins in the design. (Designs with 0 inputs do not fit into a CPLD) So make sure to have some logic somewhere. I ran into the same problem when I soldered a CPLD to my board the should fullfill some useful functions later that year, but at the time beeing just had to output a high value on two pins to disable another chip on the board. Kolja SulimmaArticle: 30767
Do they really use FPGAs for DNA sequencing? Back when Celera was working on the genome they were using these huge banks of computers to match shotgun sequencing fragment overlaps which, like correlation, is a job poorly suited to oldschool one-line-at-a-time processors. I had the great idea of using a long radix-4 correlator to do this and told my boss to patent my idea, but I'm sure it was thought of long ago, like the rest of my ideas. Just the other day I came up with a novel technique for powering automobiles through internal combustion, and then I find out it's been in use for a century! Ha. > > > > What else? > > DNA sequence matching. >Article: 30768
OK, what's the latest on the C++ -> gates story? I'm always hearing about how I should be using Celoxica or some such other tool, because it can synthesize C++. The implication is also made that such tools can take code written by software guys for regular processors and somehow efficiently cram it into an FPGA. The implication is also made that I will be obsolete soon because I will be replaced by guys who are writing PC software. I am almost certain that these tools don't work that way and are a waste of time, and that my job is not in immediate danger, but has anybody else found that they can write sequential C code and have it turned into wonderful parallel synthesizable code by these tools? I don't even understand how these things are supposed to work. Say I write some for-next loop in C describing a FIR filter. Does this C->gates tool instantiate a MAC and a loop counter, or does it know that I really didn't want a temporal loop but wanted a separate multiplier for each tap and I wanted an adder tree? Furthermore, does it know that since I'm only multiplying by one of a few values, that I really want the multipliers replaced by lookup tables? And does it automatically pipeline the adder tree for me? I don't get it.Article: 30769
I had a problem with the BRAM on my last project. The Xilinx BRAM clock->out time is about 3ns. This is fine. The problem I had was that the nets connecting the BRAM data outputs to other logic seemed to have excessively long delays, many over 3ns. Even when I handplaced flops right next to the BRAMs the net delays still seemed excessive. This was in a part that was only 30% utilized, so there were no real routing issues. Have others had this problem? I registered the BRAM outputs, but in many cases it was still over 7ns to get the data out, across the net, and meet the flop setup time. This raises an additional question about the placer. The placer seems to make some really poor decisions. All of my critical nets had huge delays because parts that should have been placed together were inexplicably placed on opposite sides of the part. Place and route seem to be completely independent processes. Isn't there a way to place, route, and then place again based on the route information, and then route again? This seems like a good idea, because on the second placement round, the placer could look at the critical nets from the previous route and say, "Whoa, it take 4ns to get from flop A to flop B; maybe I should place those closer together and try routing again." But from what I can tell, placement is done first, and then locked down, with no regard to the post-route net delays.Article: 30770
> Now I need to use an I/O pin on the FPGA- I need to use it as an input to > read values off the pin. So, after consulting the schematics, I went into > the UCF and entered "NET rdin LOC=P57;" I then went into my verilog code > and defined rdin in the top level port list, and indicated it was an > input. However, I get the error indicated above during synthesis. Some of you > have suggested maybe the input was optimized out of the system by the > synthesis tool, however I cannot determine this by looking at the > synthesis report. Also, I DO NEED this input, so how can I make sure it > synthesizes properly? In Xilinx Student Edition 2.1i, from the project-manager window, follow this menu hierarchy "Implementation -> (drop down menu) Options -> (pop up dialog box) Program Options ... Implementation -> <<< Edit Options >>> (button) Trim Unconnected Logic (checkbox)"Article: 30771
> OK, what's the latest on the C++ -> gates story? I'm always hearing about > how I should be using Celoxica or some such other tool, because it can > synthesize C++. The implication is also made that such tools can take code > written by software guys for regular processors and somehow efficiently cram > it into an FPGA. The implication is also made that I will be obsolete soon > because I will be replaced by guys who are writing PC software. I am almost > certain that these tools don't work that way and are a waste of time, and > that my job is not in immediate danger, but has anybody else found that they > can write sequential C code and have it turned into wonderful parallel > synthesizable code by these tools? I have worked "in industry" for about 15 months now, doing ASIC design. I concentrated on the front-end portion (writing RTL Verilog code, no back-end or physical stuff for me to worry about, just RTL and functional simulation.) I'm sure the first generation C++ -> gates software won't interest any serious designer on anything but an academic level. But as the technology improves (and as fabrication geometries shrink), the apparent 'penalty'/cost of using such a technology will lessen to a point where it becomes practical. Think about the olden days; an HDL line like "z=a+b" would require a structural (gate-level) description to avoid horribly inefficient implementation. But nowadays, Synopsys Design Compiler with Designware will pull up a reasonably efficient adder macro. (I'm sure an expert VLSI guy could perform an even better custom layout adder.) Likewise, a binary (X * Y) multiplier or a barrel shifter are classical classroom VLSI design exercises. VLSI layout will beat any equivalent HDL compiler equivalent. But nowadays, even in companies which can handle custom VLSI designs, the custom-stuff is reserved for analog, memory, or other special mixed-signal blocks which can't be done in HDL. As FPGAs are increasing in capacity and speed, I think the hadware design arena will open to people with less hardware-design skills. You could look at the popularity of Visual Basic and other rapid application development tools. I'm sure they create horribly bloated executable code (compared to a C-compiler or even a C++ compiler), but PCs are so loaded with MHz and RAM, who cares. 'Ordinary' (i.e. not computer science professionals) folks can setup databases, webpages, and write useful programs with today's GUI tools. I'm sure one day, the same ordinary folks could do the same with FPGAs. Just like HDL coders and schematic-capture people can code up thousand-gate designs in a matter of minutes, without worrying about individual transistor sizes. > I don't even understand how these things are supposed to work. Say I write > some for-next loop in C describing a FIR filter. Does this C->gates tool > instantiate a MAC and a loop counter, or does it know that I really didn't > want a temporal loop but wanted a separate multiplier for each tap and I > wanted an adder tree? Furthermore, does it know that since I'm only > multiplying by one of a few values, that I really want the multipliers > replaced by lookup tables? And does it automatically pipeline the adder > tree for me? I don't get it. I bet these tools require you to write code in a special way. And to add compiler-specific/intrinsic tags to assist the conversion process. I've never used one, though. so i'm just speculating out my foot.Article: 30772
> This raises an additional question about the placer. The placer seems to > make some really poor decisions. All of my critical nets had huge delays > because parts that should have been placed together were inexplicably placed > on opposite sides of the part. Place and route seem to be completely > independent processes. Isn't there a way to place, route, and then place > again based on the route information, and then route again? This seems like > a good idea, because on the second placement round, the placer could look at > the critical nets from the previous route and say, "Whoa, it take 4ns to get > from flop A to flop B; maybe I should place those closer together and try > routing again." But from what I can tell, placement is done first, and then > locked down, with no regard to the post-route net delays. You've pretty much described "physically knowledgable synthesis"...a concept Synopsys, Cadence, and everyone else are pushing toward. Those software tools don't come cheap... It's just a matter of time before FPGA vendors incorporate the same ideas into their development tool suite.Article: 30773
Kevin, I am a software engineer, with VHDL and hardware skills. I will not say that i can write superior VHDL, but am doing quite a good job at it. As a software engineer i wrote a Java to Hardware compiler. It is the same as the C/C++ compiler, obly targeting Java. As these tools are in their child stages, they will not be replacing hardware engineers for designs that will stretch the limit of the FPGA. So designs that are very time critical will be difficult to create. But this is not really a problem for designs that don't need to run at the limit of the FPGA. We needed a design that run at 50 Mhz, i coded it in Java, and it run at 66MHz. So for this application it was sufficient, and a lot faster to implement. I am not saying that it is as efficient as when it is done inVHDL, but it is not worse than that. We indeed use special java classes to create different adders, parallel performing tasks etc. We fully implemented these objects that they can also run on a PC, so it is not just a keyword class. For the things you mention about instantiating different kind of pipelines, instead of combinatorial designs etc. For this special classes need to be build, but that is not different that in VHDL, in VHDL you also instantiate different kind of objects. A second important aspect is that since FPGA's are growing rapidly in size and speed, there is a problem with the software keeping up. These tools can close the gap a little. Take a look at our website, we have a flyer called JavaToHardware, where you can see some sample code, and the simulation of how it runs. Regards Richard. Kevin Neilson wrote: > OK, what's the latest on the C++ -> gates story? I'm always hearing about > how I should be using Celoxica or some such other tool, because it can > synthesize C++. The implication is also made that such tools can take code > written by software guys for regular processors and somehow efficiently cram > it into an FPGA. The implication is also made that I will be obsolete soon > because I will be replaced by guys who are writing PC software. I am almost > certain that these tools don't work that way and are a waste of time, and > that my job is not in immediate danger, but has anybody else found that they > can write sequential C code and have it turned into wonderful parallel > synthesizable code by these tools? > > I don't even understand how these things are supposed to work. Say I write > some for-next loop in C describing a FIR filter. Does this C->gates tool > instantiate a MAC and a loop counter, or does it know that I really didn't > want a temporal loop but wanted a separate multiplier for each tap and I > wanted an adder tree? Furthermore, does it know that since I'm only > multiplying by one of a few values, that I really want the multipliers > replaced by lookup tables? And does it automatically pipeline the adder > tree for me? I don't get it. -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 30774
Hi, When I started routing my design, PAR terminated abnormally, with the following error information. Routing active signals. INTERNAL_ERROR:SpeedCalc:basndtiming.c:887:1.6 - Getnodeparms for node not on signal EXEWRAP detected a return code of '-1073741819' from program 'par' Done: failed with exit code: 0005. Can someone help me? Thanks in advance!
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