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Hi, I am doing a Master's thesis in which I am interfacing to the SBus. I have what I think is a simple question, but I can't seem to get straight. I am using a Xilinx part all I need to do is read and write from the SBus to some registers in the chip. What I can't seem to figure out is how to set this up in VHDL. I know the Sbus must be bi-directional and the registers will need to be tri-states, but I keep chasing my tail as I try to code this. In addition I am using the 5.2/6.0 Foundation tools as my part (X4008) is no longer supported under the latest foundation tools. If anyone can point me in the right direction in terms of examples or reference material I would appreciate it. Thanks, Tyrone -- -------------- thompson@eecis.udel.edu University of Delaware Tyrone Thompson EE Graduate StudentArticle: 14851
Andy Peters <apeters@noao.edu.NOSPAM> wrote: > And the new M1.x tools don't support the (obsolete) XC73xx chips (we have Nor XC4000, which is annoying too. Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/Article: 14852
On Fri, 19 Feb 1999 09:36:58 +0200, Utku Ozcan <ozcan@netas.com.tr> wrote: <snipped> you don't really give enough information, but if your post-layout simulation differs from your other two simulations, and the static analyser hasn't reported any timing errors, then this should mean that your timing constraints are incorrect. the post-layout simulation is, in most cases, simply a test of your constraints. if your ncf file has no domain information then this is likely to be your problem. if you want a fix, you should post a description of how the clocks are related, the constraints you give to synplify, and the resulting ncf. evanArticle: 14853
On Fri, 19 Feb 1999 18:46:18 GMT, frannhagen@my-dejanews.com wrote: >I find it tricky sometimes to deal with the unpredictable process execution >in VHDL. Adding a small phase differance (i.e. 1ns) could help. If your >flow of data is in one direction (i.e. 12.5 -> 25) only this works. process execution in VHDL is unpredictable only in the sense that process execution order, within a single delta cycle, is random. however, the whole point of the delta cycle model is that this doesn't matter (it does matter in verilog, but that's a different story). if you've written a model where execution order does matter, then the model is incorrect (excluding trivial cases such as generating reports in different orders) and you should fix it, rather than adding arbitrary phase delays. do you have any examples? evanArticle: 14854
> you don't really give enough information, but if your post-layout
> simulation differs from your other two simulations, and the static
> analyser hasn't reported any timing errors, then this should mean that
> your timing constraints are incorrect. the post-layout simulation is,
> in most cases, simply a test of your constraints.
>
> if your ncf file has no domain information then this is likely to be
> your problem. if you want a fix, you should post a description of how
> the clocks are related, the constraints you give to synplify, and the
> resulting ncf.
>
> evan
Design entry: Verilog
Synthesizer: Synplify 5.0.8
P&R: Design Manager M1.5 Alliance
Technology: Xilinx XC40150XV/-0.9/BG352
Ok. Let me explain my problem in a more detail.
_________ _________
Address | | Address | |----> A[x:0]
---------->| Logic A |----------->| Logic B | (Dual Port RAM)
| 12.5 MHz| | 25 MHz |----> WR_EN
Data | (FSM) | Data | (FSM) |
---------->|_________|----------->|_________|----> D
Address and Data at the output of Logic A are valid for just one clock
period (in this case, at 12.5 MHz). Logic A is running at positive edge.
Logic B accepts this signals at the falling edge of the 25 MHz clock
and generates appropriate address, data and write enable signals to
the Dual Port RAM.
Logic A and Logic B FSM's are designed and verified in functional level.
Synplify is given actual frequency values in SDC file and Global Frequency
Value has been set to 0 (zero MHz). We got the best result under this
condition. XNF netlist of Synplify is given ngduild and ngd2ver to get
the post synthesis Verilog netlist (this is recommended by Synplicity).
SDC file includes actual frequency values to the external clocks and
divided clocks (12.5 MHz internally derived from 25 MHz external clock).
Functional simulation and post synthesis simulation are exactly the same.
Static Timing Analyzer TRCE doesn't produce any timing error. But Design
Manager warns me that 12.5 MHz clock is using non-dedicated clock resources.
(Is there any way to dedicate divided clock to a clock network?) Design
Manager accepts UCF file (NCF file is not given) which includes clock
constraints and TIMESPEC FROM:TO constraints to define multiple clock
domain interaction. Without TIMESPEC timing in the UCF file of M1.5,
the analyzer reported a slower frequency result but with TIMESPEC there
are new warnings but static timing analyzer gives a better frequency.
Post layout simulations show that ONLY ADDRESS VECTOR is weird. Address
Vector of Dual Port RAM has the correct value in a definite clock period
in two clock cycles later. (This results are with UCF without TIMESPEC):
Address Waveform
_____ ____ _
12.5 MHz Clock ___/ \_____/ \_____/
____________________________
Address Input of B ____________________________ (it doesn't change at all)
__ __ __ __ __
25 MHz Clock _/ \__/ \__/ \__/ \__/
____ _____ _________________
Func & Post synthesis ____X_____X_________________
________________ _____ _____
Post Layout ________________X_____X_____
This result is horrible and we are surprised. Has anyone met such a
condition before?
Utku
Article: 14855Forgotten to say: The problem was - NCF with clock constraints - UCF with pin constraints (but no TIMESPEC and no clock constraints) Following condition was not tested: - no NCF is given - UCF with pin constraints, clock contraints and TIMESPEC regards, UtkuArticle: 14856
On Sat, 20 Feb 1999 16:38:59 +0200, Utku Ozcan <ozcan@netas.com.tr> wrote: <snipped> 1) this won't work if you're only specifying clock constraints in the NCF, and no further timespecs. the analyser needs you to tell it about the path from the 25MHz clock, to the 12.5MHz clock, through block A, to setup for the 25MHz clock at block B (example: how does TRCE know if you have 1 * 25MHz cycle for this path, or half a cycle?) 2) try the UCF with your timespecs. if this doesn't work, you should post (a) a schematic showing how the 2 clocks are related to each other, and what clocks block A and block B, and (b) all your clock-related constraints from your UCF, and the constraints on all signals going from block A to block B. (3) the fact that there's no global buffer on the 12.5MHz clock obviously doesn't help, but TRCE should pick up any problems if the constraints are correct. evanArticle: 14857
> Yes, instatiate a BUFGP (or whatever the name is for a global buffer) > at the ouput of the clock-divider. Then you can access the global > clock routing. I do this sometimes for high fan-out non-clock signals. > There are 8 global buffers, so if you need to you should use them. BUFGP and BUFGS are for XC4000E devices, so there are BUFG, BUFGE (Global Early) and BUFGLS (Global Low Skew) buffers in XC4000XV devices. But there _is_ buffer... I haven't instantiated a buffer into HDL code. Instead I have put a synthesis directive into the HDL code which is recommended by Synplicity folks: wire cpu_clk12m /* synthesis syn_keep=1 */; This automatically instantiates a buffer at the output of the clock divider. It can be seen in RTL view of Synplify FPGA Synthesizer. > / Jonas Thor UtkuArticle: 14858
Hi - On Sat, 20 Feb 1999 16:38:59 +0200, Utku Ozcan <ozcan@netas.com.tr> wrote: > Ok. Let me explain my problem in a more detail. > > _________ _________ > Address | | Address | |----> A[x:0] > ---------->| Logic A |----------->| Logic B | (Dual Port RAM) > | 12.5 MHz| | 25 MHz |----> WR_EN > Data | (FSM) | Data | (FSM) | > ---------->|_________|----------->|_________|----> D > > Address and Data at the output of Logic A are valid for just one clock > period (in this case, at 12.5 MHz). Logic A is running at positive edge. > Logic B accepts this signals at the falling edge of the 25 MHz clock > and generates appropriate address, data and write enable signals to > the Dual Port RAM. > > Logic A and Logic B FSM's are designed and verified in functional level. > Synplify is given actual frequency values in SDC file and Global Frequency > Value has been set to 0 (zero MHz). We got the best result under this > condition. XNF netlist of Synplify is given ngduild and ngd2ver to get > the post synthesis Verilog netlist (this is recommended by Synplicity). > SDC file includes actual frequency values to the external clocks and > divided clocks (12.5 MHz internally derived from 25 MHz external clock). > I know this doesn't address your question, but I'm curious: why are you using a 25MHz clock and a 12.5MHz clock? Why not run everything off a single 25MHz clock, and create a 12.5 MHz clock enable to feed to the CE inputs of logic A? In fact, you could use your existing internally-divided 12.5MHz clock as the enable (or enable*, actually). It wouldn't need to be on a global low-skew net, as long as it sets up to the destination FFs in a 25MHz clock period. I realize there are reasons to use divide-down clocks, power savings being one. But such clocks are often unnecessary. Regards, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 14859
hi guys and gals, need to do a reality check (check got hit with a whopper bill this week), what do people pay for pcb design costs, per hour? or equivalently, a non-dense, moderately populated 10" x 11" board, components on one side, 6 layer (from netlist in to artwork out), with virtually all signals done with autorouter? (it's an easy board). thanks, rk p.s. no solicitations pleaseArticle: 14860
Ray Andraka writes: > Those are dismal clock rates for a 10K-3. I know, thanks. Data points: The average fan-in for the Handel-C version is about 3.25, while for the AHDL version it is about 2.86. The AHDL version of the program runs about twice as fast as the Handel-C version. (33MHz vs. 16.5MHz). A small prototype of the Handel-C program is happy at 40MHz. It slows down a lot as more is added to the program. This is _not_ due to increased logic depth. It is due to routing delays. > Typically arithmetic stuff slows it down, but even there you should > get about 40 MHz without cliques with 20 bit carry chains in the > logic. I disagree. Time for carry chains, arithmetic etc. are negligable in this application. Most of the delays are in I/O pipelines interfacing to external devices, and internal control/multiplexing logic. I am getting >40MHz for small programs, (>70MHz for specific things like async FIFOs), but the clock rate drops drastically as the chip fills up. There's not much I can see to do about it, except use a bigger or faster chip. I see a drastic slowdown as the chip fills, even though there is no additional logic depth. I can guarantee that because I connect together different program modules through Handel-C channels, and I have a very good idea what form the logic takes through those connections. Hint: a row of registers is guaranteed between each module's input and its output, so the logic depth is bounded as more more modules are connected together. There is considerable additional fan-*out* of some control signals; will this make a difference on a 10K? BTW, the Handel-C version does not use any hierarchy in the netlist, while the AHDL version does. Does this make a difference in your experience? It is something I will be experimenting with soon, anyway. > Sounds like you have many layers of combinatorial stuff between the > registers. Not really. There is plenty of combinational stuff, but the register-to-register logic depth does not increase much as the chip is filled, and the clock rate still slows down a lot. The critical delays are through the RAM elements. I didn't turn on the "CUT_OFF_RAM_REGISTERED_WE_PATHS" for this analysis, but I know that turning it on does increase the max frequency reported by timing analysis. (For the Handel-C program. It makes no difference to the AHDL program). It is possible timing analysis is reporting bogus timings because a lot of the combinational relationships do not have to execute in a single cycle. The combinatorial stuff is mostly multiplexers, multiplexers and more multiplexers. Control logic accounts for the rest. There's hardly any arithmetic -- just a few 16 bit carry chains, and they're lost in the noise. The multiplexers and control logic are implicit in Handel-C, and it is hard to design a large program where you know exactly what is connected to what. (It is easy to design a _small_ program where you know what's what, but this application isn't one). The AHDL version is about twice as fast as the Handel-C version (33MHz vs. 16.5MHz). However, the AHDL version was specifically tuned to multiplex just two signals in each pipeline stage, hence 1 LC logic depth. I am told this tweaking took most of the AHDL development time, and is unmaintainable -- quite possibly, it would be cheaper to buy a faster FPGA than do the design tuning. > Perhaps you should spend more time on designing to the > architecture than playing with the constraints. Been doing both, ta. See above. I have no intention of writing such unmaintainable code in Handel-C. I have gone as far as I can with "designing to the architecture", several complete rewrites in fact. And yes I do know the architecture very well. You'll notice my article talks about turning _off_ constraints, and that it's better to tweak the logic than to use timing constraints. I have done some basic retiming of the output from the Handel-C compiler to get better timings, and it does work. Is messy though. To be honest, the Flex10K architecture is not really suited to the application IMO and/or tools, but it is what I have to work with ATM. The slowdown as more pipelined logic is added is a real problem. However, adding more non-pipelined logic makes it even worse. I suspect an FPGA with more local routing (e.g. a matrix where all adjacent blocks have some local routing) would scale better with this sort of program, as the chip fills up. But I have no data to substantiate it. Does anyone else? -- JamieArticle: 14861
The syn_keep attribute on your wire tells Synplify to isolate the driver and loads
of the net. It does this by inserting a "virtual" buffer between the driver and
the
loads that is retained while Synplify is processing your design. This virtual
buffer is what you see in the RTL view. You should check the net in the
technology
mapped view to see if a clock buffer was inserted. From your posting it sounds
like no clock buffer was inserted. For very small clock nets that are internally
generated (<= 16 loads) Synplify will not insert a clock buffer. The overhead
of getting to a global clock buffer and back to the flip-flops can be worse than
just
routing the signal. You can find the 12.5 Mhz clock in the <design>.dly file and
see
what the delay was to each clock pin on this clock. If you see a large delay or
large variation in delay they that could be your problem.
Possible fixes are:
1) Make the routing of the clock net high priority to shorten the routes.
2) Floorplan the flip flops in your FSM and the clock divider into a small
region
of the chip.
3) The best solution. Don't divide the clock. Use an enable instead. This
was
Bob Perlman's suggestion and is a good one. This will eliminate clock
skew
problems.
Utku Ozcan wrote:
> > Yes, instatiate a BUFGP (or whatever the name is for a global buffer)
> > at the ouput of the clock-divider. Then you can access the global
> > clock routing. I do this sometimes for high fan-out non-clock signals.
> > There are 8 global buffers, so if you need to you should use them.
>
> BUFGP and BUFGS are for XC4000E devices, so there are BUFG, BUFGE
> (Global Early) and BUFGLS (Global Low Skew) buffers in XC4000XV devices.
>
> But there _is_ buffer... I haven't instantiated a buffer into HDL code.
> Instead I have put a synthesis directive into the HDL code which is
> recommended
> by Synplicity folks:
>
> wire cpu_clk12m /* synthesis syn_keep=1 */;
>
> This automatically instantiates a buffer at the output of the clock divider.
> It can be seen in RTL view of Synplify FPGA Synthesizer.
>
> > / Jonas Thor
>
> Utku
Article: 14862On Sat, 20 Feb 1999 16:38:59 +0200, Utku Ozcan <ozcan@netas.com.tr> wrote: Hej! > Static Timing Analyzer TRCE doesn't produce any timing error. But Design > Manager warns me that 12.5 MHz clock is using non-dedicated clock resources. > (Is there any way to dedicate divided clock to a clock network?) Yes, instatiate a BUFGP (or whatever the name is for a global buffer) at the ouput of the clock-divider. Then you can access the global clock routing. I do this sometimes for high fan-out non-clock signals. There are 8 global buffers, so if you need to you should use them. / Jonas ThorArticle: 14863
If you are a student, a Chinese student or live in Hong Kong or China you can not get a license due to the company policy! The web site is http://www. Sorry, I don't know because they no allowed me to get the license. Wong Ying From: Dennis Reynolds <dennisr@model.com> To: wongying@hkstar.com <wongying@hkstar.com> Date: Fai,19 Feb 1999 AM 12:46 Subject: RE: License Request Hi Wong Ying, Thank you for your response. I apologize but the first license sent to you was in error. Because of Model Technology policy, ModelSim is not available for educational or student use in China. We regret we are unable to comply with your request. Best regards, Dennis ReynoldsArticle: 14864
Hello I'm an electronics and telecomunications student. I'm interested in VHDL and I've got an evaluation version of Activ-VHDL (for Windows) tools (from Aldec www). Unfortunately this version works only for 30 days. This period is too small becouse I'm not very good in VHDL and I want to learn it with Aldec tools. So I'm looking for a good idea how to extend this period :) Mail me please: condorek@friko3.onet.plArticle: 14865
Hi, Does anyone know if it is possible to clock SDRAM (any vendor) at 1 MHZ or less so as to interface it with an FPGA based hardware emulator ? Thanks, Binu -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14866
Hi all, The situation are as follows: ============================= I am working on a circuit which needs 2 XC4028XL-1 to contain it. part of the circuit involve the generation of 2 slower clock signals(say, B & C) from an input clock (say, A). And then there are logics in both chips that depend on these 3 clocks. In order to reduce the race between the clocks, I use the input clock A to one chip, past through the input buffer, clock buffer and then the output buffer to form a clock A' of same rate. Thus, the delay between B & C will be much less than directly use A, B and C. Problems are as follows : ========================= when I test both chip separately, they works fine. However, if I connect them together using 2 flat cables. There are lots of glitches appear on the clocks. I suspect that the glithes are induced in the flat cables but it is only part of the story. I use a logic analyzer to look at at A, A', B & C, find out that glitches appear on A', B & C but not in A. However, B and C can no longer keep there shape. It seems that glithes are propagated to the clock generation circuitry. (but remember, A is clean). I've struggled with this problem for quite long, originally I don't expect it is that difficult. (I think many ppl have connect several FPGAs together before) But it turns out that underestimate it...... Can anyone suggest any precautions when connecting 2 FPGAs together? Thank you very much. Rgds, OliverArticle: 14867
There is a low volume mailing-list concernig this subject: opendesign@circu.its.tudelft.nl -- Rainer Dorsch Abt. Rechnerarchitektur e-mail:rainer.dorsch@informatik.uni-stuttgart.de Uni Stuttgart Tel.: 0711-7816-215Article: 14868
Krzycho schrieb: > > Hello > I'm an electronics and telecomunications student. I'm interested in VHDL > and I've got an evaluation version of Activ-VHDL (for Windows) tools > (from Aldec www). Unfortunately this version works only for 30 days. > This period is too small becouse I'm not very good in VHDL and I want to > learn it with Aldec tools. > So I'm looking for a good idea how to extend this period :) > > Mail me please: condorek@friko3.onet.pl Check out HARD DISK COPY: "HARD DISK COPY is a hard disk copying utility which copies from hard disk or image file to another hard disk or image file. HARD DISK COPY is ideal for backup, hard disk upgrade, systems transfer and multiple systems set up." http://ourworld.compuserve.com/homepages/dcf_hdcp - genearte HD image - install AVHDL, after 30 days: - restore HD image - install AVHDL ... Regards mwArticle: 14869
Apparently its a pretty straight forward thing to do... Your S/W will lookup the registry and determine what memory locations are available for writing to. A friend of mine tried it and after some time to got something to work. OK to write to/from memory is easy, but IRQ handling etc., needs some expert code. When i ventured into the world of the PLX9050 i got the HDK from KrfTech. Its about 500quid for the 95/98 version and 1000quid for NT support. Boy did it make my life easy!!. It was certainly worth the money...it even comes with a wizard that can actually generate code for you. Krftech are apparently bringing out a version of their HDK that supports a number of other platforms including Linux... My application involved using 13 boards with the PLX9050 chip. I had so many problems using the 9050 across a PCI bridge that as a last resort i decided to use the pin compatible PLX9052 device - it workedfine. You might want to look at the following sites: http://www.bluewatersystems.com/products.html or http://www.krftech.com or hhtp://www.greymatter.co.uk IainArticle: 14870
Anyone had any experience using the new Xilinx Virtex chips along with any of the development boards as yet? Cheers Daryl Bradley -- Bio-Inspired Architectures Department of Electronics University of York, UK http://www-users.york.ac.uk/~dwb105Article: 14871
How did you go? I am in the same position, Bach Electronic Eng and needing a longer evaluation period. I tried contacting them about educational deals etc. but the best they could come up with was 55% discount, and that makes it $3600. Let me know how you do, and I will let you know of anything I discover. Cheers from Australia, Cameron Watt. Krzycho wrote: > Hello > I'm an electronics and telecomunications student. I'm interested in VHDL > and I've got an evaluation version of Activ-VHDL (for Windows) tools > (from Aldec www). Unfortunately this version works only for 30 days. > This period is too small becouse I'm not very good in VHDL and I want to > learn it with Aldec tools. > So I'm looking for a good idea how to extend this period :) > > Mail me please: condorek@friko3.onet.plArticle: 14872
BTW... Asynchronous resets can be used on FFs that you want in IOB's by using the GSR net. If you look in the data sheet the GSR net is used in IOBs (fig.41 p4-44). For VHDL designs I find the best way to do this is to instantiate the STARTUP block and connect your reset to the GSR net. Not very portable I know but at least it lets you know what state your input FFs are going to be after reset or configuration. Note the last point is useful if your using a uP to configure your devices long after a hardware reset has been deasserted. Also note the GSR net is active high. Darrin NagyArticle: 14873
Hi Regards wrote: > Check out HARD DISK COPY: > "HARD DISK COPY is a hard disk copying utility which copies from > hard disk or image file to another hard disk or image file. HARD > DISK COPY is ideal for backup, hard disk upgrade, systems > transfer and multiple systems set up." I haven't got a lot of free space on HD. And I'm looking for an easier way. > http://ourworld.compuserve.com/homepages/dcf_hdcp This URL is bad :(( KrzychoArticle: 14874
Cameron Watt wrote: > > Let me know how you do, and I will let you know of anything I discover. I think it is necessary to change some register (Windows '98) but witch ??? Somebody tell me that he knows easier way than changing registers. This's all what I know to this point. I tried to change system clock bat I gained nothing by this.
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