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Hi, È«ÀºÁ¾ wrote: > hello, > > i'm looking for a PCI core in the form of VHDL or Verilog source code > that is surely synthesizable and provides all kinds of stuffs neeeded to > develop an ASIC with PCI interface. > > Please, somebody tell me who sells this kind of reliable PCI core, or > where I should find information on it. Take a look at the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). Part 1 section 4.9 lists some sources for frequently requested models. -- EdwinArticle: 17576
Freund Laurent wrote: > > - I don't find java class which allow to read the parallel port. It > seems that Java.comm parallel classes only allow to write on the > parallel port (and not to read). > Hi My suggestion is to include a software in C to interface the Java software to the board. In C it is easy to read/write to the parallel port as well as to talk to a Java program. I have implemented something like that to interface a Xilinx demoboard to a Java program, using the parallel port. Eduardo.Article: 17577
Hello, I have a problem. My issue is that we are trying to multiplex clocks on the Xilinx FPGA. Is there any known issue with multiplexing clocks through CLBs. If yes what is the solution to this problem... We have multiplexed the clocks and seem to get it working in simulation and in hardware. But we are not sure whether it is a stable solution. Are we missing something? Best wishes Pandey -- ============================================== Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17578
Hi all, I have a feeling that Xilinx is favoring Verilog over VHDL; they offered a verilog tutorial but no vhdl one, also the latest memory interface core is coded in verilog....Is this a trend I missed or they are big enough now to dictate their own preferences and ignore what I think is a fairly large vhdl user base? Any illuminating comments are velcome.. jakabArticle: 17579
Ray Andraka wrote: > A maximum performance 32x32 integer multiplier can be done in about 260 > Virtex clbs. That's about 2/3rds of an XCV50, the smallest Virtex part. Based > on the nominal 50k gate size of that part, the full blown 32x32 multiplier is > roughly 33k marketing gates (or less than 1/4 the size you projected). > > If you back off on the performance, a 16x16 multiplier, an accumulator and a > little bit of logic will give you a 32x32 multiplier with better than 30MHz data > rates in under 80 clbs. You need to design to the architecture (in this case > using partial products) to get an efficient design in an FPGA. If you just copy a > multiplier designed for an ASIC, you are likely to get dismal results in terms of > both performance and area. Damn it Ray. Just when I think I know what I'm talking about, you have to come along and screw it all up! This is the second time you've done that to me. I'm warning you! :) I guess it's time I go and read your web page on multiplication. When are you going to update that page to include more information on Booth's algorithm and multiplying signed numbers? David Kessner davidk@free-ip.com http://www.free-ip.comArticle: 17580
I was wondering if anyone has a behavioural model of a UART (Universal Asynchronous Receiver Transmitter) that can be easily sythesized. A free version would be preferred. Or if someone could point to some resources so I can write my own that would be great. This UART is to go inside a Xilinx 4028EX. Cheers, TimArticle: 17581
Jan Vorbrueggen wrote: > Alec Cawley <alec@cawley.demon.co.uk> writes: > > > The original transputer idea was, I think, that all > > data would fit into the on-chip ram, and sometimes the program as well. > > There are machines where this is the case - I think DRA Malvern built a radar > deconvolver based on ~400 T2s that had no external memory. It all fit into a > 19 inch enclosure less than 10cm high. Of course, if you do a custom design in an FPGA, the entire radar signal processor can fit in a chip or three depending on the processing involved. For example, a doppler pulse pair processor can fit in one FPGA, including complex demodulation from IF and matched filtering. Look for my paper at the Asilomar conference at the end of October for that example. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17582
The main problem with multiplexing clocks is that stable, portable designs should be syncronous. When you "switch" to another clock, you can get glitches on the clock lines as it propagates through the device. -- Keith F. Jasinski, Jr. kfjasins@execpc.com Shardendu Pandey <pandey@my-deja.com> wrote in message news:7os0cp$8gs$1@nnrp1.deja.com... > Hello, > > I have a problem. My issue is that > we are trying to multiplex clocks > on the Xilinx FPGA. Is there any > known issue with multiplexing clocks > through CLBs. If yes what is the > solution to this problem... > > > We have multiplexed the clocks > and seem to get it working in > simulation and in hardware. But > we are not sure whether it is a > stable solution. > Are we missing something? > > > Best wishes > Pandey > > -- > ============================================== > > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't.Article: 17583
Depends on your coding style and how much floorplanning you are willing to do. The LPMs are "optimized" designs for the target FPGA architecture, and they are often floorplanned too. I put optimized in quotes because more often than not, the optimization seems to be a compromise between conflicting goals. A faster design may take up more resources than a slower one for example. LPMs do allow someone less familiar with the device architecture to get better performance/density than he might otherwise. However, LPMs come at a cost: First, they are a pain for simulation. Second, the LPM boundaries are usually "hard" so surrounding logic often won't get absorbed in optimization. Most of the LPM functions are pretty simple. In schematic based designs, they can hide details like carry chain (which can be confusing) implementation. A good synthesizer can generate the carry chain logic without resorting to LPMs, so their usefulness is diminished. I personally don't use the LPMs much because with usually little effort I can meet or exceed the performance and/or density of the LPMs without the associated headaches. So the short answer is: No, you don't need to use LPMs to minimize area or maximize performance, but you need to know the implementation that will get you minimum area and how to write the VHDL to get that implementation. Generally speaking, if you write at an RTL level so that the logic between each register is explicitly defined, you get pretty close. For xilinx, you may also have to go into the floorplanner to layout the design to obtain the performance of the LPM. In Altera, that is less critical. Asher C. Martin wrote: > Greetings, > > Thanks for the advice... would anyone happen to know if LPM functions > are necessary to reduce the amount of space that VHDL takes up on an > FPGA? > > Best regards, > > >Asher< > > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> > Asher C. Martin > 805 West Oregon Street > Urbana, IL 61801-3825 > (217) 367-3877 > E-MAIL: martin2@acm.uiuc.edu > http://fermi.isdn.uiuc.edu > telnet://fermi.isdn.uiuc.edu > ftp://feynman.isdn.uiuc.edu > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17584
In article <37B18B6E.3CCC714D@ics-ltd.com>, jakab tanko <jtanko@ics-ltd.com> wrote: >Hi all, >I have a feeling that Xilinx is favoring Verilog over >VHDL; they offered a verilog tutorial but no vhdl one, >also the latest memory interface core is coded in >verilog....Is this a trend I missed or they are big >enough now to dictate their own preferences and >ignore what I think is a fairly large vhdl user base? >Any illuminating comments are velcome.. We (Xilinx) aren't advocating any particular design entry language and don't see a need to do so. We provide both VHDL and Verilog simulation libraries. The CoreGen tool provides both VHDL and Verilog behavioral models and VHDL component and Verilog module templates. The Xilinx implementation tools can back-annotated final place and route information for simulation in both VHDL and Verilog. The standard tutorials are written in both VHDL and Verilog and can be found at: http://support.xilinx.com/support/techsup/tutorials/tutorials21i.htm You can also find HDL design techniques for both VHDL and Verilog at http://support.xilinx.com/apps/hdl.htm And in the latest SW releases we have an evaluation copy of the ModelTech simulator that works with both VHDL and Verilog. Hopefully this clears up any perceived HDL bias. Ed McGettigan Xilinx Inc.Article: 17585
Hi, Tim Warnes wrote: > I was wondering if anyone has a behavioural model of a UART (Universal > Asynchronous Receiver Transmitter) that can be easily sythesized. A free > version would be preferred. Or if someone could point to some resources so I > can write my own that would be great. This UART is to go inside a Xilinx > 4028EX. > Take a look at part 1 section 4.9 of the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). It lists some sources for frequently requested models. -- EdwinArticle: 17586
Anna Acevedo (anna.acevedo@xilinx.com) wrote:
: See http://www.xilinx.com/programs/xse1.htm for complete information on the
: Xilinx Student Edition Software.
: Ram Meenakshisundaram wrote:
: > I have a homebrew card that contains an inmos T425 transputer connected
: > to a Xilinx XC4000E-3 FPGA and a Motorola DSP56002 DSP processor.
: > I ordered the Xilinx Student Edition 1.5 from Barnes & Nobles. What are
: > the limitiations of the tools that come with the book? What is the max
: > number of gates that I can use using these tools? And is there a FAQ on
: > FPGA? Now, this is my first look into FPGA, so I pretty much no nothing
: > about it. Thanks.
If it's like mine, you can use OpenABEL and the schematic-based
design entry out-of-the-box. If you want to use the VHDL tools,
you have to register. That includes providing the name of your
school, your instructor, course number, and expected date of graduation.
Not exactly conducive to hobbiest use.
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 17587--------------81E8026024DC969750B827F5 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit "Keith Jasinski, Jr." wrote: > The main problem with multiplexing clocks is that stable, portable designs > should be syncronous. When you "switch" to another clock, you can get > glitches on the clock lines as it propagates through the device. > It's not quite that bad. Click on http://www.xilinx.com/xcell/xl24/xl24_20.pdf for a description of " Trouble-Free Switching Between Asynchronous Clocks". This design once led to a spirited exchange in this newsgroup about the perils of metastability, but I am still defending this particular circuit idea as being safe. Peter Alfke, Xilinx Applications --------------81E8026024DC969750B827F5 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>"Keith Jasinski, Jr." wrote: <blockquote TYPE=CITE>The main problem with multiplexing clocks is that stable, portable designs <br>should be syncronous. When you "switch" to another clock, you can get <br>glitches on the clock lines as it propagates through the device. <br> </blockquote> It's not quite that bad. Click on <p><u><A HREF="http://www.xilinx.com/xcell/xl24/xl24_20.pdf">http://www.xilinx.com/xcell/xl24/xl24_20.pdf</A></u><u></u> <p>for a description of <br>" Trouble-Free Switching Between Asynchronous Clocks". <p>This design once led to a spirited exchange in this newsgroup about the perils of metastability, but I am still defending this particular circuit idea as being safe. <p>Peter Alfke, Xilinx Applications</html> --------------81E8026024DC969750B827F5--Article: 17588
--------------D45626FF83DBE5C45EE27F0D Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit "Keith Jasinski, Jr." wrote: > The main problem with multiplexing clocks is that stable, portable designs > should be syncronous. When you "switch" to another clock, you can get > glitches on the clock lines as it propagates through the device. It's not quite that bad. Click on http://www.xilinx.com/xcell/xl24/xl24_20.pdf for a description of " Trouble-Free Switching Between Asynchronous Clocks". This design once led to a spirited exchange in this newsgroup about the perils of metastability, but I am still defending this particular circuit idea as being safe. Peter Alfke, Xilinx Applications --------------D45626FF83DBE5C45EE27F0D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>"Keith Jasinski, Jr." wrote: <blockquote TYPE=CITE>The main problem with multiplexing clocks is that stable, portable designs <br>should be syncronous. When you "switch" to another clock, you can get <br>glitches on the clock lines as it propagates through the device.</blockquote> It's not quite that bad. Click on <p><u><A HREF="http://www.xilinx.com/xcell/xl24/xl24_20.pdf">http://www.xilinx.com/xcell/xl24/xl24_20.pdf</A></u> <p>for a description of <br>" Trouble-Free Switching Between Asynchronous Clocks". <p>This design once led to a spirited exchange in this newsgroup about the perils of metastability, but I am still defending this particular circuit idea as being safe. <p>Peter Alfke, Xilinx Applications</html> --------------D45626FF83DBE5C45EE27F0D--Article: 17589
Hi,
I apologize if this message does not belong to this newsgroup......
Does anyone know any I/O board that interface the WildForce board
from Annapolis Micro to the analog world? I contacted them but they do
not have anything available, and there is no information on any third
party support on this topic. I also tried some companies making Data
Acquisition board, but almost all of them have sample rate of less than
5MSPS, and none of them has the bandwidth we need.
I would appreciate if any of you who has done the interface can
inform me about your approach. Is there any off-the-shelf products
available that has high sample rate ( >10MSPS) and good resolution
(10-12bits), or do you simply custom-make your own?
Artur
8.11.99
Article: 17590Does anyone know of a good tool to convert .jed files to boolean? I know that Viewlogic comes with j2vhdl or jtowhatever but I cannot get it to work. Is there any others I could look at? Also, if you have successfully used j2vhdl or similar, please send/post a known working example. I want to convert a .jed in a 18CV8 to a CPLD. If I could just extract the boolean eq, the rest would be easy. Thanks! Please reply to: apco25@ZZten.net take out the ZZ to e-mail.Article: 17591
David Kessner wrote: > Damn it Ray. Just when I think I know what I'm talking about, you > have to come along and screw it all up! This is the second time you've > done that to me. I'm warning you! :) I guess I'm on a roll. Sorry to let the steam out of your kettle twice in a row there (I honestly didn't realize I nailed you twice). Just don't go letting the air out of my tires now :-) > I guess it's time I go and read your web page on multiplication. > When are you going to update that page to include more information > on Booth's algorithm and multiplying signed numbers? In my spare time! Yes, it is on my list of things to do, but it just hasn't percolated to the top. For signed multipliers, the easiest way to picture the correction is to substitute -2^n for 2^n for the msb weighting. For example, an 8 bit signed (2's complement) number is correctly weighted -128,64,32,16,8,4,2,1. Do that, and the correction for signed multiplication becomes easy to see. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17592
I have a problem in programming a 22V10 using Orcad express version
7.2.and VHDL.
A simple 8-bit synchronous counter programs fine, but I cannot find any
way of controlling the tri-state gates on the outputs. If I include any
reference to "ZZZZZZZZ",
e.g. cntr<=std_logic_vector(present_count) when (enable='1')
else "ZZZZZZZZ"
the enable lines for the macrocells are connected to the input pin, but
the configuration fuses (5808 upwards) are all set to the combinational
mode (11 instead of 10).
Has any one any suggestions?
Gil Harrison
Article: 17593
Hello ....
I have designed some logics which uses xilinx SelectRAM Libraries.
But when simulating on vhdlsim of synopsys tools, the vhdlsim
puts some errors like this before loading the design is completed.
Now I use synopsys simulation version 1998.08-1 and alliance 2.1i.
When I used synopsys simulation version 1998.08, no problem occured.
But after synopsys simulation tools was upgraded, the Errors are encountered.
Does any one know why this errors occur ??
**Internal Error: vhdlsim:
Please report (couldn't find root).
FAULT CONTEXT
Program : 'vhdlsim'
Release : '1998.08-1'
Architecture : 'sparcOS5'
Phase : <null>
Last UI Command : <null>
Simulation Time : 0 NS
FAULT ID:
'1959228 1960632 1992680 2089520 2093164 2095972 2096216 2095804 2094904 824540 683376 369836'
Regards...
Boumjin
Article: 17594This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_001_01BEE4C0.0267B0DA Content-Type: text/plain; charset="koi8-r" Dear colleagues, I've heard a lot of good words about XILINX Floorplanner. But where can I read its manual? Thanks, Alex Sherstuk ------_=_NextPart_001_01BEE4C0.0267B0DA Content-Type: text/html; charset="koi8-r" <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"> <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=koi8-r"> <META NAME="Generator" CONTENT="MS Exchange Server version 5.5.2448.0"> <TITLE>Foundation F1.5i Floorplanner document - ?</TITLE> </HEAD> <BODY> <P><FONT SIZE=2 FACE="Arial">Dear colleagues,</FONT> </P> <P><FONT SIZE=2 FACE="Arial"> I've heard a lot of good words about XILINX Floorplanner.</FONT> <BR><FONT SIZE=2 FACE="Arial">But where can I read its manual?</FONT> </P> <P><FONT SIZE=2 FACE="Arial">Thanks,</FONT> <BR><FONT SIZE=2 FACE="Arial"> Alex Sherstuk</FONT> </P> </BODY> </HTML> ------_=_NextPart_001_01BEE4C0.0267B0DA--Article: 17595
The manual is on xilinx's website in pdf form at http://www.xilinx.com/techdocs/htm_index/docs_M1.htm . If you have the xilinx tools, it should be in the online docs that came with the tools; make sure you install the documentation. The floorplanner in 1.5 is buggy and incomplete compared with the one in the xact6 software. It is supposed to be fixed in 2.1, which was just released a month or so ago. I haven't run the new floorplanner through the wringer yet, so I don't know how much is still broken. One good thing about the one in 2.1 is that it finally supports Virtex. Alexander Sherstuk wrote: > I've heard a lot of good words about XILINX Floorplanner. > But where can I read its manual? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17596
Have a look at the National semiconductor CLC016. Will auto sync to four data rates. Eirik Esp wrote in message <7nk6gp$603$1@pyrite.mv.net>... >I am looking at trying to extract clock & data from a ~100 MHz NRZ serial >data stream. I was just wondering if anyone has tried this and had any >successes of failures to report? Any suggestions? > >Article: 17597
Vacancies at Philips Semiconductors Nijmegen, NL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Philips Semiconductors is one of the world's biggest manufacturers of ICs with design and manufacturing centres in different countries all over the world. In Nijmegen, the Netherlands, Philips Semiconductors employs today about 4000 people working in various design departments, five wafer fabs and one test fab. Within Business Line Cellular in Nijmegen there are vacancies in the area of digital design at present. Business Line Cellular develops and produces IC's for telecom terminals (e.g. mobile phones). These are in general complex digital or mixed-signal CMOS IC's consisting of a microprocessor (80C51, ARM), digital signal processor (DSP) and digital and mixed-signal peripherals (e.g. UART's, IIC, A/D and D/A converters, power management functions). PRINCIPAL DESIGN ENGINEER (DIGITAL DESIGN) The Principal Design Engineer is expected to play a leading role during the definition phase of new projects, making recommendations on architecture, test strategy, tool flow, resource requirements and technology for specific projects. On occasion the Principal Design Engineer may be asked to lead Project teams, and candidates should therefore have some experience of leading teams of engineers. Candidates are further expected to be experienced engineers who have knowledge of the complete digital design flow from specification to layout and timing verification. Requirements: * B.Sc/M.Sc.EE. or comparable level. * Experience in developing digital circuits for CMOS processes. * Able to work independently. * Good communication skills. If you are interested to work in an international and expanding environment with challenging and innovative products, please send/email your application/CV to :- Kenneth Currie Philips Semiconductors, BL Cellular, FB3, Gerstweg 2, 6534 AE Nijmegen, The Netherlands mailto:K.Currie@nym.sc.philips.comArticle: 17598
Does anyone here have any experence with the XILINX 4000 series logic? I am attempting to parrallel load a 4020 and the load is failing. I'm using the same bits as would program the chip in serial mod through the Xchecker cable. any help here? & thanks much.Article: 17599
z0rbaf@newsguy.com wrote: > Does anyone here have any experence with the XILINX > 4000 series logic? I am attempting to parrallel load > a 4020 and the load is failing. I'm using the same > bits as would program the chip in serial mod through > the Xchecker cable. any help here? & thanks much. Lots of people have lots of good experience with XC4000-series devices. I happen to be the resident guru on configuration issues, so I suggest you e-mail me your details. But please also give me your real name. Did you read my app notes: "FPGA Configuration Guidelines", "Configuration Issues", and "Dynamic Reconfiguration" near the back-end of the Xilinx data book ? The first suggestion is always to monitor the Dout pin, where the 40-bit preamble must appear if the configuration process ever even got started. We can then guide you through the rest of your problems. Satisfaction guaranteed! Peter Alfke, Xilinx Applications
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Compare FPGA features and resources
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