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Daryl Bradley wrote: > have a look at www.xess.com > > THey have a virtex board coming soon with memory on it > Haven't looked at the specs but maybe suitable? yes, there's quite a lot on that board, although not quite enough memory. will ask them if they can fit it with more thanks, SukandarArticle: 17726
Bill Blyth wrote: > The Virtex boards from Alpha Data have separate memory interfaces with > SRAM and SSRAM. Size might be a problem. RC1000 has 4 x 512k x 32 SRAM. > ADM-XRC has 4 x 128k(256,512) x 36. > Try www.alphadata.co.uk. yes, nice boards. I'm in contact with them thanks, SukandarArticle: 17727
Jonathan Feifarek wrote: > Signalware (www.signalware.com) makes several plug-in boards hmm, not much on their website.....I could only find a C50 based board which is slightly under-powered for our needs. also www.signalware.com redirects automatically to www.qwest.net/ipcommerce/SNI/ (now it's www.sni.net/dsp/index.htm) > (I assume 24 bits mean 8 bits per > color channel), yes thanks, SukandarArticle: 17728
Daniel Figuerola Estrada wrote: > Has anyone worked with those two technologies and could give his opinion > of them? Why look at them as mutually exclusive? We develop a controller board (very small, PCMCIA form-factor) that has both a microcontroller AND an FPGA. This allows for some amazing flexibility and utility. Especially because of all sorts of neat devices already on the die on the uC. We run the FPGA at twice the clock speed of the uC, and operate networking, flash/memory interface, ADC, and many more things in there. We run our Fuzzy and PID control in the uC.. it's perfect. If you look at straight logic, you can also get amazing performance for cost, weight, and power. Any comparisons are strictly dependant on a specific application, but for many of our trade-off studies. A logic only node can beat an embedded PowerPC!! In the end though, it's apples and oranges, so why not have fruit salad? =) Joshua Lamorie Systems Designer Xiphos Technologies Inc.Article: 17729
Depends on the design, your skills and the device. There's a good chance you'll need to instantiate at a low level to get the constructs you need unless you know your synthesis tool inside out (and probably even then). You're also probably going to have to floorplan to keep routes tight. It is certainly possible to do a 200MHz design in the current crop of fast parts, but you aren't going to do it by accident. thiru1457@my-deja.com wrote: > Hi, > > I intend to implement a logic in FPGA (roughly > 12K logic gates complexity), running at 200 MHz. > > Is it possible to implement the above design, > with the current FPGA technology?. > > How difficult it would be (interms of manweeks) > for synthesis and "place and route" the above > design. > > Thanks in advance for your response. > > -Regards > > Thiru > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17730
The UCF will only let you use LOC constraints, not RLOCs and you won't be able to nail down the OR gate there. Instead, put an FMAP around the OR gate (in parallel with it), and attach RLOC=R0C0 constraints to both flip-flops, and to the FMAP. Read the chapter on constraints in the online user's guides. Heinrich Fonfara wrote: > Hi, > can somebody tell me how to constrain two FFs that synchronize two > different signals with the same clock followed by a simple or-gate to be > implemented into one Xilinx XC4005 CLB. > I use schematic entry from OrCAD and the usage of constraints is very > similar to that of Xilinx Foundation entry. I also use an UCF-file. > > Regards, > > Heinrich Fonfara -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17731
Depends on the size of the multiplier, obviously. The efficient parallel multiplier can do a 2xN partial product in N LUTs (2 per slice). You need to compute m/2 2xN partial products for an n x m multiplier. Those partial products are summed in an adder tree, which requires one LUT per adder bit. Some of the adders will need to have wired shifts in front of them to handle the weighting of the individual partial products. Please refer to the multiplier page under the DSP section on my website for more detail on multiplication in FPGAs. For an area optimization, you could go with a multiple of the data rate to share hardware over multiple partial products, again refer to my multiplier page. Pieter Op de Beeck wrote: > Can anyone give me the total number of CLBs for a multiplier (area or > performance optimized) in a Virtex ? Is this the same as for the 4000 > family (why not?)? > > Thanks, > Pieter -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17732
For higher data rate stuff, no question about using FPGAs. For lower data rates, bit serial designs in
FPGAs can make for a low power and very compact design. FPGA design is made more difficult, but not
impossible, if there is lots of exception handling.
I have to argue with the chap who at the beginning of this thread says microcontrollers are always more
maintanable and cheaper for silicon and tools. I recently looked at a microprocessor application, that
by the time we got the RTOS, the compilers, debuggers etc, we would have spent several times the cost
of basic FPGA tools, and even a bit more than a Synplicity synthesis suite with the RTL analyst. With
proper FPGA design, there is no need to have to move pins. I've done several hundred high speed FPGA
designs now, and I don't think I've ever had to move a pin. The key is to pick the pin assignments
wisely (hint don't let the tool do it for you) and register at the I/O whenever possible. BTW, the
Xilinx 3000 series, the Atmel 6K series, and Actel Act 1 families are all about 10 years old, and are
all still available today.
Dave Vanden Bout wrote:
> microcontrollers - used for low-speed I/O (KHz range) and algorithms with complicated control flow.
> FPGAs - used for high-speed I/O (MHz range) and algorithms with simple control flow.
>
> Daniel Figuerola Estrada wrote:
>
> > I am making a project in wich I compare advantages and disadvantages in
> > using microcontrollers and FPGA in the design of a digital system.
> >
> > Has anyone worked with those two technologies and could give his opinion
> > of them?
> >
> > ------------------------------------------------------------------------
> > ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> > // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> > // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> > // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> > \//////////////////////////////// (il),-'' (li),' ((!.-'
> > ------------------------------------------------------------------------
>
> ------------------------------------------------------------------------
>
> Dave Vanden Bout <devb@xess.com>
> FPGA Product Manager
> XESS Corp.
>
> Dave Vanden Bout
> FPGA Product Manager <devb@xess.com>
> XESS Corp.
> 2608 Sweetgum Drive Fax: (919) 387-1302
> Apex Work: (919) 387-0076
> NC Netscape Conference Address
> 27502
> USA
> Additional Information:
> Last Name Vanden Bout
> First Name David
> Version 2.1
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 17733Try Visicom or Coreco (formerly dipix). I think both have boards that might meet your needs. Sukandar Kartadinata wrote: > Hi everybody, > I'm looking for a DSP/FPGA development system to do the following: > > Capture the RGB output (1280x1024, 75Hz, 24bit) of a standard PC (Mac, > SGI, etc.), do some processing, then output RGB again. > (btw, there is a reason why I don't do the processing within the PC) > > Processing: 2D spatial transformations like zooms and shifts but also > more complex according to displacement maps. Plus 4pt. bilinear > interpolation > > In particular I couldn't find any frame grabbers that can handle the > high pixelrates of almost 100Mpixel/s. Usually they're targeted at video > capturing with max. 40Mpixel/s. Also, most frame grabbers are PCI cards > - I'm looking for an embedded system solution. > > Another problem is memory bandwitdh. Apart from accessing the image > buffer at least 4 times (for the interpolation) I also have to pipe in > the displacement and interpolation data. > > What I did find is an ADC from AD (AD9884) that might at least be suited > for the converting, although it's mainly targeted at LCD monitors. > However, I'd really like to avoid messing too much with the hardware. > > In general I'd prefer a "one-supplier-solution" rather than buying > components from different companies. I'd also be willing to spent some > money on a nice software environmant rather than doing everything from > scratch in assembler. > > Finally, does anyone know a newsgroup that specializes on image > processing (like the music-dsp list does for sound) ?? > > Thanks, > Sukandar > sk@zkm.de -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17734
test!Article: 17735
Hi, Is it wise to cascade two frequency multipliers in the form of PLLs in VIRTEX chips in order to get a high multiplication factor (within the frequency limits of course), e.g. cascade PLLX4 and PLLX8 to obtain a multipication factor of 32=4x8. Is there any limitation other than the maximum PLL output frequency? Thanx, GeorgeArticle: 17736
Ray Andraka wrote: > Try Visicom or Coreco (formerly dipix). I think both have boards that might > meet your needs. Thanks, but as far as I can see all their products max out at 40MHz for capture, whereas we'd need 1280 x 1024 x 24bit x 75Hz = 100MHz..... SukandarArticle: 17737
Ray Andraka wrote: > Try Visicom or Coreco (formerly dipix). I think both have boards that might > meet your needs. Thanks, but as far as I can see all their products max out at 40MHz for capture, whereas we'd need 1280 x 1024 x 24bit x 75Hz = 100MHz..... SukandarArticle: 17738
Kevin, Do you have high frequency clock available? Say 10MHz or some such frequency? An alternative is to us a momentary switch that is single pole and two throw. It is less common, but the debounce curcuits are a pair of cross coupled NAND or NOR gates. Clyde Kevin Toliver wrote: > Can anyone tell me where to find vhdl code to debounce and latch a input > from a momentary switch? > > Regards, > > KevinArticle: 17739
The following was posted June 11 th of this year, and is almost certainly an answer to your problem: ============================== A friend and I have just been through exactly this problem: Student edition F1.5 hangs in the router. We also had crashes in the mapper. The solution to both was to apply BOTH the F1.5 service pack, and the version 2 hot fix to that service pack. Do not apply F1.5i service packs to version F1.5, it wont work. The main service pack is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip and the increment is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip For ref, see this for warnings http://www.xilinx.com/techdocs/4897.htm Some of the problems seem to be related to having visual C++ V 6.0 on your system. Philip Freidin ===================================== You wrote: In article <37C68FD6.45617301@ini.phys.ethz.ch>, Tobi Delbruck <tobi@ini.phys.ethz.ch> wrote: >i got xilinx student edition v1.5, installed it on my windows NT machine, >and it immediately >started bombing at the "map" stage of implementation, with access violation >at address 0x78001799. >this happens even after i installed the service pack for 1.5. also, i do >NOT have microsoft >visual studio installed. it could be some other application installed a >bad microsoft DLL. >but i read in the xilinx tech notes that xilinx decided they did NOT think >it was due >to this DLL. anyhow, it is all very confusing and unsatisfying because i >cannot >even compile a simple AND gate to my nice, brand new 4010 XS40 XESS board. > >does anyone know the real fix to this, besides buying for $500 the >university edition >of 2.1? (assuming that fixed it). > >thanks! >-tobi delbruck > >Bob Pearson wrote: > >> Hi, >> >> Has any one encountered a situation where M1.5i >> map get hung apparently in an infinite loop? And >> if so what was the cause? >> >> Thanks for any help >> >> Bob Pearson >> bpearson@pmr.com > > > >-- >Tobi Delbruck >Institute of Neuroinformatics, UniZ/ETHZ >Winterthurerstr. 190 >8057 Zurich, Switzerland >phone +41 1/635 30 38 fax +41 1/635 30 53 >tobi@ini.phys.ethz.ch ><http://www.ini.unizh.ch/~tobi> > >Article: 17740
thiru1457@my-deja.com wrote: > I intend to implement a logic in FPGA (roughly > 12K logic gates complexity), running at 200 MHz. > > Is it possible to implement the above design, > with the current FPGA technology?. It is impossible to estimate practicality or effort needed without any more information. The size is no problem. The speed might be a problem. The path from flip flop, through any routing and/or logic, to setup into the next flip flop needs to be 5 ns or less for all paths (with a few exceptions) for a design running at 200 MHz. To route a signal a significant distance may well take several ns. To get a design to work at such speeds there can be at most only a few levels of logic between each flip flop, and not much routing, or perhaps a longer route (or a route with large fanout), and a single 4in-LUT (four input look up table). The layout of the design also matters because longer routes take more time. If the design is regular and needs to communicate only to a few of the nearest neighbor logic cells then it might be made to run very fast. If communication needs to be very general, it might be very hard to make run fast. If the design is regular and rectangular it might be made to run very fast. Very irregular logic is very difficult to place. Some non rectangular logic is hard to place, and some is fairly easy. If your design is already structured into simple logic between pipeline stages that can be easily floorplanned into a regular rectangular structure, a design like this might be done in 2 to 6 person weeks by an experienced FPGA designer. It also might take a few person years of effort to fit the design into the next generation of FGPAs, defined for this statement as twice as fast as the current generation. It's also very possible that your design can't be done with existing FPGAs at all, even assuming a factor of two speedup for the next generation, regardless of effort, regardless of experience. The questions you need to ask are: 1) can the design be pipelined "enough"? (How much time will this take?) 2) what is the "shape" of the parts of design? How can they be floorplanned to minimize route lengths and delays? Best of luck. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 17741
Yes, there is a min/max frequency range for the DLLs. I don't recall offhand what the minimum reference frequency is, but IIRC, you can't get a 32x clock multiplication because you either violate the maximum DLL frequency or the minimum reference. George wrote: > Hi, > > Is it wise to cascade two frequency multipliers in the form of PLLs in > VIRTEX chips in order to get a high multiplication factor (within the > frequency limits of course), e.g. cascade PLLX4 and PLLX8 to obtain a > multipication factor of 32=4x8. Is there any limitation other than the > maximum PLL output frequency? > > Thanx, > > George -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17742
Joshua Lamorie wrote in message <37C6A794.EA82B0AA@xiphos.ca>... >Gidday there, > > I'm currently climbing up the learning curve with FPGA Express, and >porting my VHDL (isn't that a silly statement) from Cypress Warp. I >keep getting the following error on my code. > >Error L-1/C0:#0 Not enough storage is available to complete this >operation. > > According to the Xilinx Answer #5301, this is due to underscores within >binary strings. However, though I am using binary strings, I do not >have any underscores. You can find the answer at: > >http://www.xilinx.com/techdocs/5301.htm > > Actually, it can't be anything with the strings, I just can't get past >this step. Is there a patch somewhere? The software was installed by a >Xilinx FAE, with about 30 CDs (exageration). So, maybe he missed one. > > Any hints would be greatly appreciated. > >Joshua Lamorie >Systems Designer >Xiphos Technologies Inc. > >ps. Some specs > >PC: P-II 350 w/128MB RAM 270MB Virtual >OS: NT4 SP5 >Foundation: F1.5 Build 3.1.140 >FPGA Express: 3.1.1.0w Try downloading Service Pack 2 for F1.5. -- a ---------------------------------------------------------------------------- -- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories apeters (at) noao.edu The Repulican Party: "We've upped our standards. Now, up yours!"Article: 17743
thank you thank you thank you! that version 2 hot fix (which just replaces about 10 files in nt/bin, including "map", did in fact kill the crashing map problem. the techdocs/4897.htm technote seems to have disappeared from the index and trying to access it says it doesn't exist anymore. so i don't know what it says, but so what - it runs now! -tobi Philip Freidin wrote: > The following was posted June 11 th of this year, and is almost > certainly an answer to your problem: > > ============================== > A friend and I have just been through exactly this problem: Student > edition F1.5 hangs in the router. We also had crashes in the mapper. > > The solution to both was to apply BOTH the F1.5 service pack, and the > version 2 hot fix to that service pack. Do not apply F1.5i service packs > to version F1.5, it wont work. > > The main service pack is at > ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip > > and the increment is at > ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip > > For ref, see this for warnings > http://www.xilinx.com/techdocs/4897.htm > > Some of the problems seem to be related to having visual C++ V 6.0 on > your system. > > Philip Freidin > > ===================================== > > You wrote: > > In article <37C68FD6.45617301@ini.phys.ethz.ch>, > Tobi Delbruck <tobi@ini.phys.ethz.ch> wrote: > >i got xilinx student edition v1.5, installed it on my windows NT machine, > >and it immediately > >started bombing at the "map" stage of implementation, with access violation > >at address 0x78001799. > >this happens even after i installed the service pack for 1.5. also, i do > >NOT have microsoft > >visual studio installed. it could be some other application installed a > >bad microsoft DLL. > >but i read in the xilinx tech notes that xilinx decided they did NOT think > >it was due > >to this DLL. anyhow, it is all very confusing and unsatisfying because i > >cannot > >even compile a simple AND gate to my nice, brand new 4010 XS40 XESS board. > > > >does anyone know the real fix to this, besides buying for $500 the > >university edition > >of 2.1? (assuming that fixed it). > > > >thanks! > >-tobi delbruck > > > >Bob Pearson wrote: > > > >> Hi, > >> > >> Has any one encountered a situation where M1.5i > >> map get hung apparently in an infinite loop? And > >> if so what was the cause? > >> > >> Thanks for any help > >> > >> Bob Pearson > >> bpearson@pmr.com > > > > > > > >-- > >Tobi Delbruck > >Institute of Neuroinformatics, UniZ/ETHZ > >Winterthurerstr. 190 > >8057 Zurich, Switzerland > >phone +41 1/635 30 38 fax +41 1/635 30 53 > >tobi@ini.phys.ethz.ch > ><http://www.ini.unizh.ch/~tobi> > > > > -- Tobi Delbruck Institute of Neuroinformatics, UniZ/ETHZ Winterthurerstr. 190 8057 Zurich, Switzerland phone +41 1/635 30 38 fax +41 1/635 30 53 tobi@ini.phys.ethz.ch <http://www.ini.unizh.ch/~tobi>Article: 17744
Hi, I am working with the 4085xla device and running xact m1.5. The size of the configuration files (.rbt, .bit) generated in my most recent run does not match the size from previous runs. The bits printed in the .rbt file are still 1924992. Should I be concerned about this size mismatch? (The design does not work and I was wondering if this could be a reason.) ls -lt foo* all previous designs: v1/foo1.rbt 1927897 v1/foo1.bit 240697 new design: v2/foo1.rbt 1927901 v2/foo1.bit 240701 thanks, asa kalavade@lucent.comArticle: 17745
Slight variations in length of the .RBT amd .BIT files is
normal. For instance, I have a XC4085XLA design with the
following lengths:
design.BIT 240699
design.RBT 1930623
The variation in length is due to the fact that both file
formats include a variable length header, prior to the
actual bit stream itself. You can check this easily by
looking at the header of the .RBT:
Xilinx ASCII Bitstream
Created by Bitstream M1.5.28i
Design name: design.ncd
Architecture: xc4000xl
Part: 4085xlbg560
Date: Fri Jul 09 01:01:24 1999
Bits: 1924992 <<<< check this, it
<<<< should not change.
Good luck,
Philip Freidin
In article <37C955DF.61772FC3@bell-labs.com>,
Asa Kalavade <kalavade@bell-labs.com> wrote:
>
>Hi,
>I am working with the 4085xla device and running xact m1.5.
>The size of the configuration files (.rbt, .bit) generated
>in my most recent run does not match the size from previous
>runs. The bits printed in the .rbt file are still 1924992.
>
>Should I be concerned about this size mismatch? (The design
>does not work and I was wondering if this could be a reason.)
>
>ls -lt foo*
>all previous designs:
>v1/foo1.rbt 1927897
>v1/foo1.bit 240697
>
>new design:
>v2/foo1.rbt 1927901
>v2/foo1.bit 240701
>
>thanks,
>asa
>kalavade@lucent.com
Article: 17746I'm attempting to add some UK-oriented *companies* to my programmable logic links (at http://www.alife.co.uk/links/hardware/). So far I've come up with the following list: http://www.embedded-solutions.ltd.uk/ Embedded solutions - boards http://www.alphadata.co.uk/hardhome.html Alphadata - FPGA boards http://www.nallatech.com/ Nallatech - FPGA boards http://www.microcall.memec.com/xilinx/xilinx.htm Micro Call Ltd http://www.entegra.co.uk/ EnTegra Ltd Home Page - in the DSP field... http://www.doulos.co.uk/ VHDL/Verilog training and HDL-based FPGA designs http://www.orcad.co.uk/europe/products/products_f.htm Orcad Express. http://www.archaeoptryx.co.uk/ Xilinx Full Chip Design VHDL/Verilog http://www.saros.co.uk/ VHDL and Verilog design tools http://www.eda.co.uk/ - makers of "Protel for Windows" http://www.nmi.co.uk/ip.htm NMI If I've missed any prominent companies, please feel free to mail me their URLs. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Some things have to be believed to be seen.Article: 17747
Joshua Lamorie wrote: > > Rickman wrote: > <snip> > We have decided to go with an Altera device, because it is the > smallest. > > The only question remaining is converting the output from the Xilinx software > (some sort of bit file) into an SVF, or JAM file required by the Altera JTAG > programmer. Or, I hack together a JTAG programmer of my own. Any hints? Ask Altera. Another option, given the 'high' prices of these FPGA serial memories, is a uC and other memory. Fairchild TSSOP8 uC ACE1101 + ATMEL TSSOP14 memory, choice of 3 protocals i2c : 24C256, SPI : 25C256, DataFlash : AT45D011 and its a reprogrammable solution.. -jg -- ======= Manufacturers of Design Tools for uC and PLD ===== * IceP2051 - Full Speed ICE, for 1K,2K,4K 20 Pin FLASH controllers => http://www.DesignTools.co.nz/winner51.htm for highlightsArticle: 17748
Hello, According to the specs, the new AMD Athlon CPU is ~35% faster than a equiv Pentium at real number work. How does this translate into FPGA / VHDL Simulation performance speeds ? Has anyone tried this CPU on FPGA tools yet ? thanks - jgArticle: 17749
Sorry but I don't read the original, we build this boards, please send me by e-mail your needs Walter. In article <37C7305A.6A9F08FA@zkm.de>, sk@zkm.de wrote: > Ray Andraka wrote: > > > Try Visicom or Coreco (formerly dipix). I think both have boards that might > > meet your needs. > > Thanks, but as far as I can see all their products max out at 40MHz for > capture, whereas we'd need 1280 x 1024 x 24bit x 75Hz = 100MHz..... > > Sukandar > > -- Walter D. Gallegos Software & FPGA Services Montevideo, MVD Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.
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