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This is a periodic posting to let readers of these newsgroups know about several online resources that may be relevant: [1] Embedded Systems Glossary http://www.netrino.com/Publications/Glossary/ [2] Embedded Systems Bibliography http://www.netrino.com/Publications/Bibliography/ These are online versions of the Glossary and Bibliography from my recent O'Reilly book, "Programming Embedded Systems in C and C++" (ISBN 1-56592-354-5). It is my intention to make occasional changes and updates to these online versions. I would very much like to hear your constructive feedback. Please send your suggestions to <webmaster@netrino.com>. I have put a lot of work into writing the book and creating and maintaining these online resources. I hope that they will be a valuable contribution to the community of embedded systems hard- ware and software designers. Sincerely, Michael BarrArticle: 16001
There's this guy who designed a modem for amateur radio with a digital PLL in a Xilinx 5200... Lots of good ideas http://www.microlet.com/yam/yamfeat.htm I've implemented digital lock detectors for analog PLLs that use the fact that the system clock is running faster than the reference clock. This allows you to treat the reference clock as a discrete sampled signal. You can define a window where valid edges are expected (a phase offset range) using the "divide-by-n" counter. Of course where you place the windows depends on the phase detector your using, the 'gains' in the loop, and the signal your locking on to. John John Troch wrote: > Hi all, > > I have to implement a Digital Phase Locked Loop in an FPGA. > The center-frequency is in the order of KHz, but it has to be in lock > over a few KHz. > Does anyone has experience with that ? Or if you have doc's on that > subject, let me know. > > Thanks > > john.troch@barco.comArticle: 16002
Hi, Does someone knows where i could find some information on the differents Virtex die sizes ? (just to compare to current generation DSP or Processor's) Thanks StevenArticle: 16003
Jim Kipps wrote: > Austin- > > FPGA Express from Viewlogic and FPGA Express from Xilinx are essentially > the same, with the exception that the licensing is different and the > Xilinx version > only supports Xilinx devices while Viewlogic supports all vendors. It is > also > possible that the revisions can be different. Viewlogic is at rev 3.1 > and testing > the 3.2 beta. > > -Jim > > Austin Franklin wrote: > > > Anyone know of any differences between the Viewlogic offering of FPGA > > Express and the Xilinx offering of FPGA Express? > > > > Thanks, > > > > Austin Franklin > > austin@darkroom.com > > -- > -------------------------------------------------------- > James R. Kipps FPGA Marketing Manager > jkipps@viewlogic.com Phone: (508) 303-5246 > -------------------------------------------------------- Is there any remote chance that 3.2 might get around to implementing `ifdef ?? And maybe even ``defparam''.Article: 16004
Why not just ask Xilinx. I saw the die for the V1000 at both a Xilinx seminar and at Aptix. I must admit they are huge (a little less than 1" on a side). -Edwin In article <3725CDA8.AE0FCFD1@irisa.fr>, Steven Derrien <sderrien@irisa.fr> wrote: > Hi, > > Does someone knows where i could find some information on the differents > Virtex die sizes ? > (just to compare to current generation DSP or Processor's) > > Thanks > > Steven > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16005
Hi everyone,
I have to store 16 32-Bit-vectors in a Xilinx XCS30XL. These vectors
must be accessible by a address from outside (like a RAM), and on the
other hand I must access them simultanous to compare them with another
vector.
vector 0 \
compare if vector 0 <= vector x<= vector 1
vector 1 /
vector 2 \
compare if vector 2 <= vector x <= vector 3
vector 3 /
: :
vector15
The vectors are limits of memory-ranges. For instance is vector 0 the
lower limit and vector 1 the upper limit of a range.
With the comparison I want find out in wich range is vector x is.
What is the best way to store the Vectors and how can I compare them
fast?
Thanks for your help
Frank
Article: 16006Hi all, i heard about the frequence doubling in the new virtix family. But what I need if not twice the frequnce but nearly 20 times the input clock frequence. I now have a crazy idea: Maybe it is possible to implement a Delayline with normal CLBs and routing. By changing the numbers of CLB a signal is travelling through an feed it back inverted it must be possible to adjust the frequence like with a DCO. Has anybody experience with thing like that please let me know thanks peterArticle: 16007
Hello! I am a beginner in the design of FPGA, and I want to know whether it is possible to create a 9000*1bit Dual-Port Ram on an EPF10K20 in internal (with the EABs).... or must I add an external one??? Thanks for your response, Best regards, Eric Trinh, an humble student. etrinh@ifhamy.insa-lyon.fr etrinh@cri.ens-lyon.fr trinh@rfv.insa-lyon.frArticle: 16008
Hi Frank, Unless you have 8 clock cycles in which you can perform the 8 comparisons, you can't really use the dual port RAM feature of the XCSxx select ram. Because the comparisons must all be done simultaneously, all bits must be visible to the routing, in order to feed them to the comparators. Thus the vectors must be stored in a register. This is not wasteful of space though, because you will most likely be implementing your comparison logic using the fast carry logic. This gives you two bits of comparison/CLB, and the FFs to implement the register are easiest co-located in the same CLB that holds the comparison logic. For details on carry logic, check the xilinx web site. Lots of good application notes there. The comparisons you want to do can be implemented as a subtraction, with the sign bit of the result giving you the A < B information. To write to the registers, either use a common write clock with an address decode/register select routed to CE for the registers, or you can develop an individual write clock for each register. To read the registers, use the internal T-bufs enabled onto horizontal long lines, with the t-buf enable signal decoded from your read strobe and read address. Frank Papendorf wrote: > > Hi everyone, > > I have to store 16 32-Bit-vectors in a Xilinx XCS30XL. These vectors > must be accessible by a address from outside (like a RAM), and on the > other hand I must access them simultanous to compare them with another > vector. > > vector 0 \ > compare if vector 0 <= vector x<= vector 1 > vector 1 / > > vector 2 \ > compare if vector 2 <= vector x <= vector 3 > vector 3 / > : : > vector15 > > The vectors are limits of memory-ranges. For instance is vector 0 the > lower limit and vector 1 the upper limit of a range. > With the comparison I want find out in wich range is vector x is. > > What is the best way to store the Vectors and how can I compare them > fast? > > Thanks for your help > FrankArticle: 16009
The problem is with Synplicity.
Synplify is not counting the BUFGDLL cell as a BUFG resource and inserts
another 4 BUFG or BUFGP cells violating the resource limit of 4 for Virtex.
Alan Chan wrote:
>
> According to the Virtex data sheet, the dedicated clock pins can be used as
> normal inputs, but not I/Os. I have solved the the problem by replacing
> BUFGDLL with IBUFG, CLKDLL and BUFG, and ended up with 4 instances of BUFGs
> only. Before the change, Synplify treated BUFGDLL as a single instance and it
> generated 1 BUFGDLL plus 4 BUFGs. Then, Xilinx Alliance would generate 5
> GCLKs! Leonardo Spectrum doesn't have any problem with that. I was confirmed
> by Xilinx people that there is a bug in Synplify, and will be fixed in the
> new release.
>
> Alan
>
> ems@riverside-machines.com.NOSPAM wrote:
>
> >
> >
> > GCK0/1/2/3 are dedicated pins - you can't use them for normal I/O.
> > Sounds like you've got one on your 50MHz clock, one on the BUFGDLL,
> > and three other ones on the other GCK pins.
> >
> > Evan
--
Paulo //\\\\
| ~ ~ |
( O O )
__________________________________oOOo______( )_____oOOo_______
| . |
| / 7\'7 Paulo Dutra (paulo@xilinx.com) |
| \ \ ` Xilinx hotline@xilinx.com |
| / / 2100 Logic Drive (800) 255-7778 |
| \_\/.\ San Jose, California 95124-3450 USA |
| Oooo |
|________________________________________oooO______( )_________|
( ) ) /
\ ( (_/
\_)
Article: 16010Depends on your memory addressing, clock speed vs memory address rate etc.. As with many other things, if you can make the circuit less general you can reduce the logic required. If, for instance, the memory address is linear, you can load up a down-counter with the difference between the current pointer and the limit. If you truely need access to all 32 bits of all 16 vectors simultaneously (well, on the same clock cycle anyway), then you won't be able to use the RAM for the storage, as you can only get at best two values simultaneously out of each RAM (and that 'wastes' the other half of the CLB). You'll also need 16 32 bit comparators. Assuming you need to do all the compares on the same clock cycle, I'd opt for a partitioned look-up compare approach. For each group of 4 bits in the memory address, you generate a 16 x 2n look up table (n is the number of compares) containing all of the compares for that 4 bit slice. In your case, it sounds like you are looking for an in-range/out-of-range indication for each pair of limits, so the upper and lower limit compares within each slice can also be combined so that the slice outputs are two of "in-range", "above range", and "below range". The outputs of each slice are then combined in separate compare trees for each limit pair. You are storing the compare results for each input address rather than the compare values, so you will need to do some pre-computation to get the LUT values. The reward for the extra effort comes in the form of a smaller and faster circuit, and less storage locations to deal with. Frank Papendorf wrote: > Hi everyone, > > I have to store 16 32-Bit-vectors in a Xilinx XCS30XL. These vectors > must be accessible by a address from outside (like a RAM), and on the > other hand I must access them simultanous to compare them with another > vector. > > vector 0 \ > compare if vector 0 <= vector x<= vector 1 > vector 1 / > > vector 2 \ > compare if vector 2 <= vector x <= vector 3 > vector 3 / > : : > vector15 > > The vectors are limits of memory-ranges. For instance is vector 0 the > lower limit and vector 1 the upper limit of a range. > With the comparison I want find out in wich range is vector x is. > > What is the best way to store the Vectors and how can I compare them > fast? > > Thanks for your help > Frank -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16011
I am looking for information on implementing MII/RMII and UTOPIA/UTOPIA2 interfaces in FPGAs. Any information regarding design ideas, application notes, or cores that can be purchased would be greatly appreciated. Thanks, RogerArticle: 16012
This is a multi-part message in MIME format. ------=_NextPart_000_0022_01BE9186.165D21C0 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: quoted-printable Hello ! My name is Willy_Tsai. I am develope a project. It need Z80 and Z80-CTC and Z80-PIO. Who can give me a hint ? Thanks in advance. Any leads greatly appreciated. Email: Willy_Tsai@163.net=20 Web: http://www.cgw.163.net , ------=_NextPart_000_0022_01BE9186.165D21C0 Content-Type: text/html; charset="big5" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN"> <HTML> <HEAD> <META content=3Dtext/html;charset=3Dbig5 http-equiv=3DContent-Type> <META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT color=3D#000000 size=3D2>Hello !</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>My name is Willy_Tsai.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>I am develope a project.<BR>It need = Z80 and=20 Z80-CTC and Z80-PIO.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Who can give me a hint = ?</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Thanks in advance.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Any leads greatly = appreciated.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Email: <A=20 href=3D"mailto:Willy_Tsai@163.net">Willy_Tsai@163.net</A> <BR> = Web: <A=20 href=3D"http://www.cgw.163.net">http://www.cgw.163.net</A> &nb= sp; =20 ,</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 = size=3D2><BR></FONT> </DIV></BODY></HTML> ------=_NextPart_000_0022_01BE9186.165D21C0--Article: 16013
Hi theoretically it is possible to make this, however I would not recommend it with this type, unless you have prepared for using a larger device or switch to the EPF10K30E for example. Why theoretically? Altera says using Ram-Blocks of more than 2048 words has an impact on timing. Also you have to consider that the FPGA needs an overhead to create the access logic - and - the EPF10K20 does not have true dual port RAM. Therefore I recommend you using the EPF10KxxE-Family. Or, as pointed out, using a footprint and flexible splited voltage supply where you could replace your 10K20 with a 10K30E or even 10K50E... Regards Matthias vertige69@hotmail.com schrieb: > Hello! > > I am a beginner in the design of FPGA, and I want to know whether it is > possible to create a 9000*1bit Dual-Port Ram on an EPF10K20 in internal > (with the EABs).... or must I add an external one??? > > Thanks for your response, > Best regards, > Eric Trinh, an humble student. > etrinh@ifhamy.insa-lyon.fr > etrinh@cri.ens-lyon.fr > trinh@rfv.insa-lyon.frArticle: 16014
Peter Lang wrote: > Hi all, > i heard about the frequence doubling in the new virtix family. > But what I need if not twice the frequnce but nearly 20 times the input > clock frequence. > I now have a crazy idea: > Maybe it is possible to implement a Delayline with normal > CLBs and routing. By changing the numbers of CLB a signal is > travelling through an feed it back inverted it must be possible > to adjust the frequence like with a DCO. > Temperature depending? > > Has anybody experience with thing like that > please let me know > thanks peter Hello You have 4 DLLs inside a virtex, so you can have your input frequency x2 x2 x2 x2 = 16. If it is enough, you can see the XAPP132 (xilinx web site). Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16015
... or you could use a DynaChip DY6000 FPGA (www.dyna.com) which has 2 analog PLLs, each of which allows you to multiply your clock frequency by up to x8. Martin Duffy Ambar Components (UK) Le mer Michel wrote in message <3726BD1D.519D18DF@ago.fr>... >Peter Lang wrote: > >> Hi all, >> i heard about the frequence doubling in the new virtix family. >> But what I need if not twice the frequnce but nearly 20 times the input >> clock frequence. >> I now have a crazy idea: >> Maybe it is possible to implement a Delayline with normal >> CLBs and routing. By changing the numbers of CLB a signal is >> travelling through an feed it back inverted it must be possible >> to adjust the frequence like with a DCO. >> > >Temperature depending? > >> >> Has anybody experience with thing like that >> please let me know >> thanks peter > >Hello > >You have 4 DLLs inside a virtex, so you can have your input frequency x2 >x2 x2 x2 = 16. >If it is enough, you can see the XAPP132 (xilinx web site). > > >Hope this helps, > >Michel Le Mer >Gerpi sa (Xilinx Xpert) >3, rue du Bosphore >Alma city >35000 Rennes (France) >(02 99 51 17 18) >http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi .htm >Article: 16016
hi
I have BIG problems.
I can't config FPGA XC4085XLA , Have Error about Init pin and Done pin.
Now it shows " Device can't config , Done is not high"
I check init pin but have "low signal" /
What's wrong with My FPGA.???
Now i try to download FPGA from EPROM.
REgard
Please suggest me at
ksuwanna@kmitl.ac.th
ICQ - 7874501
Immediately!!!!
Article: 16017Affordable and reliable IrDA infrared communications for 8/16/32/64 bit CPU's IrPro(Tm) is An IrDA compliant software protocol stack that supports reliable infrared communications for portable devices. For more information check out: http://www.embednet.com Our customers have successfully used our stack on popular 8 bit CPU's like: 8051 derivatives and PIC. We also support Atmel's AVR CPU's. This software stack is: . modular and written in "clean" C. . small (<11K bytes) . efficient ( Zero copy buffer management ) . able to support speeds from 9.6Kbps to 4Mbps . able interface to any commercial RTOS or a custom OS . has direct support for popular CPU's or is simple to port to your custom CPU. . robust and mature. . reliable, and provides inexpensive data transfers . supported on all popular platforms: MIPS, ARM, Motorola, Intel, Hitachi SH, etc ... . affordable (<$8k, no royalties, all source code) Advantages of using IrDA infrared: . requires no connectors . is low power and low cost. . infrared is not regulated like RF and requires no certification . data transfers are reliable and robust . IrDA is supported by MS Windows operating systems.Article: 16018
Frank Papendorf <Frank.Papendorf@fh-stralsund.de> wrote: > I have to store 16 32-Bit-vectors in a Xilinx XCS30XL. These vectors > must be accessible by a address from outside (like a RAM), and on the > other hand I must access them simultanous to compare them with another > vector. From your description, it looks like you need to store your vectors in CLB flip-flops. Some things that might be possible: If the vectors are static (don't need to be written except at configuration time) then you could possibly share some logic, and certainly don't need to store them in flip-flops. In an ideal world, you could pop your vectors into a VHDL synthesizer and get an optimized circuit. In either case, it makes sense to shadow the vectors in a RAM block so that you can read them from your external port without having to access the CLB flip-flops. This eliminates a lot of decode logic and tristate drivers. You still have to implement a write path, though. Altera's latest chip (Apex) has memory block that has a Content Addressable Memory mode. When I asked if it could do arithmetic comparisons, they said it could, however based on their very minimal documentation, I'm guessing they misunderstood my question. If it can do arithmetic comparisons, then it would be ideal for your application.Article: 16019
I use three books each with it's own merits. I have the Douglas Smith book also and it is very good if you are looking for snipets of code to use or base your designs on. Ashenden's book, The designer's guide to vhdl, is also very good. It explains how everything works in the vhdl world and give numerous examples. If you are learning vhdl, the book that cypress puts out, " Vhdl for Programmable logic" is a very good book to start with. It does not deal with alot of the more in depth things that vhdl is capable of but, it gives you a good working foundation. Bill In article <kqbT2.2445$%L2.85908@news6.ispnews.com>, "Bruce Nepple" <brucen@imagenation.extra.com> wrote: > HDL Chip Design by Douglas Smith > > Side by side VHDL and Verilog examples of synthesizable code for things > people want to synthesize. No PLI. > > bruce > edwinpark@my-dejanews.com wrote in message > <7fbk3d$8ga$1@nnrp1.dejanews.com>... > >There seems to be a lot of people asking about learning about FPGAs. I > want > >to start a discussion about good books. In the short term, I personally > have > >a need for a good book describing Verilog (I did VHDL in the past) and PLI. > > > >Any other related categories are welcome. > >- VHDL > >- FPGA programming > >etc. > > > >-Edwin > > > >-----------== Posted via Deja News, The Discussion Network ==---------- > >http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16020
In article <3726BD1D.519D18DF@ago.fr>, Le mer Michel <michel.lemer@ago.fr> wrote: > >You have 4 DLLs inside a virtex, so you can have your input frequency x2 >x2 x2 x2 = 16. >If it is enough, you can see the XAPP132 (xilinx web site). > It is not possible to multiply the clock frequency by more than 4X within Virtex using two internal CLKDLLs. Creating a 8X or 16X would violate either the minimum or maximum clock input frequency for the CLKDLL. EdArticle: 16021
Help! I am looking for some help from someone who has made the transitions from XACT 5.2 to 6.0 to Foundation. I have been trying unsuccessfully to produce a working binary file for a XC4008 (no extensions!) chip using the Foundation 1.3 (Metamor) front end and XACT 6.0.2 routing under Win95. Background: I am working on a network card for a Sparc machine which uses a Xilinx XC3042 as an SBus interface and an XC4008 as a communications controller. The card is set up so the XC4008 can be programmed while installed in the machine through the XC3042. The initial design was done by someone else in SCHEMA and XACT 5.2 under DOS a few years ago. It has a few registers in it and performs some functions the details of which I won't bore you with. My job is to set up the communication interface, and then add DMA control. I have the binary file which was produced and used to test the XC4008 and it is working fine but now I need to make some changes and, of course, I do not have what I need to use the SCHEMA/XACT 5.2 path. Plus I am trying to use VHDL so the next person who inherits this can pick up where I left off. No matter what I do it seems the files I produce using the Foundation/XACT 6 path either lock up the machine or give garbage when I try to read a register. Since the same file sometimes does both this seems to me to say it's the file that's being produced that I need to check out, so I am wondering if anyone knows of any changes going from 5.2 - 6 that might cause the problem I am having. Any help is greatly appreciated, Tyrone -- -------------- thompson@eecis.udel.edu University of Delaware Tyrone Thompson EE Graduate StudentArticle: 16022
Hello, in order to conduct several experiments for my degree dissertation I am searching for representative information concerning applications of FPGAs in practice. These information can be summarized as follows: 1) Frequency distribution of the dimensions of FPGA tasks, i.e. what is the probability that a task has a size (w,h)? Here w and h are the width and height of a task (number of CLBs). 2) Frequency distribution of input data rates of tasks, i.e. what is the probability that an input data stream of a task provides data with a rate of x bits per second? 3) Frequency distribution of service times of tasks, i.e. what is the probability that an allocated task runs t seconds? 4) Frequency distribution of the inter task arrival time, i.e. supposed that tasks have to enter a queue (FCFS) before being allocated, what is the probability that the difference in the arrival time of two consecutively arriving tasks amounts to p seconds? 5) Configuration delay of tasks, i.e. how many seconds takes the configuration of a CLB in seconds? Do you have a clue, where I could get such data? In your experience, what is your personal estimation of the information requested above? Please send your answer to: e-mail: bes@aifb.uni-karlsruhe.de or news group: comp.arch.fpga Thanks for your support! Cheers Bernd -- | Bernd Schmidt | e-mail: bes@aifb.uni-karlsruhe.deArticle: 16023
SURVEY: The experiments I conduct within my degree dissertation will include the data, obtained by the evaluation of the following survey. I should be very grateful, if you would take part in this survey. Your response will represent a scientific contribution. May I ask you to send data of examples of FPGA applications? Each example should include the following data as complete as possible: 1) The dimensions (width and height in number of CLBs) of all tasks within the FPGA application. 2) The input data rate of each task in bits per second. 3) The service time of each task in seconds. 4) Time between the placement of two tasks in seconds. 5) Configuration delay per CLB in seconds. Please send your answer to: e-mail: bes@aifb.uni-karlsruhe.de or news group: comp.arch.fpga Each participant will obtain the results of this survey upon request! Thanks for your support! Cheers Bernd -- | Bernd Schmidt | e-mail: bes@aifb.uni-karlsruhe.deArticle: 16024
On Tue, 27 Apr 1999 00:52:42 GMT, Bob Sefton <rsefton@home.com> wrote: <snip> > I agree that it takes a lot >of work to completely spec some designs, but you have to do that >anyway. If a timing sim reveals a broken path the only way to fix >it is to constrain the path correctly. agreed. i'm not meaning to imply that a timing sim is better than a static analysis, or can replace it; only that, if you have a complicated (or any) set of constraints, then the only way to check them is with a timing sim. evan
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