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Duane <junkmail@junkmail.com> writes:
> Petter Gustad wrote:
> >
> > Hi,
> >
> > I've been working with ASIC design under Unix for the past 10 years
> > and I'm happy to see that I can run a lot of my EDA SW under Linux on
> > cheap PC's.
> >
> > Lately I've been working with Alliance under Solaris and was wondering
> > if Xilinx have any plans to release their software under Linux?
> >
> > Petter
>
> There are a number of us running the Xilinx implementation tools under
> Wine in Linux. I have found that all the command line programs work
[...snip...]
I'm aware of emulators like wine and vmware, but I has hoping that a
native version was under its way. I would like to continue to use the
simulation infrastructure that I have been using during the past years
(cvs, slogin from home, tclsh, sh scripts, etc...).
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 26951On Fri, 03 Nov 2000 18:48:40 +0000, Simon Gornall <simon@unique-id.com> wrote: >> eml writes: >> > Exactly. And how many of us actually care about whether or not we have >> > source code? As far as I'm concerned, it's just wasting valuable disk >> > space. >Besides, the original poster was uninformed. The majority of Linux >programs are available as binaries - in nice easily-installed packages >called .deb or .rpm (etc.) They'll even check for dependencies and run >configuration scripts to make sure the program is properly installed. > >The remaining point is that if (s)he don't like it, don't use it - just >don't bitch about it. There's no obligation on the part of open-source >programmers to solve his(her?) problem with the open-source credo. > >To be honest it sounds like the poster would be better off staying in >the nice safe Windows environment, it sounds like the trade-offs >there are more to the poster's tastes than those under Linux. > >[You can probably tell I have little sympathy for people who moan without >cause having done no gainful research into what they're moaning about] > >Simon. Nice to get your point of view, Simon. However, it's not a good idea to make wide-ranging assumptions based on a few lines of text. I started on Unix V7 (?) over 15 years ago, I've written my own mini SVR4 kernel, which I sold successfully for several years, I've done drivers for SunOS4 and a Linux-a-like, and I've been waiting over 10 years for a Windows replacement. However, The last Linux program I installed aborted during make with two out-of-memory failures, which required manual intervention. The Debian install I referred to incorrectly calculated my dependencies which made it impossible to install X. The Sysadmin who managed to install X for me, and who has far more experience than me, still couldn't manage to get me on a network. Anyone who thinks that Linux is ready for primetime, by which I mean use outside of software or hardware development is, in my opinion, on another planet. EvanArticle: 26952
http://www.ikn.com/solutions/kits/xilinx/spartan-ii.htmlArticle: 26953
Simon Gornall wrote: > Hi all, > > Being more of a software than hardware guy, I don't appear to be able to > find vendors of any prototyping boards for Spartan2's. Are you all really > that gung-ho that you just get your hands dirty and build a board :-) > Or am I missing all the adverts due to years of auto-filtering ads on > Usenet ? > > The Spartan2 looks ideal for what we need to do, but I'd rather take out > some of the initial design uncertainty by buying a prototype board that > I know works - offers on (an e- :-) postcard please ... > > Cheers, > Simon. > > -- > Physicists get hadrons! As you might have seen on this ng getting hold of Spartan2's requires a Ph. D. in disti shmoozing or maybe a well planned commando raid on the fab [finance for such an operation would not be a problem]. Probably easier to buy some of these boards, strip the chips off & throw the boards away.Article: 26954
Petter Gustad <spam@gustad.com> writes: > I'm aware of emulators like wine and vmware, but I has hoping that a > native version was under its way. I would like to continue to use the > simulation infrastructure that I have been using during the past years > (cvs, slogin from home, tclsh, sh scripts, etc...). I asked a Xilinx employee, and was told that they have no plans for Linux-hosted tools because there's no demand for them. I think those guys are living in a cave, probably on the lunar farside.Article: 26955
Martin,
Besides the pinout differences mentioned by the other posters, the ACEX
family implements dual-port RAM (DPRAM) in their EABs. This is a big plus,
because the FLEX family lacked this feature, and it cost Altera BIG TIME!
In fact, I think that this one feature was responsible for several (many?)
design wins for Xilinx, since DPRAMs are used in many designs requiring
either raw DPRAMs or FIFOs.
I know in my design history, I was able to swallow up little DPRAMs and
FIFOs that were used to solve synchronous boundary problems in Xilinx 4K and
Virtex parts. I guess that Altera finally figured out that designers do
really want DPRAMs after all.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message
news:3a02ce1a.2445236103@news.trw.com...
> Can anyone tell me what the difference between the ACEX and FLEX
> families of Altera devices is? As far as I can tell, the only
> difference is the number of packages supported...
>
> Anyone from Altera lurking here?
>
> Thanks,
> Martin
>
> --
> Martin Thompson
> martin.j.thompson@trw.com
>
Article: 26956Hi Simon, ... > Besides the pinout differences mentioned by the other posters, the ACEX > family implements dual-port RAM (DPRAM) in their EABs. ... I recently tried to use this feature for a Memory mapped interface between a Microcontroller and my FPGA, but I struggled because of the lack of time. A collegue programmed a solution with a simple register based version indeed covers many resources. I think I have to take the time to programm the Dual-Port RAM feature. I think this should be done by using the LPM lpm_ram_dp, shouldn't it? CU, CarlhermannArticle: 26957
Andy Peters wrote: > > Ray Andraka wrote: > > > > Yep, but the thing is it doesn't pay much attention to partitioning the > > replication, so as a result you can wind up with pieces that you want to share a > > slice using different clock enables. This has come up as a problem a number of > > times on logic with carry chains, and is the main reason the carry chains get > > messy. > > Amplify might fix that to some degree, I don't know fer sure tho. It can also > > be fixed using local copies of the CE with syn_keep buffers added to keep it > > from breaking up stuff that should have a common replicated ce. > > Ah, I see. I was just using the fan-out to replicate things like output > enables and such. It still be the hell out of putting the duplicate > registers in the code, and having to convince the tool NOT to optimize > the duplicates away! How exactly could the tools know to optimize the duplicate register away? Even if it uses the same input signal and the same logic to the register, the output nets are different. I don't think the tools are smart enough to know that the duplicate registers could be removed. Have you seen this happen? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26958
Eric Smith wrote: > > Petter Gustad <spam@gustad.com> writes: > > I'm aware of emulators like wine and vmware, but I has hoping that a > > native version was under its way. I would like to continue to use the > > simulation infrastructure that I have been using during the past years > > (cvs, slogin from home, tclsh, sh scripts, etc...). > > I asked a Xilinx employee, and was told that they have no plans for > Linux-hosted tools because there's no demand for them. I think those > guys are living in a cave, probably on the lunar farside. Perhaps they measure demand by sales. If they don't sell a Linux version of their tools, then there is no measurable demand? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26959
Petter Gustad wrote:
>
> Duane <junkmail@junkmail.com> writes:
>
> > Petter Gustad wrote:
> > >
> > > Hi,
> > >
> > > I've been working with ASIC design under Unix for the past 10 years
> > > and I'm happy to see that I can run a lot of my EDA SW under Linux on
> > > cheap PC's.
> > >
> > > Lately I've been working with Alliance under Solaris and was wondering
> > > if Xilinx have any plans to release their software under Linux?
> > >
> > > Petter
> >
> > There are a number of us running the Xilinx implementation tools under
> > Wine in Linux. I have found that all the command line programs work
>
> [...snip...]
>
> I'm aware of emulators like wine and vmware, but I has hoping that a
> native version was under its way. I would like to continue to use the
> simulation infrastructure that I have been using during the past years
> (cvs, slogin from home, tclsh, sh scripts, etc...).
I think that is one of the great things about running the tools under
wine. Without knowing the details of your scripts and infrastructure, it
is very possible that they could work without changes under wine. It
sounds to me like you are bypassing the fancy Xilinx frontend programs
like design manager and flow engine. And you get "native" performance,
because the vast majority of the time, the Xilinx tools are executing
X86 code directly, with no interaction with wine (which is why wine
people prefer not to call it an emulator).
And all this should work fine with CVS as you are using it. And it
definitely runs fine with slogin, since everything here is plain text -
there are no windows involved.
For example, let me give you a very quick glance at what I do. The first
step was to set things up so that I could execute all the programs as if
they really were native Linux. This is so that when the manual indicates
to run "ngdbuild -p xcv300e-6-bg432 -sd ../.. design.ngo", I type that
in exactly, and it works. But even more important to a homogenous
environment, it works in scripts, including returning the same result
codes as the native applications.
To do this, in /usr/local/bin, I created an executable file called
ngdbuild that is a wrapper for ngdbuild under wine, and that looks like
this:
#!/bin/csh -f
# echo xwine --debugmsg fixme-all -- $XILINX/bin/nt/$0:t.exe $*
exec wine --debugmsg fixme-all -- $XILINX/bin/nt/$0:t.exe $*
Then in the same directory I created a bunch of hard links to it:
# ln ngdbuild xnf2ngd
# ln ngdbuild edif2ngd
# ln ngdbuild map
# ln ngdbuild par
...etc. Somewhat tedious, but doesn't really take that long. The result
of that is that all the Xilinx implementation commands now work. So I
type "ngdbuild -p xcv300e-6-bg432 -sd ../.. design.ngo", and it runs
just as if I were on a Sun system (which is where I had previously run
the Xilinx tools).
Then I have a fairly simple script that look like:
----------------------------------------------------------------
#!/bin/tcsh
# setiathome takes too much resources
seti stop
mkdirhier $XREV
foreach i (`ls *.xnf`)
if ( ! { xnf2ngd $i $XREV/$i:r.ngo } ) then
echo "ERROR in xnf2ngd."
exit
endif
end
if ( -f $XTOP.ucf ) then
cp -p $XTOP.ucf $XREV
endif
cd $XREV
if ( $?XNGD ) then
if ( ! { ngdbuild -p $XPART $XNGD $XTOP.ngo } ) then
echo "ERROR in ngdbuild."
exit
endif
endif
# Report file is $XTOP.bld
----------------------------------------------------------------
...etc. You probably get the idea. That is a global script, which I
control from another file in each project directory:
----------------------------------------------------------------
#!/bin/tcsh
# These environment variables should be all that are needed
# to control the script make_xilinx
# XREV controls the directory the project will be compiled
# into - relative to the current directory. The directory is
# created if it does not exist. If an argument is supplied
# to this script, it will be used as a subdirectory name.
if ( { test $1 } ) then
setenv XREV xproj/$1
else
setenv XREV xproj/rev1
endif
# XTOP is the top level design name (without a . extension).
setenv XTOP design
# XPART is the part number of the device to be used.
setenv XPART xcv300e-6-bg432
# XNGD contains -sd options to be passed to ngdbuild.
# The ngdbuild line should have -sd options for all
# directories containing source .xnf files. ngdbuild will use
# this to verify that the .ngo file is newer then the
# corresponding .xnf files.
# For example, "-sd ../.." is a reference to the directory
# containing XTOP, because ngdbuild is being run from XREV,
# which is (if XREV is xproj/rev1) 2 subdirectories below
# XTOP. Separate -sd options are needed if there are
# additional directories: "-sd ../.. -sd ../../vhdl/synth"
setenv XNGD "-sd ../.."
# Comment out any of the following lines to skip that step.
# Otherwise, set command line arguments here.
setenv XMAP ""
setenv XPAR "-l 5 -w"
# setenv XTRCE "-v 10 -u"
# setenv XBITGEN "-w"
# setenv XPROMGEN "-p mcs -s 1024 -u 0"
# setenv XNGDANNO ""
# setenv XNGD2VHDL "-w"
# execute the global script
/usr/local/bin/make_xilinx
----------------------------------------------------------------
The one extra caveat that I would throw in is that wine uses (in the
background where you don't see it) a "wineserver". When you first start
up a wine program, the server is also started and can take a significant
amount of time to do that. Any additional wine programs use the existing
wineserver and so start up much faster. When the last wine program
exits, the server also exits.
So with the script above, if there is no wine program already running,
the server will be started and stopped many times, causing a serious
performance drop. The simple solution that I use is to run some wine
program that just sits in the background and doesn't do anything, except
to keep the server up.
--
My real email is akamail.com@dclark (or something like that).
Article: 26960In article <sv4N5.6530$vc3.822699@typhoon.tampabay.rr.com>, sramirez@deleet.cfl.rr.com (S. Ramirez) wrote: > Martin, > Besides the pinout differences mentioned by the other posters, the > ACEX > family implements dual-port RAM (DPRAM) in their EABs. This is a big > plus, > because the FLEX family lacked this feature, and it cost Altera BIG > TIME! So does the 10KE family, which is much closer to the 1K in features. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 26961
Carlhermann,
In the design below, I inferred DPRAM with Synplify. You can
immediately register the read side or use it directly as I did. This
implementation uses the SelectRAM feature in Xilinx 4K and Virtex (e), which
converts two CLB LUTs to 16x1 DPRAM.
I'm not 100% sure how you would do it in an Altera design, though.
Please check with someone else here or with your friendly Altera FAE, if you
can find him!
-Simon Ramirez, Consultant
Synchronous Design, Inc.
//**************************************************************************
***
// Infer 64x48 dual port RAM for bidirectional FIFO. -SNR
10/26/99
//
//**************************************************************************
***
// FIFO memory declaration
reg [31:0] fifo_dpram [63:0]; //Note: depth = 64
reg [5:0] bibuf_rd_addr;
reg [5:0] bibuf_wr_addr;
wire bibuf_wen;
//implement synchronous write side
always @(posedge I_clk)
begin
if (bibuf_wen)
begin
fifo_dpram[bibuf_wr_addr] <= bibuf_din;
end
end
//output data asynchronously from memory using read address
assign O_bibuf_dout = fifo_dpram[bibuf_rd_addr];
****************************************************************************
*****
"Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de> wrote in message
news:8u3av7$s31$05$1@news.t-online.com...
> Hi Simon,
>
> ...
> > Besides the pinout differences mentioned by the other posters, the
> ACEX
> > family implements dual-port RAM (DPRAM) in their EABs.
> ...
>
> I recently tried to use this feature for a Memory mapped
> interface between a Microcontroller and my FPGA, but I
> struggled because of the lack of time. A collegue
> programmed a solution with a simple register based
> version indeed covers many resources.
> I think I have to take the time to programm the Dual-Port
> RAM feature. I think this should be done by using the
> LPM lpm_ram_dp, shouldn't it?
>
> CU, Carlhermann
Article: 26962"Berni Joss" <berni_13@yahoo.com> wrote in message news:8u208c$6ej$1@news1.urbanet.ch... > http://www.ikn.com/solutions/kits/xilinx/spartan-ii.html Excellent. Thanks :-)Article: 26963
I spoke to a distributor who has them last thursday. email me at crawfora@dscltd.com and I will give you his #. try www.avnet.com "Simon Gornall" <simon@unique-id.com> wrote in message news:3A03CE25.8E495429@unique-id.com... > Hi all, > > Being more of a software than hardware guy, I don't appear to be able to > find vendors of any prototyping boards for Spartan2's. Are you all really > that gung-ho that you just get your hands dirty and build a board :-) > Or am I missing all the adverts due to years of auto-filtering ads on > Usenet ? > > The Spartan2 looks ideal for what we need to do, but I'd rather take out > some of the initial design uncertainty by buying a prototype board that > I know works - offers on (an e- :-) postcard please ... > > Cheers, > Simon. > > -- > Physicists get hadrons!Article: 26964
What is the proper way to do these things in ViewLogic's ViewDraw?
o Merge multiple buses. Eg, say that I have A[31:0] and B[31:0].
I'd like to form C[31:0] from A[31:16] concatenated with B[15:0].
Is there an elegant way of doing this without making a VHDL block?
o Set a bus to a constant value. Say I want F[31:0] to be set to
the constant value 0xDEADBEEF. How is this done in the schematic
editor without resorting to a VHDL block?
Thanks,
Tobin
Article: 26965I do both these manipulations in viewdraw. No good way ! pass a[31:00] thru a BUFT16 and out put C[31:15] similar with b. or pass Ann thru BUF out as Cnn. repeat 15 times. similar for b. Use logiblox or coregen to set a constant. DanArticle: 26966
Ray Andraka <ray@andraka.com> writes: > And it is an absolute nightmare for source control, particularly when the work > goes to a third party as it does for most consulting. Also creates problems if > you have multiple projects with different tweaks in the source code. No > thanks. I'd rather work around the bug and have everyone working with the same > set of tools than open this can of worms. In an open source environment the situation is much less gloomy than you paint. The nightmare that you paint does not seem to affect tens of thousands of individuals and corporates who use open source tools. Even though most of them are software people and as seasoned readers of this NG should know by now, they are ab ovo inferior cretins, they seem to achieve some results which might be worthy of notification. If you always contribute the bugfixes and improvements back to the community then all changes get merged in and the incompatibity will not cause nightmares. Instead of having incompatible versions, you end up with incremental improvements. Also, as long as the tool is free (as in speech) and is under some public source control facility, you (or your client) can re-create any given version of the tool, if your solution actually depends on the existence of some bug. Existing commercial tools are not compatible to each other even today and as the content of this NG indicates, even different versions of the same tool seem to behave quite differently. The GNU tools, however, were (and are) popular not just because they are free but because if you had a project that was based on gmake and gcc and other g-tools, then the same project tree produced binaries that behaved identically on Sun or HP or whatever else you had hanging around. This was very much not the case with the tools you got with the systems, they were vastly incompatible. In addition, while you personally might find the thought of having access to the source nightmarish, others, who use some other business model to design chips might still find the idea of being able to fix bugs or even improving the tool appealing. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 26967
Try Insight, they sell some nice Spartan2 boards. H. "Simon Gornall" <simon@unique-id.com> wrote in message news:3A03CE25.8E495429@unique-id.com... > Hi all, > > Being more of a software than hardware guy, I don't appear to be able to > find vendors of any prototyping boards for Spartan2's. Are you all really > that gung-ho that you just get your hands dirty and build a board :-) > Or am I missing all the adverts due to years of auto-filtering ads on > Usenet ? > > The Spartan2 looks ideal for what we need to do, but I'd rather take out > some of the initial design uncertainty by buying a prototype board that > I know works - offers on (an e- :-) postcard please ... > > Cheers, > Simon. > > -- > Physicists get hadrons! >Article: 26968
Nallatech have a new "ENTRY LEVEL SPARTAN-2 BASED PCI CARD WITH DIME". The DIME module allow you to connect additional hardware (DSP / A2D / LVDS / etc ) to your FPGA. http://www.nallatech.com/products/dime_select/strathnuey/index.htm I hope it helps, ----------------------------------------------------------------------- Rotem Gazit *** MystiCom Ltd. *** System & Architecture rotem @ mysticom.com http://www.mysticom.com ----------------------------------------------------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26969
Yes. Synplify does. I think it is probably part of the resource sharing algorithm. rickman wrote: > > Andy Peters wrote: > > > > Ray Andraka wrote: > > > > > > Yep, but the thing is it doesn't pay much attention to partitioning the > > > replication, so as a result you can wind up with pieces that you want to share a > > > slice using different clock enables. This has come up as a problem a number of > > > times on logic with carry chains, and is the main reason the carry chains get > > > messy. > > > Amplify might fix that to some degree, I don't know fer sure tho. It can also > > > be fixed using local copies of the CE with syn_keep buffers added to keep it > > > from breaking up stuff that should have a common replicated ce. > > > > Ah, I see. I was just using the fan-out to replicate things like output > > enables and such. It still be the hell out of putting the duplicate > > registers in the code, and having to convince the tool NOT to optimize > > the duplicates away! > > How exactly could the tools know to optimize the duplicate register > away? Even if it uses the same input signal and the same logic to the > register, the output nets are different. I don't think the tools are > smart enough to know that the duplicate registers could be removed. Have > you seen this happen? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26970
Hello, I'm student and I'm interested in encoding of internal states in FSMs (finite state machine) in relation to realization these FSMs to Xilinx FPGA. I try to use different encoding of internal states (binary, gray, johnson, onehot, twohots, fanin ... etc) and I woud like to find out some relations between encoding and number of used CLBs, etc.. So, could you send me some tips to literature or www links (about this)? Thanks, MICHAL (michal.prokes@asicentrum.cz)Article: 26971
Hello FPGA users, I am trying my best to intelligently lock at least some of the pins in a design using a Spartan XL, in this case it is the XCS20XL-4TQ144. The compiler does not produce an attractive design, in that the buses are ordered in a seemingly random fashion. Also, it does not appear to produce an optimum placement from the standpoint of routing, even though it probably meets the requirements of the design. The pins that I seek to lock are for several 16 bit buses. The design contains a 16b bidirection data bus D[15:0], a buffered version of it that is enabled for certain operations BD[15:0], an input bus from an ADC that can drive onto the data bus ADC[15:0], and an output bus that can latch data from the data bus L[15:0]. My first thought is to place D[] and BD[] at opposite ends of horizontal longlines. Then intersperse ADC[] with D[] on one side, and L[] with BD[] on the opposite side. Alternatively one could put intersperse ADC[] and L[], and place them at the top and bottom of the chip to take advantage of splitting the vertical longlines. (Say ADC[7:0]/L[7:0] at the top and ADC[15:8]/L[15:8] at the bottom.) But I am quickly getting beyond my understanding of the device and the subtleties of routing. Can someone offer a suggestion on this specific layout ? Or perhaps better for all, give us a pointer to some general information on human-assisted pin locking ? Any suggestions or discussion on the subject will be much appreciated ! -- George PontisArticle: 26972
Hello, I'm not familiar with jtag algorithms. What is the exact purpose of the Boundary Scan register of the serial eeprom XC18V00 => what is the purpose of the data written in this register in the Shift-DR state? What is the exact difference between the EXTEST and the SAMPLE/PRELOAD instructions? Thank you Alexandre Boyer Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26973
George Pontis ha scritto nel messaggio ... :Hello FPGA users, : :I am trying my best to intelligently lock at least some of the pins in a :design using a Spartan XL, in this case it is the XCS20XL-4TQ144. The :compiler does not produce an attractive design, in that the buses are :ordered in a seemingly random fashion. Also, it does not appear to :produce an optimum placement from the standpoint of routing, even though :it probably meets the requirements of the design. : : I use XCS20XL TQ144, too. I experienced your current problem once: if you doesn't lock bus pins, the router produces quite messy results. Then, I usually design my PCB layout before the FPGA and always lock ALL of the device pins. I've never had any routing problem since Spartan devices have a large amount of routing resources. The router was always able to accomplish the task also when the FPGA was almost full (>90% CLB used), without the need of using the maximum PAR effort. I've had routing problems only with XC5200s, but this seems rather be a bug of Foundation series software, since the old XACT router could manage the same project without effort.Article: 26974
Bonjour Alexandre,
alexboyer@my-deja.com wrote:
> I'm not familiar with jtag algorithms. What is the exact purpose of the
> Boundary Scan register of the serial eeprom XC18V00 => what is the
> purpose of the data written in this register in the Shift-DR state?
The Boundary-Scan Register (BSR) is one of the test registers that can
be
serially loaded and read by JTAG (there are a few ones). The BSR is
special
since it can sense the values applied to the I/O pads of the device (in
your case, the XC18v00 PROM); if needed, the BSR can also drive values
for
test purposes.
I took a look at one of the programming algorithms of the XC18V00 and I
haven't seen any place where the BSR is written/read. In any cases,
writing
to the BSR (specifically) is usually an operation done for testing
purposes
and/or to ensure safe values are applied to the board when programming
the
chip.
> What is the exact difference between the EXTEST and the SAMPLE/PRELOAD
> instructions?
Both instructions give the ability to read/write from/to the BSR. In the
case of SAMPLE/PRELOAD, the device continues to operate normally (the
output pads get their value from the core logic). With EXTEST, however,
the
chip is placed in its test mode and the outputs are driven with the
values
from the BSR.
In addition, in the case of the XC18V00 PROM, the inputs to the core
logic will also be driven with the values coming from the BSR when the
EXTEST instruction bacomes active. Such functionality is usually seen in
another standard JTAG instruction named INTEST, but Xilinx folks
integrated this optional feature in EXTEST.
Regards,
Étienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
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