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I'm referring to cases where I've had a fan-out on CE that is very large (several hundred or more). You can break that into multiple parallel CE signals, all doing the same thing to decrease the time due to fan-out. In order to get significantly better than the low skew network, you need to reduce the load on each duplicated ce signal to something pretty small. As a result, you wind up with many many ce generators. The early ce that is distributed to those flip-flops has a large enough fan-out that it also needs to be duplicated to keep the speed up (alternatively you could use many instances of the state machine that generates CE, but that might be complex, and you still need a signal to synchronize them). So in order to get the high speed you end up duplicating the pre-CE signal too. This is a tree structure. erika_uk@my-deja.com wrote: > > HI RAY, > > I am sorry but still having problem > > ?? As a result, you need many parallel (duplicated) CE flip-flops, > which generally are sourced by a register tree (or by parallel state > machines as someone else pointed out here)?? > > what do you mean by register TREE, parallel stae machine..I DON'T SEE > WHY U R USING THE TERM TREE > > --Erika > > In article ?39FDE13E.CA37ADD3@andraka.com?, > Ray Andraka ?ray@andraka.com? wrote: > ? > ? > ? Rick Filipkiewicz wrote: > ? ? > ? ? Ray Andraka wrote: > ? ? > ? ? ? Nope, That's one of the problems with the VIrtex architecture. > They tell you > ? ? ? to use the "low skew routing resource" ie secondary clock network > for this, but > ? ? ? I find it is way too slow compared to the speed of designs I can > do in the > ? ? ? part. The only viable solution I have found is to pipeline the > CE's in a > ? ? ? distribution tree. > ? ? ? > ? ? ? Steven Derrien wrote: > ? ? ? ? > ? ? ? ? Hello, > ? ? ? ? > ? ? ? ? I was wondering if it is possible to use a Virtex BUFG buffer > to drive a > ? ? ? ? non clock signal ( in my case it is a CE signal with a very > heavy > ? ? ? ? fan-out (all DFF CE ports)) > ? ? ? ? > ? ? ? ? Steven > ? ? > ? ? Unusually Ray's no quite right here. I was using this trick to make > the domain > ? ? crossing between the main system clock and a 1/2 speed clock formed > by a divide by > ? ? 2 FF followed by a BUFG [The ASIC Vendor coudn't emulate Virtex's > div2 DLL output]. > ? ? What happens is that you get a warning in MAP and the delay from > the BUFG output to > ? ? the CE inputs is very much longer than the delay to the clock > inputs BUT > ? > ? True, you can make a kludged connection by connecting through a LUT. > I don't > ? think that it is any faster than using the 'low skew' network, and > has a higher > ? skew. The low skew network has a pretty good distribution with well > controlled > ? delays. The problem with it is that it is slow compared to the > potential clock > ? speeds of the device. As a result, you need many parallel > (duplicated) CE > ? flip-flops, which generally are sourced by a register tree (or by > parallel state > ? machines as someone else pointed out here). > ? > ? ? > ? ? o Its still not huge. I've just knocked up a test case that shows > it to be 1.8-2.6 > ? ? nsec against the CLK input delay of 0.59 nsec. > ? ? > ? ? o Its still bounded in that most of the routing is along the global > clock lines so > ? ? that even CE inputs a long way from the global buffer have well > controlled delays. > ? ? > ? ? In the end I had to remove this for the ASIC since the Vendor > couldn't [... or > ? ? wouldn't - I'm still not sure which] allow clock tree connections > to CE inputs. I > ? ? then used Synplify's automatic register replication mechanism to do > the fanout from > ? ? a duplicate of the BUFG input but it was still a lot more hassle. > ? ? > ? ? Of course even though it works at present Xilinx might always, in > their infinite > ? ? wisdom, change it from a warning to an error. > ? > ? -- > ? -Ray Andraka, P.E. > ? President, the Andraka Consulting Group, Inc. > ? 401/884-7930 Fax 401/884-7950 > ? email ray@andraka.com > ? http://www.andraka.com or http://www.fpga-guru.com > ? > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26826
Did you use the update design function. It will clean up the BELs that were generated by the mapper. You do lose placement for anything that has changed names, just as youwould if you were using guide. when you have the floorplanner open, pull down the file menu and select the update design option. When the dialog box opens, select the name of your new netlist. news@rtrussell.co.uk wrote: > > Ray Andraka ?ray@andraka.com? wrote: > > : Open the floorplanner on the old design, do a replace all with placement and > : save it. That makes a floorplan file from the automatic place and route > : solution. > > : Then, when you start with a new design, select your saved floorplan as the > : floorplan file for the new design. As long as hierarchical names are not > : changed, it will work fine in 3.1 > > I tried that, but it doesn't seem to work. Even if I > make *no changes at all* to the design, 'map' reports > a large number of "not matched to a frag - ignoring > constraint" warnings, and the resulting build has a > very poor performance compared to the original one > from which the floorplan was generated. Some of the > warnings seem to be related to MUXCYs which are used > to generate local logic 0's (as suggested in an earlier > thread). > > Richard. > http://www.rtrussell.co.uk/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26827
Hi Qian, Can you supply a bit more information for this e.g.: What version of Foundation (check in the menu item Help->about) are you using? What synthesis tool are you using? What is the exact wording of the error you are seeing? Colm Qian Zhang wrote: > Hi There > > When I try to synthesis VHDL file, > when I check check syntax, it always > show me Error, cannot generate report file. > What is wrong with Foundation? > > Thank you very much! > > QianArticle: 26828
In article <39EDDC34.E81D3E2E@andraka.com>, Ray Andraka <ray@andraka.com> wrote: .> Yep. Try Nu Horizons or Insight. We got them from one of the two (not sure > which now). We got XC2S50-5FG256 I've just been quoted 14-18 weeks lead-time for some XC2S50-5TQ144C by our distributor, Insight Memec, in the UK Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26829
Leon Heller wrote: > > I've just been quoted 14-18 weeks lead-time for some XC2S50-5TQ144C by > our distributor, Insight Memec, in the UK > I was just quoted 16 weeks for XC2S30-5VQ100C Anyone able to buy XC2S30 or XC2S50 with reasonable leadtimes?Article: 26830
Hi,
I've been working with ASIC design under Unix for the past 10 years
and I'm happy to see that I can run a lot of my EDA SW under Linux on
cheap PC's.
Lately I've been working with Alliance under Solaris and was wondering
if Xilinx have any plans to release their software under Linux?
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 26831Ray Andraka wrote: > > I'm referring to cases where I've had a fan-out on CE that is very large > (several hundred or more). You can break that into multiple parallel CE > signals, all doing the same thing to decrease the time due to fan-out. In order > to get significantly better than the low skew network, you need to reduce the > load on each duplicated ce signal to something pretty small. As a result, you > wind up with many many ce generators. The early ce that is distributed to those > flip-flops has a large enough fan-out that it also needs to be duplicated to > keep the speed up (alternatively you could use many instances of the state > machine that generates CE, but that might be complex, and you still need a > signal to synchronize them). So in order to get the high speed you end up > duplicating the pre-CE signal too. This is a tree structure. All that is one of the reasons I ended up buying Synplify. Put a max fan-out attribute on a signal and it gets replicated! Very neat. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26832
Dear Newsgroupies,
Has anyone here used Xilinx 3.2i? I am presently using 3.1i, with
service_pack_31i_3_2_03i_pc and am fairly happy with it. Does 3.2i with SP4
bring anything great to the table? Does it have any bugs that anyone has
uncovered?
Thanks.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
Article: 26833Yep, but the thing is it doesn't pay much attention to partitioning the replication, so as a result you can wind up with pieces that you want to share a slice using different clock enables. This has come up as a problem a number of times on logic with carry chains, and is the main reason the carry chains get messy. Amplify might fix that to some degree, I don't know fer sure tho. It can also be fixed using local copies of the CE with syn_keep buffers added to keep it from breaking up stuff that should have a common replicated ce. Andy Peters wrote: > > Ray Andraka wrote: > > > > I'm referring to cases where I've had a fan-out on CE that is very large > > (several hundred or more). You can break that into multiple parallel CE > > signals, all doing the same thing to decrease the time due to fan-out. In order > > to get significantly better than the low skew network, you need to reduce the > > load on each duplicated ce signal to something pretty small. As a result, you > > wind up with many many ce generators. The early ce that is distributed to those > > flip-flops has a large enough fan-out that it also needs to be duplicated to > > keep the speed up (alternatively you could use many instances of the state > > machine that generates CE, but that might be complex, and you still need a > > signal to synchronize them). So in order to get the high speed you end up > > duplicating the pre-CE signal too. This is a tree structure. > > All that is one of the reasons I ended up buying Synplify. Put a max > fan-out attribute on a signal and it gets replicated! Very neat. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt." -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26834
I'm using it. It fixes a number of bugs, but there is one that it created. Can't remember off hand which one it was, as I currently have several cases open. It is supposed to be fixed in the service pack due out next week. "S. Ramirez" wrote: > > Dear Newsgroupies, > Has anyone here used Xilinx 3.2i? I am presently using 3.1i, with > service_pack_31i_3_2_03i_pc and am fairly happy with it. Does 3.2i with SP4 > bring anything great to the table? Does it have any bugs that anyone has > uncovered? > Thanks. > -Simon Ramirez, Consultant > Synchronous Design, Inc. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26835
"Petter Gustad" <spam@gustad.com> wrote in message news:87g0ldj5et.fsf@firewall.home.gustad.com... > I've been working with ASIC design under Unix for the past 10 years > and I'm happy to see that I can run a lot of my EDA SW under Linux on > cheap PC's. > > Lately I've been working with Alliance under Solaris and was wondering > if Xilinx have any plans to release their software under Linux? This doesn't answer your question directly, but perhaps could get you the same results... Have you considered running the Windows NT version of Alliance using emulation software available for Linux? Specifically, VMware (http://www.vmware.com) or Win4Lin (http://www.win4lin.com). The savings on hardware and software cost easily offset those of buying the emulation software. Regards, JamieArticle: 26836
Hello Santiago,
Xilinx has a university program which can be found at the following URL:
http://university.xilinx.com/
The limitations can be found under frequently asked questions at the
following URL:
http://www.xilinx.com/products/software/cpldswfaqs_new.htm
I've cut and pasted the limitations below.
Thanks for the feedback! There is always room for improvement!
Q: Are there limitations on the third party tools included with WebPACK, and
if so, what are they?
A: These tools are starter versions offered by third
party vendors such as Model Technology Inc.
and Visual Software Solutions. The scaled down versions
demonstrate the capabilities of their
software and provide an indication of whether the full
scale tool would be useful for the designer.
The limits for ModelSim Xilinx Starter Edition are 500
lines of debuggable code. Beyond this limit,
the processing begins to slow down, but does not stop.
The usefulness of this software is going to
depend on coding style and type of simulation (either
functional or timing) that is desired.
Visual Software Solutions tools comprised of StateCAD
and HDL Bencher follow the limits below:
Unregistered
------------------
StateCAD: 6 states, 16 transitions, 2 logic
equations
Bencher: 12 signal assignments, 6 ports, max bus
width (port) 8 bits
Registered
------------------
StateCAD: 10 states, 20 transitions, 8 logic
equations
Bencher limit is 21 assignments (other limits
dropped)
HDL Bencher and StateCAD may be used unregistered and
without a license up to the limits given
above. Once the limits are reached, the tools will
automatically prompt you to register. Registration is
as easy as providing a name and e-mail address. A
password will be sent directly to the address
given within minutes, and the limits are automatically
relaxed.
Both MTI and Visual Software Solutions offer registered
users a discount on full software support
purchases.
Best regards,
Richard Chidester
Santiago de Pablo wrote:
> Richard Chidester escribió:
> >
> > Just wanted to make everyone aware that the new WebPACK ISE which adds
> > support for FPGAs (Spartan II and Virtex 300E) is now available.
> >
> > Go to http://www.xilinx.com/products/software/webpowered.htm
>
> Hi folks,
>
> I've downloaded the WebPACK ISE for PLDs, trying to find a development
> environment using VHDL for my students. When I use it I've found a lot
> of limits: no more than 21 transitions on the bencher, ...
>
> I want to know which are the complete *list of limits* of these (free)
> products. Hey, Xilinx guys, give our students a really *free* set of
> software! (Currently we are using Max+Plus II 7.21 and 9.23).
>
> Cheers, Santiago.
Article: 26837
Peter,
This may have an obvious solution, but have you tried running the
Alliance Solaris tools under Linux? I'd like to know if you have and ran
into problems. Since Solaris is a type of Unix, maybe it will directly run
under Linux.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Petter Gustad" <spam@gustad.com> wrote in message
news:87g0ldj5et.fsf@firewall.home.gustad.com...
>
> Hi,
>
> I've been working with ASIC design under Unix for the past 10 years
> and I'm happy to see that I can run a lot of my EDA SW under Linux on
> cheap PC's.
>
> Lately I've been working with Alliance under Solaris and was wondering
> if Xilinx have any plans to release their software under Linux?
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
> #include <stdio.h>/* compile/run this program to get my email address */
> int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
>
Article: 26838Ray Andraka wrote: > > Yep, but the thing is it doesn't pay much attention to partitioning the > replication, so as a result you can wind up with pieces that you want to share a > slice using different clock enables. This has come up as a problem a number of > times on logic with carry chains, and is the main reason the carry chains get > messy. > Amplify might fix that to some degree, I don't know fer sure tho. It can also > be fixed using local copies of the CE with syn_keep buffers added to keep it > from breaking up stuff that should have a common replicated ce. Ah, I see. I was just using the fan-out to replicate things like output enables and such. It still be the hell out of putting the duplicate registers in the code, and having to convince the tool NOT to optimize the duplicates away! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26839
Ray Andraka wrote: > > Yep, but the thing is it doesn't pay much attention to partitioning the > replication, so as a result you can wind up with pieces that you want to share a > slice using different clock enables. This has come up as a problem a number of > times on logic with carry chains, and is the main reason the carry chains get > messy. > Amplify might fix that to some degree, I don't know fer sure tho. It can also > be fixed using local copies of the CE with syn_keep buffers added to keep it > from breaking up stuff that should have a common replicated ce. Actually, the better use for replication that I came up with was a somewhat-global sync reset signal. I wonder if I would have been better off driving that onto a BUFGLS. I never tried it. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26840
Ray Andraka wrote: > > Yep, but the thing is it doesn't pay much attention to partitioning the > replication, so as a result you can wind up with pieces that you want to share a > slice using different clock enables. This has come up as a problem a number of > times on logic with carry chains, and is the main reason the carry chains get > messy. > Amplify might fix that to some degree, I don't know fer sure tho. It can also > be fixed using local copies of the CE with syn_keep buffers added to keep it > from breaking up stuff that should have a common replicated ce. Actually, the better use for replication that I came up with was a somewhat-global sync reset signal. I wonder if I would have been better off driving that onto a BUFGLS. I never tried it. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26841
Ray Andraka wrote: > > Yep, but the thing is it doesn't pay much attention to partitioning the > replication, so as a result you can wind up with pieces that you want to share a > slice using different clock enables. This has come up as a problem a number of > times on logic with carry chains, and is the main reason the carry chains get > messy. > Amplify might fix that to some degree, I don't know fer sure tho. It can also > be fixed using local copies of the CE with syn_keep buffers added to keep it > from breaking up stuff that should have a common replicated ce. Actually, the better use for replication that I came up with was a somewhat-global sync reset signal. I wonder if I would have been better off driving that onto a BUFGLS. I never tried it. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26842
"S. Ramirez" wrote: > > Peter, > This may have an obvious solution, but have you tried running the > Alliance Solaris tools under Linux? I'd like to know if you have and ran > into problems. Since Solaris is a type of Unix, maybe it will directly run > under Linux. Simon, Different binaries are required. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26843
"S. Ramirez" wrote: > > Dear Newsgroupies, > Has anyone here used Xilinx 3.2i? I am presently using 3.1i, with > service_pack_31i_3_2_03i_pc and am fairly happy with it. Does 3.2i with SP4 > bring anything great to the table? Does it have any bugs that anyone has > uncovered? I was kinda surprised how they went from 3.1i SP3 to 3.2i SP4. That's a Microsoft versioning scheme! -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26844
Andy,
That sucks! I thought all those Unix systems were compatible and
that's why Peter had no problem running his EDA tools under Linux.
Apparently, I have been mislead by the Linux people! Good thing I haven't
switched -- yet.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8tnmh8$15h3$5@noao.edu...
> "S. Ramirez" wrote:
> >
> > Peter,
> > This may have an obvious solution, but have you tried running the
> > Alliance Solaris tools under Linux? I'd like to know if you have and
ran
> > into problems. Since Solaris is a type of Unix, maybe it will directly
run
> > under Linux.
>
> Simon,
>
> Different binaries are required.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
Article: 26845Here is a page I like to check on every now and then... it is basically a listing of (2) webpages that give the success / failures that people have seen with Xilinx tools and Linux (mainly through windows emulators). http://dmoz.org/Computers/Hardware/Programmable_Logic/FPGA/Online_Articles/ Curtis "S. Ramirez" wrote: > Andy, > That sucks! I thought all those Unix systems were compatible and > that's why Peter had no problem running his EDA tools under Linux. > Apparently, I have been mislead by the Linux people! Good thing I haven't > switched -- yet. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > news:8tnmh8$15h3$5@noao.edu... > > "S. Ramirez" wrote: > > > > > > Peter, > > > This may have an obvious solution, but have you tried running the > > > Alliance Solaris tools under Linux? I'd like to know if you have and > ran > > > into problems. Since Solaris is a type of Unix, maybe it will directly > run > > > under Linux. > > > > Simon, > > > > Different binaries are required. > > > > -- a > > ---------------------------- > > Andy Peters > > Sr. Electrical Engineer > > National Optical Astronomy Observatory > > 950 N Cherry Ave > > Tucson, AZ 85719 > > apeters (at) n o a o [dot] e d uArticle: 26846
same problem there, as synplicity tends to use FDREs for sync resets, and once again both flip-flops in the slice have to have the same signal. Andy Peters wrote: > > Ray Andraka wrote: > > > > Yep, but the thing is it doesn't pay much attention to partitioning the > > replication, so as a result you can wind up with pieces that you want to share a > > slice using different clock enables. This has come up as a problem a number of > > times on logic with carry chains, and is the main reason the carry chains get > > messy. > > Amplify might fix that to some degree, I don't know fer sure tho. It can also > > be fixed using local copies of the CE with syn_keep buffers added to keep it > > from breaking up stuff that should have a common replicated ce. > > Actually, the better use for replication that I came up with was a > somewhat-global sync reset signal. > > I wonder if I would have been better off driving that onto a BUFGLS. I > never tried it. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt." -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26847
Petter Gustad wrote: > > Hi, > > I've been working with ASIC design under Unix for the past 10 years > and I'm happy to see that I can run a lot of my EDA SW under Linux on > cheap PC's. > > Lately I've been working with Alliance under Solaris and was wondering > if Xilinx have any plans to release their software under Linux? > > Petter There are a number of us running the Xilinx implementation tools under Wine in Linux. I have found that all the command line programs work fine; xnf2ngd, edif2ngd, ngdbuild, map, par, trce, bitgen, promgen, ngdanno, ngd2vhdl, etc... The "Design manager" does not work under wine, as for as I know. So I have a somewhat elaborate but very easy (I think) to use script that runs through the process, creating directories, checking for errors, etc. Which I think a lot of people like to do anyway. Also, the graphical fpga_editor runs and at least lets you navigate around and look at the guts of the chip; I have not tried to actually use it for editing, though. Someone even put up a web page on his mostly similar method: http://www.polybus.com/xilinx_on_linux.html The one weak link on Linux is a lack of a synthesis tool. Though Synplicity had a job posting for Linux programmer some months back, so here's hoping... I actually purchased VMware, since I still need it to run the synthesis tools. But that is all I use it for. All my other tools are either native Linux or run under wine. -- My real email is akamail.com@dclark (or something like that).Article: 26848
Ray Andraka wrote: > Yep, but the thing is it doesn't pay much attention to partitioning the > replication, so as a result you can wind up with pieces that you want to share a > slice using different clock enables. This has come up as a problem a number of > times on logic with carry chains, and is the main reason the carry chains get > messy. Resets have a similar problem. > Amplify might fix that to some degree, I don't know fer sure tho. To a degree, yes. Floorplan the CE (or reset) logic into multiple blocks with the registers, with small enough blocks that more replication of this logic isn't needed. There still is an issue when the logic driving a multi-bit register is implemented using the CE and/or reset/set inputs to the flipflops so now the register will not fit where it needs to fit, as the Xilinx mapper can only put one FF into a slice if the CE, the reset or the set is different. -- Phil HaysArticle: 26849
Jim Patterson <jpatters@stny.rr.com> wrote in message news:T4XK5.99848$JS3.15201591@typhoon.nyroc.rr.com... > Just starting at the VHDL so be gentle. I am doing a simple ALU for my > class. Having trouble with the various types in VHDL. I am trying to do a > case statement on the control input (opcode). When I get to the code that > says to add, subtract, and, or, etc. I get errors. The errors are usually > type mismatches. It seems like some operations (add, subtract) what the > inputs to be integers while other operations (and, or) what them to be > bit_vectors or std_logic_vectors. How can I do this? I have tried several > different things and can't get it going. I know this is simple and I am > just missing something (I hope). Thanks a bunch. > > -- > Jim Patterson > jpatters@stny.rr.com > jim u can try to include: library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; well i don't think that u getting problem due to the what u think : add & sub for integer and 'or' & 'and' do it for bit or std_logic. What u might have done is ur input is std_logic or bit and ur output is integer. try to declare output same as input.
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