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Thanks Bret, makes you wonder why Allan or I never opened a webcase about this rather than work around the problem. Could've been fixed years ago. Bloody hardware engineers! Cheers, Syms.Article: 71801
Simon wrote: > ... > So, I'll consult the collective wisdom of the group - which is probably > what I ought to have done in the first place :-) Can I ask if there's > anyone who's used Foundation on both architectures... > > o If there are any differences between the two ? The main thing I notice is that some toolkit was used to convert the Windows gui to run under Linux. The resulting "feel" of the GUIs is a bit sluggish compared to the Windows versions. But it is not too bad. I have very recently switched to using the "native" Linux tools exclusively. I am running both ISE and EDK in the native Linux versions, but I will admit to not using the EDK gui much. I set up the initial project with the GUI, and then mostly edit and run the resulting files at the command line. I would like to get ChipScope, but alas, that is (still?) not available on Linux. > o Is there anything you can't do from the Linux environment ? ChipScope. I have not run into any other problems yet. I would have to say I am pleasantly surprised, considering the complexity. > o Is Linux a completely self-contained environment for development ? It works for me. I recently reformatted the disk on my main design machine, and Windows is gone. My laptop is still dualboot, but I don't do serious design work there. > o How stable is it ? I haven't had a problem. > o What version of Linux are you running it on ? RH 9, kernel 2.4.20. > o Have you tried it on an AMD64 processor ? No, but I doubt any of the programs are compiled for a 64 bit processor, so I am not sure there would be a big performace improvement. I would certainly be interested in knowing if there were, though! -- My real email is akamail.com@dclark (or something like that).Article: 71802
Hallo, have a look at http://www.altera.com/literature/lit-config.jsp and especially volume 2. HTH, Carlhermann "George" <george.martin@att.net> schrieb im Newsbeitrag news:e9d879fa.0407301021.4fe97720@posting.google.com... > Hello: > > I'm looking for the the data sheet on an Altera EPC2LC20. > Can't find in on Altera web site. And a google search didn't uncover anything. > It did direct me fo web pages but no data sheets for this device. > Anyone got a copy? > > Thanks > GeorgeArticle: 71803
You asked an Altera-specific question, which delayed my response just a bit :-) Any modern programmable device from any of the major manufacturers will give you a 1 ns or faster rise/fall time, and we all consider 20 MHz a low frequency. You should not have any problem with your design, just stay away from ancient parts. Peter Alfke, Xilinx > From: dhruvish@gmail.com (Drew) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 30 Jul 2004 10:52:21 -0700 > Subject: Re: On-Chip Oscillator > > jg, > > My output is a clock which eventually will control A/D converter. Now, > the clock for converter needs to have < 2ns Rise Time (For faster > sampling rate, in my case 10MSamples/s) by the spec of it. > > Nobody really replied to my other question, can we generate clock on > the Programmable Device (Max3032)? I want to generate 20MHz clock on > the EPLD. > > Thanks, > DrewArticle: 71804
Thomas Stanka wrote: > Rene Tschaggelar <none@none.net> wrote: > >>praveen wrote: >> >>>What is the differences between FPGA and CPLD? >> >>The common understanding is that CPLDs are EEPOM or Flash based >>and have to be programmed once. They have up to say 512 Flipflops. >>FPGAs on the other hand are RAM based, meaning they have to be >>programmed at every powerup. This usually happens with a small >>external Flash, a CPU or whatever. The smallest FPFA is far bigger >>than the biggest CPLD. > > > That's pretty wrong. Actel has flashbased Fpgas (and antifuse based). > > The main difference is that CPLDs are mainly focused on > Input->(fast)Logic->Register->Output > while Fpgas are typically slower for CPLD tasks, but have more > configuration possibillities and support more complex logic > structures. > A typical CPLD design would have fast but simple operations while a > fpga has complex operations based on many internal registers. True, Flash FPGAs blurr the line. However according to the data I have available some of your statements are also not correct. The fastest CPLD I came across does in the order of 220 MHz, and has no internal multiplier. Whereas the FPGAs, at least the more modern ones tend to have clock multipliers and 220 MHz is not considered fast at all. ReneArticle: 71805
Drew wrote: > jg, > > My output is a clock which eventually will control A/D converter. Now, > the clock for converter needs to have < 2ns Rise Time (For faster > sampling rate, in my case 10MSamples/s) by the spec of it. Just make sure you select the FAST edge option on that pin, and keep the traces as short as possible. > Nobody really replied to my other question, can we generate clock on > the Programmable Device (Max3032)? I want to generate 20MHz clock on > the EPLD. I thought I had. The answer is yes, it can be done, (we have done various delay line clocks inside CPLD ) but you get low performance. If you are running an ADC where low noise matters, I'd avoid the on-chip oscillator. If you are using a CPLD with hysteresis, you can build RC oscillators, (again, low performance) but I do not think the Altera 3032 meets that. If you mean attach a crystal to the CPLD, that can also be done, but again at high risk. Spurious Oscillations, 'edge fur', and incorrect harmonics are all possible outcomes. If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive, look at http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf Or, you can use an oscillator module. -jgArticle: 71806
Mario Trams <Mario.Trams@informatik.tu-chemnitz.de> wrote in message news:<cedcm7$nn7$1@anderson.hrz.tu-chemnitz.de>... > Rajeev wrote: > > > Lets take an example and see what the concensus is: > > > > Gate Count: 40K ASIC gates > > Speed: 50 MHz > > PinOut: 100 pins > > Other: ??? > > > > > > One Configuration: Spartan-III would be a suitable fit with $20 > > price tag (scaling to $10 with volume) + $3 prom. > > > > Altenatives from Altera? Actel (may be anti fuse?) > > > > Could some one fill in... > > > Where is the relation with my posting? > > Mario Mario, I was trying to being up an example so that we could see which techonlogy from which vendor makes best sense. This happens to be a design I worked in the past. -RajeevArticle: 71807
Do not use an on-chip oscillator (they are not stable). Do not use an external RC, (that's better, but still not stable) Do not use a crystal driven by a CPLD or FPGA, because it's more trouble and problems than it is worth. Spend a whole dollar ( or $ 1.50) and buy yourself a crystal oscillator module and live happily ever after ! Peter Alfke > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Sat, 31 Jul 2004 08:30:43 +1200 > Subject: Re: On-Chip Oscillator > > Drew wrote: >> jg, >> >> My output is a clock which eventually will control A/D converter. Now, >> the clock for converter needs to have < 2ns Rise Time (For faster >> sampling rate, in my case 10MSamples/s) by the spec of it. > > Just make sure you select the FAST edge option on that pin, and keep the > traces as short as possible. > >> Nobody really replied to my other question, can we generate clock on >> the Programmable Device (Max3032)? I want to generate 20MHz clock on >> the EPLD. > > I thought I had. The answer is yes, it can be done, (we have done > various delay line clocks inside CPLD ) but you get low > performance. > If you are running an ADC where low noise matters, > I'd avoid the on-chip oscillator. > > If you are using a CPLD with hysteresis, you can build RC oscillators, > (again, low performance) but I do not think the Altera 3032 meets that. > > If you mean attach a crystal to the CPLD, that can also be done, > but again at high risk. Spurious Oscillations, 'edge fur', and incorrect > harmonics are all possible outcomes. > > If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive, > look at > http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf > > Or, you can use an oscillator module. > > -jg >Article: 71808
Actually, they are in the year 1994 as ISE still refuses to use long file names (or paths) with spaces in them. Long files names have been with us since Windows 95. Antti Lukats wrote: > http://www.xilinx-china.com/china/xdt/flash_interfaces.pdf > > another unkept promise from Xilinx: take a look at pages 14 and 15 from the > above document! > > Or has anyone seen those free reference designs? > > Q1 CY04 is past already isnt it? > Or am I mistaken with my calendar? > > Antti > PS I just sold my first IP cores :) feels good! > at ebay ;) > http://stores.ebay.com/OpenChip-Online-Shop_IP-Cores > >Article: 71809
http://www.xilinx-china.com/china/xdt/flash_interfaces.pdf another unkept promise from Xilinx: take a look at pages 14 and 15 from the above document! Or has anyone seen those free reference designs? Q1 CY04 is past already isnt it? Or am I mistaken with my calendar? Antti PS I just sold my first IP cores :) feels good! at ebay ;) http://stores.ebay.com/OpenChip-Online-Shop_IP-CoresArticle: 71810
Peter Alfke wrote: > Do not use an on-chip oscillator (they are not stable). As noted, but there are applications where that is perfectly acceptable. > Do not use an external RC, (that's better, but still not stable) There are also application where this is OK. Truckloads of uC ship these days with calibrated RC Osc, that give ~2% precision. Newer CPLDs include hysteresis, to allow 2 & 3 terminal oscillator designs, if one wishes. > Do not use a crystal driven by a CPLD or FPGA, because it's more trouble and > problems than it is worth. As noted. > Spend a whole dollar ( or $ 1.50) and buy yourself a crystal oscillator > module and live happily ever after ! Unless Size, Frequency, or power considerations exclude that. I have not seen many Modules at 32Khz, for example. Modules under around 10mA are also rare, so you can easily find your Osc Module chews far more power than your Xilinx Coolrunner, for example. Depends on the design, but that could be a killer. We have tried the 74lvc1gx04 I mentioned, (Philips have a little Eval PCB ) and it is quite impressive. You can vary Vcc, for quite wide Freq/Power trade offs, and it comes in a tiny SOT23 sized package. > Peter Alfke > > >>From: Jim Granville <no.spam@designtools.co.nz> >>Organization: TelstraClear >>Newsgroups: comp.arch.fpga >>Date: Sat, 31 Jul 2004 08:30:43 +1200 >>Subject: Re: On-Chip Oscillator >> >>Drew wrote: >> >>>jg, >>> >>>My output is a clock which eventually will control A/D converter. Now, >>>the clock for converter needs to have < 2ns Rise Time (For faster >>>sampling rate, in my case 10MSamples/s) by the spec of it. >> >>Just make sure you select the FAST edge option on that pin, and keep the >>traces as short as possible. >> >> >>>Nobody really replied to my other question, can we generate clock on >>>the Programmable Device (Max3032)? I want to generate 20MHz clock on >>>the EPLD. >> >>I thought I had. The answer is yes, it can be done, (we have done >>various delay line clocks inside CPLD ) but you get low >>performance. >>If you are running an ADC where low noise matters, >>I'd avoid the on-chip oscillator. >> >>If you are using a CPLD with hysteresis, you can build RC oscillators, >>(again, low performance) but I do not think the Altera 3032 meets that. >> >>If you mean attach a crystal to the CPLD, that can also be done, >>but again at high risk. Spurious Oscillations, 'edge fur', and incorrect >>harmonics are all possible outcomes. >> >>If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive, >>look at >>http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf >> >>Or, you can use an oscillator module. >> >>-jgArticle: 71811
John_H wrote: (snip of TDC description) > In some TDCs, the ramp is generated by trigger signal and sampled by the > steady clock. If the ramp came from the clock, you'd have large > uncertainties near the corners; the harmonics to get a "nice" corner are > also huge and outside the range of affordable A/D converters. By designing > to guarantee a (reasonably) linear ramp, the trigger-signal's start ramp can > be sampled in 2 spots on the ramp far from the "corner" giving the precise > delta voltage for one sampling clock period. The stop ramp can also be > sampled in 2 spots on the ramp and should have the same delta voltage. The > voltage difference between these two ramp sample pairs relative to the > voltage difference for one clock cycle will give you the offset in time > relative to one clock cycle. But I hate precision analog beyond a few 10s > of MHz. That sounds like a better description of the one I was trying to describe. It is sometimes used for high resolution timing of photomultiplier tube pulses. You could use the semi-analog method to measure the time relative to a steady clock, and count the number of clock cycles in between. The main point I was trying to make was that there are some partly analog methods that can get timing resolution finer than affordable digital methods. There are some that claim 50ps. (snip of sin/cos TDC description) -- glenArticle: 71812
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: : John_H wrote: : (snip of TDC description) :> In some TDCs, the ramp is generated by trigger signal and sampled by the ... For TDCs, look at http://www.acam.de -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71813
Could you please give me a piece of advice?Article: 71814
Hello All I am new to FPGA world and thinking to start self-project for learning purpose. I am thinking of building ethernet switch as exercise and wondering what are the options I have for development board which has ethernet interfaces (2-4) connected to it. Looking for any other suggestion you have. Thanks -- VikramArticle: 71815
Hi Vikram,
If you wish to start your project to FPGA which has ethetnet
interface on it, I suggest you take a look into Altera Stratix
Professional Development Board such as EP1S40F780C5...You can go to
Altera website (www.altera.com) to look for more detail information.
Article: 71816
Hi, to all FPGA expoert,
i wish to ask, when I synthesis my VHDL code using QuartusII ,
my logic function will go to FPGA LE logic assignment while the Altera
LPM Memory module such as LPM_RAM_DQ will go to EAB....
if i wish to use the EAB to perform the logic circuit instead
just of memory module, what should i do? Is there any setting or
options that i need to set???
I looking for your reply, thank you very much.
Article: 71817mikeandmax@aol.com (Mikeandmax) wrote in message news:<20040730131548.23098.00002650@mb-m07.aol.com>... > > > > I've discovered that there is some significant propagation delay > >between the input and bidirectional pin & bidirectional pin to output > >pin in my simulation. I've compared the function LPM_BUSTRI within > >Quartus, a construction made up from Tri-state buffers within Quartus > > often prop delays in a tristate pin are due to OE performance - have you looked > at the OE timinng numbers, or are you indeed looking at the prop delay of the > in or out buffer. Most modern FPGAs now have syncronous OE and data registers > at the pin, which can give you much better timing through the I/O. > > Mike Thomas > Lattice fae Thanks for the update on where to start looking. After reading further the specificatios in the delays within the Stratix IOE structure, I've managed to compute the internal timing and external timing for a given drive strength at the output for a bidirectional pin: Internal Timing: ================= total prop. delay = ip/op register clock-to-output delay + IOE data input to combinatorial output + setup time + hold time + routing delay In equation form I have this as: tpd1 = tco_c + tpcombin2pin_c + tsu + th + tlocal tpd1 = 0.171 + 3.357 + 0.080 + 0.068 + 0.345 tpd1 = 4.021 ns External Timing (4mA drive strength LVTTL) : ========================================== total prop. delay = Setup time for bidi pin using column IOE registers + Hold Time for bidi pin using column IOE registers + Clock-to-Output Delay Bidi pin using column IOE registers In equation form I have this as: tpd2 = tinsu + tinh + toutco tpd2 = 2.33 + 0 + 4.922 tpd2 = 7.252 ns ** Hopefully I interpreted the specifications correctly? If my interpretation is correct, the issue I have now is that I'm not sure if I should take total prop. delay = tpd1 + tpd2 = 11.273 ns? Does anyone know if this is the correct thing to do? My reasoning for combining both is that the internal one relates to the IOE internal timing & the external timing is associated directly to the output bidirectional pin. Regards, PinoArticle: 71818
I have been trying to access Virtual Computer Corp.'s website and have been unsuccessful in reaching the support pages for the Virtual Workbench VW300. I'm looking for any of the files pertaining to the VW300 that might have been posted there. If anybody has these could you please send them to me? Thanks, Derek SimmonsArticle: 71819
Dear all, I am trying to download hello_nios.srec to nios, using the sdk by typing the following command: nr hello_nios.srec I am following the software tutorials provided by altera. for some reason, it is not working, it gives: [SOPC Builder]$ nr hello_nios.srec nios-run: Ready to download hello_nios.srec nios-run: Downloading...................... ........................................... ........................................... nios-run: Terminal mode (Control-C exits) ----------------------------------------- and it stops here, and the program always not downloaded... anyone has an idea what could be the problem...??? regards, johnArticle: 71820
Hi Vikram, you can use any Altera Evaluation Board that has daughtercard connectors on it. From www.devboards.de there is an ethernet daughtercard available with a National 10/100/1000 PHY on it (just a PHY not a MAC/PHY). hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0407311828.4859da8a@posting.google.com>... > Hi Vikram, > > If you wish to start your project to FPGA which has ethetnet > interface on it, I suggest you take a look into Altera Stratix > Professional Development Board such as EP1S40F780C5...You can go to > Altera website (www.altera.com) to look for more detail information.Article: 71821
Hi I'd like to know the price for X3S200 - PQ208 X3S200 - FT256 X3S400 - PQ208 X3S400 - FT256 X3S400 - FG456 I have the price I'll pay for the X3S200 - PQ208, so if you give relative price, ( eg twice the price ) It doesn't have to be precise, just to know if there is a big change or not. My usual account manager is in vacation and It's just a quick info. Thanks SylvainArticle: 71822
On Sun, 01 Aug 2004 15:32:53 +0200, Sylvain Munaut wrote: > Hi > > I'd like to know the price for > X3S200 - PQ208 > X3S200 - FT256 > X3S400 - PQ208 > X3S400 - FT256 > X3S400 - FG456 > > > I have the price I'll pay for the X3S200 - PQ208, so if you give relative price, ( eg twice the price ) > It doesn't have to be precise, just to know if there is a big change or not. > > My usual account manager is in vacation and It's just a quick info. > > > Thanks > > Sylvain Distributer websites have pricing, just look it up there.Article: 71823
Before downloading the srec, make sure that you have programmed the FPGA device on the board using the programming file generated by Quartus. Hope this helps. - Subroto Datta Altera Corp.Article: 71824
We can add multiple interfaces on our Broaddown2 product via plug-in modules. We have a PHY/RJ45 module coming in a few months that may be of interest. Alternatively doing your own add-on is possible. Were you planning to have the MACs in the FPGA or planning to use all in one chips for the ethernet? John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Vikram" <v_ditya@yahoo.com> wrote in message news:yXQOc.2818$Ng.7@newssvr27.news.prodigy.com... > Hello All > > I am new to FPGA world and thinking to start self-project for learning > purpose. I am thinking of building ethernet switch as exercise and wondering > what are the options I have for development board which has ethernet > interfaces (2-4) connected to it. > > Looking for any other suggestion you have. > > Thanks > -- > Vikram > >
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