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Messages from 116375

Article: 116375
Subject: Re: Spartan3AN - Roadmap
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Thu, 8 Mar 2007 04:53:49 +0100
Links: << >>  << T >>  << A >>
Hi,
as Peter already wrote, the difficulty of implementation of ADC is to decide 
what application is to be targeted. I also recognize the problems of 
high-speed, high precise and high bitwidth ADCs may be distorted by the 
noise on the digital chip. I think those ADCs would have to be separately 
powered and accuratley decoupled from the digital part of the FPGA. In case 
the ADCs are targeted for temperature and sytem internal voltage monitoring, 
they are normally not that high sophisticated ones (the measured parameters 
won't change that quick, nor is a 12bit precision necessary. Those ADC may 
be implementable easier, while for e.g. brushless motor controllers those 
ADC's performance may not meet the control loop requirements (phase current 
measurement precision and sample rate). In case these ADCs are attached as 
separate ICs, they are easily selectable to suit the intended application's 
requirement perfectly.
I was just curious for future trends re. more functions to be integrated in 
one FPGA "housing".

Greetings, Carlhermann


Article: 116376
Subject: Re: Query regarding Project.Plz help very urgent
From: pra.vlsi@gmail.com
Date: 7 Mar 2007 20:10:02 -0800
Links: << >>  << T >>  << A >>
On Mar 7, 5:31 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> <pra.v...@gmail.com> wrote in message
>
> news:1173269021.700256.96120@t69g2000cwt.googlegroups.com...
>
>
>
> > I m not getting data from any source.
>
> I wouldn't be too hopeful of getting any data with this type of posting
> either!
>
>
>
> >i have to generate random data.
>
> But wait, perhaps you could generate random data from the content of
> homework questions posted on usenet. The sheer cheek of students asking
> folks to do their work for them for free implies a randomness of thought
> which should be reflected in their postings. Also, their spolling and
> caPITaliSation is atroshus, which should plz your rendom nuber generator.
> Lots of love, Syms.x
>
> p.s. For anyone who's interested in a proper random number generator, a
> search for
>
> random webcam smoke alarm
>
> gives interesting results.

This is not the way to answer questions.


Article: 116377
Subject: Re: No Clock in ChipScope Pro Analyzer
From: "Yaseen Zaidi" <yaseenzaidi@NETZERO.com>
Date: 7 Mar 2007 20:29:54 -0800
Links: << >>  << T >>  << A >>
On Mar 7, 3:06 pm, "Helmut" <helmut.leonha...@gmail.com> wrote:
> I sometimes connet the clockdv output (clock/2) of the clocks dcm to a
> data port. This is very helpful for debuging purpose.

Clock/2 is a good idea.

Thanks.


Article: 116378
Subject: Re: Where do I find CMOS image sensors and lenses?
From: birla.manish@gmail.com
Date: 7 Mar 2007 20:36:02 -0800
Links: << >>  << T >>  << A >>
On Mar 7, 4:22 pm, it.st...@gmail.com wrote:
> Hi everyone,
>
> I would to interface a CMOS image sensor to my FPGA. I'm looking for
> low-end sensor and a matching lens. Nothing fancy or several mega
> pixels - just the bare minimum. Do any of you have a few links to
> vendors or distributors? It doesn't seem to be an "off the shelf"
> product.
>
> Thank you very much.
> Regards
> - Stein

Hi Stein,
I have done such an interface of CMOS iamge sensor with Virtex 4 SX
and LX device. I used CMU image sensor. You may like to buy this from
http://www.cs.cmu.edu/~cmucam/
Also about interfacing it, you can refer to one of my IEEE
publications at
http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4017656&arnumber=4017689&count=124&index=32

Hope it helps,
Regards,
Manish


Article: 116379
Subject: Re: Where do I find CMOS image sensors and lenses?
From: birla.manish@gmail.com
Date: 7 Mar 2007 20:38:09 -0800
Links: << >>  << T >>  << A >>
On Mar 7, 4:22 pm, it.st...@gmail.com wrote:
> Hi everyone,
>
> I would to interface a CMOS image sensor to my FPGA. I'm looking for
> low-end sensor and a matching lens. Nothing fancy or several mega
> pixels - just the bare minimum. Do any of you have a few links to
> vendors or distributors? It doesn't seem to be an "off the shelf"
> product.
>
> Thank you very much.
> Regards
> - Stein

Hi Stein,
I have done such an interfaceing between CMOS image sensor and Virtex
4 FPGA, its quite interesting. You can refer to one of my IEEE
publications at
http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4017656&arnumber=4017689&count=124&index=32
for more detials.
You can buy CMOS image sensor at http://www.cs.cmu.edu/~cmucam/.

Regards,
Manish


Article: 116380
Subject: Re: V.34 Modem IP core
From: "GX" <growxpert@gmail.com>
Date: 7 Mar 2007 20:43:40 -0800
Links: << >>  << T >>  << A >>
On Mar 5, 11:00 am, Eric Smith <e...@brouhaha.com> wrote:
> "GX" <growxp...@gmail.com> writes:
> > any IP vendor out there who supply hard/soft core for V.34Modem?
>
> V.34 is normally (probably always) implemented in software.  You could
> put any DSP core (or RISC core with DSP capability) into your FPGA or
> ASIC, and run a V.34 implementation on it.

Thanks for your response.

After googling, I have found lot of Single chip Modem ASICs.
like, MN195006 from Panasonic.

Did anyone integrated the functional equivalent of these single chip
modem chip in to FPGA/ASIC/SoC?

-GX


Article: 116381
Subject: Re: No Clock in ChipScope Pro Analyzer
From: birla.manish@gmail.com
Date: 7 Mar 2007 20:44:04 -0800
Links: << >>  << T >>  << A >>
On Mar 7, 12:49 pm, "Yaseen Zaidi" <yaseenza...@NETZERO.com> wrote:
> I setup a CDC test configuration using ILA in Chipscope Pro ver
> 8.1.03i. There is activity on bus and on data lines in the Analyzer
> but the system clock (BUFGP) of which the core is running is dead in
> the Analyzer window even though I added the system clock as data to be
> captured.
>
> I know the clock is there otherwise I would not be able to see data. I
> am surprized as why the clock is stuck low. I like to see clock on top
> just as in the conventional logic analyzer testsets for triggering and
> referencing data. There is a seperate tab for clock during setup, but
> wouldn't hurt  adding it as data. Without a clock I am unable to
> fathom anything else.
>
> What's happening here?
>
> Best regards.

If you are interested in seeing clock at chipscope window, you have to
sample it at faster clock. So chipscope cores should geta faster clock
at clock input, and the clock that u want to see at data input.


Article: 116382
Subject: Re: Introducing picosecond delay between two output signals
From: "Ulrich Bangert" <df6jb@ulrich-bangert.de>
Date: Thu, 8 Mar 2007 07:45:16 +0100
Links: << >>  << T >>  << A >>
Austin,

> With 35ps p-p jitter (minimum) in any FPGA...

I am currently designing some circuitry that needs to have jitter as low as
possible, therefore this spec is most interesting for me. Are you talking
about jitter introduced by DCMs or does ANY logic contained in an FPGA
exhibit this jitter even when clocked with a low jitter clock. I have a 0.8
ps RMS jitter clock source available (DS4077). If the logic that I would
like to clock with it would make a 35 ps pp minimum jitter out of it this
would be a sheer catastrophe for me!

Best regards
Ulrich Bangert

"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:esndg3$6os2@cnn.xsj.xilinx.com...
> Amish,
>
> The only method I am aware of is hand routing.  10ps is too small to
> really be able to hold to in all cases.  With 35ps p-p jitter (minimum)
> in any FPGA, and +/- 10 ps route matching (due to process variations
> chip to chip), this may be impossible.
>
> Austin
>
> axr0284 wrote:
> > Hi,
> >  I would like to know what are the common methods of introducing
> > delays as low as 10ps between two outputs in an FPGA. I do not
> > currently have a specific FPGA in mind. I am just looking for a
> > general answer.
> >
> >  I know there are DCMs but this usually adds jitter and one needs to
> > wait for the DCM output to phase lock before the signal is stable and
> > it might take too long in our case. Basically I would want to power up
> > a board and have the delay be set in as short a time as possible. I
> > also need to minimise jitter to a minimum so that the two signals are
> > NEVER high at the same time. Thanks for any answer.
> > Amish
> >



Article: 116383
Subject: Avnet Virtex-4 FX12 mini module
From: jrabbani@gmail.com
Date: 7 Mar 2007 23:35:10 -0800
Links: << >>  << T >>  << A >>

  Hello,

   I have recently bought Avnet Virtex-4 FX12 mini module. I am trying
to implement the Gigabit ethernet communication between the FPGA and
the host PC. Can anyone give me some hints to get started? I have not
found the data sheet for the giga bit ethernet physical transceiver
from Broadcom that the board has on it. The part number for it is
BCM5461. If any one has the data sheet for this transceiver, I will
greatly appreciate. The Broadcom website does not contain any, only a
2 page product flyer is available. Thanks.

  - Javed Rabbani


Article: 116384
Subject: Re: Where do I find CMOS image sensors and lenses?
From: Mike Harrison <mike@whitewing.co.uk>
Date: Thu, 08 Mar 2007 08:11:06 GMT
Links: << >>  << T >>  << A >>
On 7 Mar 2007 03:22:29 -0800, it.stein@gmail.com wrote:

>Hi everyone,
>
>I would to interface a CMOS image sensor to my FPGA. I'm looking for
>low-end sensor and a matching lens. Nothing fancy or several mega
>pixels - just the bare minimum. Do any of you have a few links to
>vendors or distributors? It doesn't seem to be an "off the shelf"
>product.
>
>Thank you very much.
>Regards
>- Stein
http://www.electronics123.com/

Under ' kits & modules-> TV,Video and Camera'

Article: 116385
Subject: odd warning in Xilinx ISE webpack
From: Steve Battazzo <thesteveman_ice9@yahoo.co.jp>
Date: Thu, 08 Mar 2007 00:39:19 -0800
Links: << >>  << T >>  << A >>
At the XST-synthesize stage, I'm getting this weird warning:
"Property use_dsp48" is not applicable for this technology.
I don't have anything in my code that I know of that calls for any such 
thing.. it doesn't affect the program actually running on my board, but 
I'm curious anyway.

Anyone know what this means?

Thanks,

Steve

Article: 116386
Subject: Re: FPGA Vs ASIC design and implementation
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 8 Mar 2007 00:49:59 -0800
Links: << >>  << T >>  << A >>
Hi,

On 7 Mrz., 23:30, "Karl" <karl.polyt...@googlemail.com> wrote:
> Being familiar with FPGA design and implementation flow and illiterate
> with ASIC corresponding one. My question is the following
>
> what are the main similarities/differences between designing and
> implementing an algorithm on these two different targets? in

A good RTL-code has no differences between FPGA and ASIC in general.
You might use resources only available for a special type, but this is
not a question alone of FPGA or ASIC, but also a question if your
choosen technology provides special features like memorys, plls,
dplls, IO-Buffers, clk resources,.....
The difference between ASIC and FPGA is about the size as the
difference between ASIC and ASIC or FPGA and FPGA.

> particular what are the design/implementation practises   and user
> tasks needed in ASIC and not in FPGA implementation and vice versa?

The major difference is the processing after you have the netlist from
synthesis.
For ASIC you typically need to insert testing structures (Scan chains)
which are not usual for fpgas. The layout and P&R for an ASIC may
require much more effort than for an FPGA and after layout step you
need to do post layout verification, produce masks for production,
have the waiver run, packaging, testing unless you have an IC. This is
_much_ more expensive in money and time as the layout, P&R and
programming for an fpga.

> at the end what is the most widely tool used in asic?

Dificult question for all tools used in the designflow. Primetime for
static timing analysis could be the tool with the higest market share
under all tools needed for the ASIC design flow.
Depending on the major design steps I would rank emacs or vi for
design entry, modelsim for simulation. For synthesis it was Synopsys
DC a few years ago, but I expect the tools for physical aware
synthesis have outrun DC in the last five years. I don't know if
Synopsys is still leader in ASIC synthesis, as synthesis needs today a
good link to layout. Layout is AFAIK dominated by Cadence.

bye Thomas



Article: 116387
Subject: Re: Query regarding Project.Plz help very urgent
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Thu, 8 Mar 2007 10:22:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
pra.vlsi@gmail.com wrote:
> On Mar 7, 5:31 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> > <pra.v...@gmail.com> wrote in message
> >
> > news:1173269021.700256.96120@t69g2000cwt.googlegroups.com...
> >
> >
> >
> > > I m not getting data from any source.
> >
> > I wouldn't be too hopeful of getting any data with this type of posting
> > either!
> >
> >
> >
> > >i have to generate random data.
> >
> > But wait, perhaps you could generate random data from the content of
> > homework questions posted on usenet. The sheer cheek of students asking
> > folks to do their work for them for free implies a randomness of thought
> > which should be reflected in their postings. Also, their spolling and
> > caPITaliSation is atroshus, which should plz your rendom nuber generator.
> > Lots of love, Syms.x
> >
> > p.s. For anyone who's interested in a proper random number generator, a
> > search for
> >
> > random webcam smoke alarm
> >
> > gives interesting results.

> This is not the way to answer questions.

This is not the way to ask question. Tell us
- more about your problem
- what you already did yourself
- where you met problems

then somebody might be willing to help you. The readers of this group are
not required  to help you. Mostly the will help, if they find the problem
interesting and the poster doing most of his homework himself.

B.t.w. where did you struggle with a google/altavista/.. search for some/all
of the words FPGA Random HDL VHDL verilog?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 116388
Subject: Re: FPGA Vs ASIC design and implementation
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: 8 Mar 2007 02:31:04 -0800
Links: << >>  << T >>  << A >>
On 7 Mrz., 23:30, "Karl" <karl.polyt...@googlemail.com> wrote:
> what are the main similarities/differences between designing and
> implementing an algorithm on these two different targets?
Verification.
For an ASIC you really must be sure that you get it right the first
time.
Therefore huge efforts are spent on simulation, formal verification,
monte carlo timing simulation for various process parameters and the
like.

Otherwise HDL based ASIC-Design ist very similar to FPGA based design.
For more advanced projects additional degrees of freedom can be
used that require additional knowledge and tools like adding your own
full custom cells, optimizing the clock distribution and power
distribution,
improving manufacturability, etc. But for most designs (as opposed to
most chips produced) automatic tools are used for that.

Kolja Sulima


Article: 116389
Subject: Re: SCons build tool as an alternative to makefiles
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Thu, 08 Mar 2007 10:31:13 +0000
Links: << >>  << T >>  << A >>
"Patrick Dubois" <prdubois@gmail.com> writes:

>> Ahh, yes I can see that being a problem!  In that case, SCons looks
>> like it could be a good route, it certainly looks a lot more flexible
>> than make, but it may have a bigger learning curve (!)
>
> At least by learning SCons I'll be learning some Python (hopefully) as
> well.
>

And then you can use MyHDL for your logic :-)

>> What source language are you using? I can see that it might be tricky
>> to teach SCons how to deal with VHDL, given that entities and archs
>> are unrealted by name to the file they exist in.   Finding C
>> dependencies by header file name is a little easier!
>>
>> But Make will be no easier!
>
> I'm using VHDL. If I could make SCons smart enough to figure out
> dependencies automatically that would be nice but I'm not looking for
> something that smart. Actually I don't want something that smart. I
> want complete control over source files dependencies, even if that
> means that I must specify them explicitly myself.
>

OK, that'll make life easier I imagine.

>> If using VHDL, maybe you could create a Compiler target for Emacs'
>> vhdl-mode that runs XST (for example) instead of Modelsim's vcom etc.
>
> I keep hearing about Emacs vhdl-mode but I'm not using it at the
> moment. I might give it a try when I have more spare time. Thanks for
> the suggestion.
>

Well worth the effort IMHO!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 116390
Subject: Re: Spartan3AN - Roadmap - bigger questions may prevail...
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 8 Mar 2007 10:32:38 -0000
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> wrote in message 
news:esnd9t$6os1@cnn.xsj.xilinx.com...

>
> empty.  We have no hi-K gate dielectric (yet).  How do we 'improve'?
>
> Even Intel and AMD have completely revised their stories:  it is no
> longer about clock speed but "multicore" and "multicore+graphics
> processor."  I have heard at a conference someone ask the Intel
> presenter "isn't where you are going where FPGAs have already been?"
>
I read this back along about Intel's hafnium based high-k material. Is that 
one of the hi-k materials that FPGA manufacturers have tried already?
http://www.intel.com/technology/silicon/45nm_technology.htm?iid=homepage+42nm

Thanks, Symon.




Article: 116391
Subject: Re: Introducing picosecond delay between two output signals
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Thu, 08 Mar 2007 06:04:26 -0500
Links: << >>  << T >>  << A >>
Ulrich Bangert wrote:
> Austin,
> 
>> With 35ps p-p jitter (minimum) in any FPGA...
> 
> I am currently designing some circuitry that needs to have jitter as low as
> possible, therefore this spec is most interesting for me. Are you talking
> about jitter introduced by DCMs or does ANY logic contained in an FPGA
> exhibit this jitter even when clocked with a low jitter clock. I have a 0.8
> ps RMS jitter clock source available (DS4077). If the logic that I would
> like to clock with it would make a 35 ps pp minimum jitter out of it this
> would be a sheer catastrophe for me!

Someone else posted a similar question a few months ago, also asking about the feasibility 
of using FPGAs to work with 10ps-class events. Back then, all the local experts agreed 
that the routing fabric inside FPGAs will add many times this much jitter to any signal 
passing through it, even if the FPGA is only doing a direct routing from one IOB to another.

Dedicated high-precision time bases are heavily shielded, temperature-controlled, built 
with highly specialized single-function low-noise ASICs fed with extensively 
regulated/filtered power supplies, etc., none of which applies to FPGA in a remotely 
comparable scale. On top of all the wonderful external noise sources such as radio 
interference, radiations, magnetic and capacitive coupling with the surroundings, etc., 
FPGAs generate their own heat, their own electromagnetic noises and all the other 
wonderful junk that spews jitter all over the fabric. Keep in mind that each electron 
moving through the FPGA adds its own tiny bit of noise and jitter while each transistor 
happily amplifies the noise of every electron bumping into its gate and that there are 
millions of transistors in the smallest modern FPGAs.

You might have better luck by looking at the smallest CPLDs you can find: much fewer 
transistors, much less on-chip hardware, much simpler routing fabric, etc., this means 
much less internal noise and much fewer routing uncertainties but also pretty much no 
chance to do routing tricks to tweak timings.

Maybe an hypothetical Virtex 7 would be able to do 10ps... but by the time these 
materialize, people will be posting here to ask for sub-ps precision and we'll have to 
tell them to wait for the Virtex 11.

Article: 116392
Subject: CAN vhdl code document
From: barukula.ramesh@gmail.com
Date: 8 Mar 2007 03:22:37 -0800
Links: << >>  << T >>  << A >>
hi,
    i have downloaded the CAN VHDL from opencores but am unable to
understand the code.
can anyone please tell me where i can get the document for that code.

thanks
ramesh.


Article: 116393
Subject: Re: FPGA Vs ASIC design and implementation
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Thu, 08 Mar 2007 06:57:47 -0500
Links: << >>  << T >>  << A >>
Karl wrote:
> Hi,
> 
> Being familiar with FPGA design and implementation flow and illiterate
> with ASIC corresponding one. My question is the following
> 
> what are the main similarities/differences between designing and
> implementing an algorithm on these two different targets? in
> particular what are the design/implementation practises   and user
> tasks needed in ASIC and not in FPGA implementation and vice versa?

The main differences:
- FPGAs come with IOBs (QDR/DDR/SDR, differential/single-ended, in/out/inout, etc.), with 
ASICs you have to license someone else's or create your own
- FPGAs come with some analog bits (PLLs, DACs, ADCs, MGTs, etc.), with ASICs you have to 
license someone else's or create your own
- FPGA resources are pre-placed and the tools have to map whatever you want to do onto 
what exists in the device, with ASICs you can have any primitive you can license or can 
design on your own
- ASICs know no such thing as a LUT4/LUT6/etc., you can have a 20 inputs combinational 
function with nearly no timing penalty since synthesis tools can create it as a primitive, 
unlike FPGAs where everything has to be mapped onto a tree of N-inputs functions.
- FPGA messes are inexpensive - fix the firmware and update... if a prototype releases the 
magic blue smoke, the worst that happens is you chuck out the $1k PCB along with an $5k 
FPGA and you swear to get the PCB right (not mix up power/ground pins) next time around. 
ASIC fuck-ups after the masks have been ordered cost about a million (@90nm) and it takes 
at least a month (more like two) from re-tape-out to new silicon when everything goes well

Because all the very low-level "analog bits" like FFs, IOBs, PLLs, etc. are considered as 
high technological risk items, most small-medium ASIC firms who do not specialize in 
low-level components license other firms' designs instead of whipping their own... unless 
you want to enter the hard-macro library market, it makes no sense to waste millions on 
designing PLL/FF/IOB/etc. libraries if you can license silicon-proven ones for $500k. 
(This $500k figure is only a random believable number.)

So, for me, the most significant difference between ASIC and FPGA after the development 
cost and production timetable is having to license all the low-level nuts and bolts if I 
want to be able to concentrate on the higher-level functions I wish to implement without 
having to worry about going through a dozen re-spins just to get the low-level stuff like 
FFs and IOBs to work properly.

Article: 116394
Subject: Re: Spartan3AN - Roadmap
From: dalai lamah <antonio12358@hotmail.com>
Date: Thu, 08 Mar 2007 12:10:47 GMT
Links: << >>  << T >>  << A >>
Un bel giorno Jim Granville digiṭ:

> Most of the FPGA architectures I know of, all load the config : I'm not 
> sure even anti-fuse devices have the fuses actually in the signal path.
> (imagine the tpd cost, of those fuse-program circuits ! )

Actually I think that Actel antifuse FPGAs are made that way (otherwise it
wouldn't make much sense to differentiate between "flash" and "antifuse"
FPGAs, like Actel does).

See for example http://www.actel.com/documents/RTAXS_DS.pdf, page 7 and
following.

I agree with the OP, in my opinion defining S3AN as "nonvolatile" is quite
inaccurate. Maybe it isn't misleading for an engineer (it's very clear,
starting from the name, that the S3AN is just the usual SRAM device with a
boot flash embedded), but it could be misleading for a IT manager that
takes decisions about things he doesn't know (i.e. the 95% of the grand
total).

-- 
emboliaschizoide.splinder.com

Article: 116395
Subject: Re: Avnet Virtex-4 FX12 mini module
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Thu, 08 Mar 2007 07:16:54 -0500
Links: << >>  << T >>  << A >>
jrabbani@gmail.com wrote:
>   Hello,
> 
>    I have recently bought Avnet Virtex-4 FX12 mini module. I am trying
> to implement the Gigabit ethernet communication between the FPGA and
> the host PC. Can anyone give me some hints to get started? I have not
> found the data sheet for the giga bit ethernet physical transceiver
> from Broadcom that the board has on it. The part number for it is
> BCM5461. If any one has the data sheet for this transceiver, I will
> greatly appreciate. The Broadcom website does not contain any, only a
> 2 page product flyer is available. Thanks.
> 
>   - Javed Rabbani
> 

All the GbE PHYs I have seen have their datasheets available only under NDA.

If the sources for the ML-401 demos (IIRC, there was a networking demo in there) are 
available, you could look around in there to find the PHY's initialization sequence.

Alternately, I presume GbE PHYs belong to a finite number of families (MII for example) so 
you might be able to get baseline functionality by reading those generic PHY interfaces' 
specs.

Article: 116396
Subject: Re: Introducing picosecond delay between two output signals
From: "axr0284" <axr0284@yahoo.com>
Date: 8 Mar 2007 05:28:03 -0800
Links: << >>  << T >>  << A >>
Thanks for all the answers. I guess using an external component might
be more appropriate in this case. We used to use the AD9501 but it's
going obsolete thus the problem. Anyways I'll keep digging for a
solution. Thanks,
Amish



Article: 116397
Subject: Re: Introducing picosecond delay between two output signals
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 08 Mar 2007 14:07:36 GMT
Links: << >>  << T >>  << A >>
axr0284 wrote:
> Thanks for all the answers. I guess using an external component might
> be more appropriate in this case. We used to use the AD9501 but it's
> going obsolete thus the problem. Anyways I'll keep digging for a
> solution. Thanks,
> Amish

You can use the FPGA to do all the random logic you need on the signal 
but you must then *reclock* the signal external to the FPGA with your 
high precision clock.  The output from the FPGA will be "sloppy" 
compared to your sub-picosecond jitter.  A reclocked output will restore 
your extrememly low jitter performance.

Article: 116398
Subject: Re: Introducing picosecond delay between two output signals
From: jhmccaskill@gmail.com
Date: 8 Mar 2007 06:08:23 -0800
Links: << >>  << T >>  << A >>
On Mar 8, 7:28 am, "axr0284" <axr0...@yahoo.com> wrote:
> Thanks for all the answers. I guess using an external component might
> be more appropriate in this case. We used to use the AD9501 but it's
> going obsolete thus the problem. Anyways I'll keep digging for a
> solution. Thanks,
> Amish


For all my 10ps programmable delay line applications, I just use the
On Semiconductor MC10EP195.

http://www.onsemi.com/PowerSolutions/product.do?id=MC10EP195

Just remember that while ps may be very small, they Hertz just as
much.

Regards,

John McCaskill
www.fastertechnology.com



Article: 116399
Subject: Re: Introducing picosecond delay between two output signals
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Thu, 08 Mar 2007 09:18:34 -0500
Links: << >>  << T >>  << A >>
axr0284 wrote:
> Thanks for all the answers. I guess using an external component might
> be more appropriate in this case. We used to use the AD9501 but it's
> going obsolete thus the problem. Anyways I'll keep digging for a
> solution. Thanks,
> Amish

I tried searching a bit but did not find anything that comes close... the nearest I have 
seen was a Maxim part that had 25ns jitter and was marketed as a "programmable delay line" 
instead of "programmable delay generator".

I am almost certain I have seen the AD9501 (or a similar old chip, if there is any) pop up 
in one or two threads here over the last year. With some luck, the people involved may 
still be around.



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