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There is a separate group for the VHDL questions : comp.lang.vhdl
I think what you want is a flip-flop with enable. I don't think "when" can
be used in this context. The standard way of coding this would be as shown
below:
process(clk)
begin
if clk='1' and clk'event then
count <= count + 1;
if count ="01" then
R <= composante;
end if;
if count ="10" then
G <= composante;
end if;
if count ="11" then
B <= composante;
end if;
end if;
end process;
/Mikhail
Article: 116301Symon, you are welcome. An out of office junk filter is mandatory for SI-List sanity. Intel has been doing what you mention for a long time. The cut-off frequency between the PCB and package is down in the low MHz, and falling. For all of those other chips, the keys to good decoupling are: low inductance, low inductance, and low inductance. That is why I like X2Y's so much and consult for X2Y. Six vias with one X2Y will get you 100pH at the surface + 4-5pH / mil for plunge down to the power cavity. Only IDC caps come close with similar numbers for eight vias. Resonance management is a matter of managing phase. That too means getting low inductance. I have long been fascinated with the Proadlizers but have never found a situation where I felt they were the best answer. They are (or were ) pricey, big and need a lot of vias. I have always found I could synthesize a cheaper solution with cheaper capacitors, sometimes a little creative etch, and in the very rare instance a little iron. The FPGA guys have an interesting set of trade-offs to resolve. They tend to use power pins for signal return path as well as power distribution. They also don't get to choose return path of things like DDR2 memory, which is Vss for data and Vccio for address / control. As edge rates continue to push upwards, this gets trickier to manage. Regards, Steve. On Mar 6, 3:20 am, "Symon" <symon_bre...@hotmail.com> wrote: > <s...@x2y.com> wrote in message > > news:1173137413.433634.222140@n33g2000cwc.googlegroups.com...> In the PS3 > > application, those mighty ASICs have a lot of bypass under the lid. > >>From a system design perspective this is cheaper than trying to make > > the PCB do all the work. The PCB just becomes a low frequency power > > distribution network. Since Sony isn't asking the PCB to distribute > > high frequency, using the Proadlizers to isolate noise is an effective > > way to limit EMI propagation. That allows meeting FCC with thicker > > dielectric in the power planes of the PCB. > > > Regards, > > > Steve. > > Hi Steve, > Firstly, thanks for your post. I lurk on the SI-list (posting is a pain with > all those 'out-of-office' replies) which is how I found your stuff onX2Y. > The paragraph of yours I've quoted above explains to me what's going on > inside a PS3. For a while I was worrying that I'd missed a big trick with my > FPGA board designs. If FPGA manufacturers follow this lead of putting even > more bypassing on the BGA carrier, and I guess that soon they will have no > choice, then the PCB power distribution requirements will become a little > less rigorous. > Thanks again, Symon.Article: 116302
Patrick Dubois wrote: > On Mar 6, 3:59 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > wrote: >> >> Surprised that Cadence prefers Verilog? Not really... after seeing so >> many ISE VHDL bugs suggesting Verilog as the work-around until ISE >> v90.87 (many of these fixes keep getting pushed back to the next >> revision), I might decide to switch to Verilog for my future projects -VHDL 200X(which promises significant nonsense reduction) is getting >> nowhere and it'd be years until ISE gets it right anyhow. > > Instead of ditching VHDL for Verilog, you might want to consider > Synplify instead of xst. I am using some tidbits of VHDL-200x in my > current design and xst produced a wrong netlist from that vhdl. I have > access to Synplify for my master's degree (thankfully) and I ran that > piece of code through Synplify. The post-synthesis simulation showed > that the result from Synplify was correct, contrary to xst (v9.1 btw). If I had access to synplify, that would probably make my life sympler... but since I am between jobs right now and ASIC/FPGA-oriented shops in my area can probably be counted on two or three hands, it may be a while until I get an opportunity to update my 8.1 suite (ISE+EDK+ChipScope) for cheap/free... unless I decide to take one or two master classes to sneak into edu programs.Article: 116303
> If I had access to synplify, that would probably make my life sympler... > but since I am between jobs right now and ASIC/FPGA-oriented shops in my > area can probably be counted on two or three hands, it may be a while > until I get an opportunity to update my 8.1 suite (ISE+EDK+ChipScope) > for cheap/free... unless I decide to take one or two master classes to > sneak into edu programs. If you ever needs some features/bug fix in a later ISE version (works for xst only), there's one way to do it. You can download the webpack for free and compile some piece of code with a target chip in the same family but smaller that the full ISE Foundation allows. You can then revert to your older full version to compile your top level and merge every ngc together. Of course that only works for the xst part of the flow, for the downstream tools you need to target your final (big) chip AFAIK. I used this technique recently to benefit from some improvement in xst v9.1 over xst v8.1. Good luck for your job search Daniel. If I recall correctly from your signature, you're from Montreal right? PatrickArticle: 116304
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1173203586.424949.18610@s48g2000cws.googlegroups.com... > > Hi Kevin, > In my first posting, there are 3 questions: > 1. Why doesn't compiler generate an error for unintended latch > generation? Simply put because it is not an 'error' to write code that infers a latch. To presume that every latch is 'unintended' would be wrong. > This question is satisfactorily answered: there is a new attribute to > give errors if an unintended latch is to generate. It says that some > other people had already observed the situation long time ago. > If you choose to use that attribute and find a tool that supports it then by all means use it. But keep in mind that if you forget to use the new attribute (because people are human) that you can still end up in the same situation. It's up to you if that's the coding style you prefer to use to avoid unintended latches, personally I prefer other coding styles but the attribute is at least an improvement and gives another method which is good. No matter which of these two methods you use, you can still get an 'unintended latch' with the following type of code which infers a latch Q <= (C and D) or (not(C) and Q); This is obviously a very stripped down example, a 'real' design might be much more complicated, but you have to train yourself to look at every concurrent statement and make sure that you don't see the output on both sides of the equation. It gets worse though because the 'latch' could be a function of multiple concurrent statements that happen to loop back. The synthesizer report that it finds a combinatorial loop works to catch that but nothing in the language prevents it (nor should it, since it may not be 'unintended'). > 2. If the above error is given an error, VHDL may include a special > statement to generate a latch. If you want a 'special' statement that creates a latch, then write one and instantiate it until your heart is content....but don't presume that everyone else agrees with you and that the language itself should only support your coding style for creating a latch and any other method should cause an error. > This is another big problem: I don't know how ASIC people generate a > real latch using VHDL? I think they may most likely use latch library > to generate special latch instead of using VHDL statements. That doesn't preclude them from inferring a latch in other ways. > I read an > article about asynchronous FIFO written by two engineers one of whom > is Pete Alfke of Xilinx (it is the best article I have read in my > life). In the paper they say that they fail to generate two or 3 > latches in their design using Xilinx chip. No idea what you mean by this...but reading on > If so, it seems to me that > there is no reliable statement in VHDL to generate a latch for a FPGA > chip. Unless the underlying hardware has a hard latch available as a resource to use and most (if not all) FPGAs do not, then I would agree that there is no reliable way to generate a latch inside an FPGA in any language, not just VHDL. The lack of latches in FPGAs though has nothing at all to do with VHDL or any language it is simply recognition by the FPGA suppliers that there is very little demand for a hard latch inside the FPGA. A flip flop would have the exact same coding issues, the only reason it's not a 'problem' is because there are hard flip flops inside the FPGA. The 'problem' with inferring any storage element (latch, flip flop, big hunk-o-memory, fifo, etc.) is when the underlying hardware doesn't directly support the inferred element and it needs to be cobbled together from basic logic blocks. In the FPGA/CPLD world, it is very difficult to meet internal setup, hold time and 'no glitching' requirements between two arbitrary signals. Remember also, that you can build ANY logical element strictly from NAND gates or NOR gates....so in theory you could write your code using only these two building blocks. Were you to do so and target an FPGA, it would most certainly fail if that design had any sort of storage. > > 3. If the example would generate a latch for signalA, how it is > generated? Same as any other logical description....it gets mapped to whatever internal resources exist in the device (LUTs, macrocells, flip flops, latches, whatever the target device supports). > > KJ answered the question. If the equation KJ suggested is true, it > would like the following: > if (state = stateA_S and a = "000001") then > signalA <= '1'; > end if; > > Finally I realized KJ saying is correct. > You're welcome. Kevin JenningsArticle: 116305
On Mar 6, 5:24 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > PatrickDuboiswrote: > > I am using some tidbits of VHDL-200x in my > > current design and xst produced a wrong netlist from that vhdl. > > Which bits? Not much. I'm just using the functions to convert from fixed-point to floating-point and vice-versa (functions to_signed, to_unsigned and to_float). I'm also doing some floating point math but I'm using the Coregen cores from Xilinx for doing that. PatrickArticle: 116306
Did you set your environment variables? set XIL_DCM_BUFG_CLKIN=3D1 Xilinx has all these stupid environment setting that they don't document well. 1=2E Right-click My Computer(Start Menu), and select Properties. 2=2E =E2=80=A8Click the Advanced tab. 3=2E Click Environment Variables, and add XIL_DCM_BUFG_CLKIN=3D1. Personally I place my DCM/IBUG/at the top level. I cant stand it when you get the par errors after waiting for hours. Cheers, BillArticle: 116307
On Mar 6, 5:37 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > news:1173203586.424949.18610@s48g2000cws.googlegroups.com... > > > Hi Kevin, > > In my first posting, there are 3 questions: > > 1. Why doesn't compiler generate an error for unintended latch > > generation? > > Simply put because it is not an 'error' to write code that infers a latch. > To presume that every latch is 'unintended' would be wrong. > > > This question is satisfactorily answered: there is a new attribute to > > give errors if an unintended latch is to generate. It says that some > > other people had already observed the situation long time ago. > > If you choose to use that attribute and find a tool that supports it then by > all means use it. But keep in mind that if you forget to use the new > attribute (because people are human) that you can still end up in the same > situation. It's up to you if that's the coding style you prefer to use to > avoid unintended latches, personally I prefer other coding styles but the > attribute is at least an improvement and gives another method which is good. > > No matter which of these two methods you use, you can still get an > 'unintended latch' with the following type of code which infers a latch > > Q <= (C and D) or (not(C) and Q); > > This is obviously a very stripped down example, a 'real' design might be > much more complicated, but you have to train yourself to look at every > concurrent statement and make sure that you don't see the output on both > sides of the equation. > > It gets worse though because the 'latch' could be a function of multiple > concurrent statements that happen to loop back. The synthesizer report that > it finds a combinatorial loop works to catch that but nothing in the > language prevents it (nor should it, since it may not be 'unintended'). > > > 2. If the above error is given an error, VHDL may include a special > > statement to generate a latch. > > If you want a 'special' statement that creates a latch, then write one and > instantiate it until your heart is content....but don't presume that > everyone else agrees with you and that the language itself should only > support your coding style for creating a latch and any other method should > cause an error. > > > This is another big problem: I don't know how ASIC people generate a > > real latch using VHDL? I think they may most likely use latch library > > to generate special latch instead of using VHDL statements. > > That doesn't preclude them from inferring a latch in other ways. > > > I read an > > article about asynchronous FIFO written by two engineers one of whom > > is Pete Alfke of Xilinx (it is the best article I have read in my > > life). In the paper they say that they fail to generate two or 3 > > latches in their design using Xilinx chip. > > No idea what you mean by this...but reading on > > > If so, it seems to me that > > there is no reliable statement in VHDL to generate a latch for a FPGA > > chip. > > Unless the underlying hardware has a hard latch available as a resource to > use and most (if not all) FPGAs do not, then I would agree that there is no > reliable way to generate a latch inside an FPGA in any language, not just > VHDL. The lack of latches in FPGAs though has nothing at all to do with > VHDL or any language it is simply recognition by the FPGA suppliers that > there is very little demand for a hard latch inside the FPGA. A flip flop > would have the exact same coding issues, the only reason it's not a > 'problem' is because there are hard flip flops inside the FPGA. > > The 'problem' with inferring any storage element (latch, flip flop, big > hunk-o-memory, fifo, etc.) is when the underlying hardware doesn't directly > support the inferred element and it needs to be cobbled together from basic > logic blocks. In the FPGA/CPLD world, it is very difficult to meet internal > setup, hold time and 'no glitching' requirements between two arbitrary > signals. > > Remember also, that you can build ANY logical element strictly from NAND > gates or NOR gates....so in theory you could write your code using only > these two building blocks. Were you to do so and target an FPGA, it would > most certainly fail if that design had any sort of storage. > > > > > 3. If the example would generate a latch for signalA, how it is > > generated? > > Same as any other logical description....it gets mapped to whatever internal > resources exist in the device (LUTs, macrocells, flip flops, latches, > whatever the target device supports). > > > > > KJ answered the question. If the equation KJ suggested is true, it > > would like the following: > > if (state = stateA_S and a = "000001") then > > signalA <= '1'; > > end if; > > > Finally I realized KJ saying is correct. > > You're welcome. > > Kevin Jennings Hi KJ, 1. Q <= (C and D) or (not(C) and Q); I have never seen such equation in my coding experiences and have no idea how this equation would be written. The logic result is beyond a reason. Could you please write it in equivalent latch equation in informal VHDL? 2. FPGA of Xilinx chip really has latch primative and one may use it using latch primative to call it. But it is hard to refer to it in VHDL. I don't mean VHDL should have included latch statement, what I mean is VHDL really lacks the statement element to refer to a latch in a clear and reliable way and the lack can be easily corrected. Thank you. WengArticle: 116308
Well you can do anything how about researching orthogonal processors FPGAs lend themselfs well to it. You could create your own machine architecture. Oh do what you like.Article: 116309
On Mar 6, 2:14 am, "wojt" <wojtek.bo...@gmail.com> wrote: > Hi guys > > I'm trying to synthesize processor core with ROM and RAM in the > VirtexE FPGA. > > I've created RAM memory using VirtexE Block RAM resources by means of > 'Single-Port Block Memory Core Generator' in Xilinx ISE. > > My problem is that VirtexE memory supports only 'Read-after-Write' > mode. In this mode, what has been written to the memory is transferred > on the active clock edge to the output port of the memory immediately > after assertion of 'Write Enable' input. > > I need to interface this memory to the processor which accepts all > values coming from the RAM, therefore 'No-Read-on-Write' mode, where > input data are not transferred to the output of the memory after > successful write, should be used. > > 'Read-after-Write' causes invalid values to be transferred to the > processor after each write to the RAM. > > Does anyone know how to overcome this problem? > > Thanks! > Wojt Hi Wojt, 1. 'Single-Port Block Memory' means the RAM block cannot do read and write at the same clock. If your design cannot guarantee this principle, your choosing single-port is wrong and you have to switch to dual-port block memory ram. 2. Whether single-port or dual-port block memory ram is used, you must design an interface between your processor and the block memory ram to guarantee that write and read work normally as you desire. 3. The most important thing you have to do now is to read Xilinx materials thoroughly and carefully and understand every technological details, otherwise you are doomed to a failure. 4. Xilinx block ram is very well designed and works excellent in my experiences with it. WengArticle: 116310
RaKa wrote: > Hello Everybody, > > I am looking for some interesting project ideas for a Masters Project. > An idea/project that can be implemented on a Xilinx/Altera board and > can be "seen" working. > > I would appreciate any suggestions, at the least they would give me a > direction to think in. How about this : Take the new Xilinx Spartan 3AN, and port the Lattice Mico32 open source SoftCPU to this, and implement a version that runs from on-chip flash ( ie fast serial memory access ) - Publish on the web. If you have spare time :) Add register frame support to the Mico32 (allows registers to map into on chip RAM), and also add a hardware threading system, that gives two iterleaved Mico32's. - Publish on the web. -jgArticle: 116311
On Mar 6, 7:28 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > On Mar 6, 2:14 am, "wojt" <wojtek.bo...@gmail.com> wrote: > >> Hi Wojt, > 1. 'Single-Port Block Memory' means the RAM block cannot do read and > write at the same clock. If your design cannot guarantee this > principle, your choosing single-port is wrong and you have to switch > to dual-port block memory ram. This is a wrong statement. Each port of the BlockRAM has independent write and read data lines. When data is being written into the port (WE active) then the data output has 3 choices: either reflect the data being written (write first) or reflect the previous content of the addressed location, before it was being overwritten (read first) or keep the output the way it was (no change) This describes Virtex-4 and Virtex-5 BRAM behavior. Older Virtex BRAMs do not have the read-first option. The other memory port has the same array of choices, since the two ports are independent, sharing only the stored data. Only when both ports happen to address the same location, is the timing somewhat demanding... Peter Alfke > >Article: 116312
Patrick Dubois wrote: >> If I had access to synplify, that would probably make my life sympler... >> but since I am between jobs right now and ASIC/FPGA-oriented shops in my >> area can probably be counted on two or three hands, it may be a while >> until I get an opportunity to update my 8.1 suite (ISE+EDK+ChipScope) >> for cheap/free... unless I decide to take one or two master classes to >> sneak into edu programs. > > If you ever needs some features/bug fix in a later ISE version (works > for xst only), there's one way to do it. You can download the webpack > for free and compile some piece of code with a target chip in the same > family but smaller that the full ISE Foundation allows. You can then > revert to your older full version to compile your top level and merge > every ngc together. Of course that only works for the xst part of the > flow, for the downstream tools you need to target your final (big) > chip AFAIK. I used this technique recently to benefit from some > improvement in xst v9.1 over xst v8.1. This sounds like something worth investigating next time I see XST choke on a bit of VHDL - thanks for the tip. An XC2VP7 is not exactly the most spacious FPGA around but still fits sizable chunks of logic. It would be nice if Xilinx extended WebPack to at least cover the specific chips featured on Xilinx's edu-minded, endorsed and subsidized boards like the XUP-V2P's XC2VP30-7/FF896 - that would make everybody who got XUPs (like me) really happy. > Good luck for your job search Daniel. If I recall correctly from your > signature, you're from Montreal right? Yup, Montreal, QC, congrats for remembering! Since there aren't too many digital logic or similar jobs around here compared to Ontario, I might start a short master here while looking and head out after that if I do not find anything worth staying around here for.Article: 116313
I setup a CDC test configuration using ILA in Chipscope Pro ver 8.1.03i. There is activity on bus and on data lines in the Analyzer but the system clock (BUFGP) of which the core is running is dead in the Analyzer window even though I added the system clock as data to be captured. I know the clock is there otherwise I would not be able to see data. I am surprized as why the clock is stuck low. I like to see clock on top just as in the conventional logic analyzer testsets for triggering and referencing data. There is a seperate tab for clock during setup, but wouldn't hurt adding it as data. Without a clock I am unable to fathom anything else. What's happening here? Best regards.Article: 116314
Weng Tianxiang wrote: > On Mar 6, 5:37 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: >> "Weng Tianxiang" <wtx...@gmail.com> wrote in message >> >> news:1173203586.424949.18610@s48g2000cws.googlegroups.com... >> >>> Hi Kevin, >>> In my first posting, there are 3 questions: >>> 1. Why doesn't compiler generate an error for unintended latch >>> generation? >> Simply put because it is not an 'error' to write code that infers a latch. >> To presume that every latch is 'unintended' would be wrong. >> >>> This question is satisfactorily answered: there is a new attribute to >>> give errors if an unintended latch is to generate. It says that some >>> other people had already observed the situation long time ago. >> If you choose to use that attribute and find a tool that supports it then by >> all means use it. But keep in mind that if you forget to use the new >> attribute (because people are human) that you can still end up in the same >> situation. It's up to you if that's the coding style you prefer to use to >> avoid unintended latches, personally I prefer other coding styles but the >> attribute is at least an improvement and gives another method which is good. >> >> No matter which of these two methods you use, you can still get an >> 'unintended latch' with the following type of code which infers a latch >> >> Q <= (C and D) or (not(C) and Q); >> >> This is obviously a very stripped down example, a 'real' design might be >> much more complicated, but you have to train yourself to look at every >> concurrent statement and make sure that you don't see the output on both >> sides of the equation. >> >> It gets worse though because the 'latch' could be a function of multiple >> concurrent statements that happen to loop back. The synthesizer report that >> it finds a combinatorial loop works to catch that but nothing in the >> language prevents it (nor should it, since it may not be 'unintended'). >> >>> 2. If the above error is given an error, VHDL may include a special >>> statement to generate a latch. >> If you want a 'special' statement that creates a latch, then write one and >> instantiate it until your heart is content....but don't presume that >> everyone else agrees with you and that the language itself should only >> support your coding style for creating a latch and any other method should >> cause an error. >> >>> This is another big problem: I don't know how ASIC people generate a >>> real latch using VHDL? I think they may most likely use latch library >>> to generate special latch instead of using VHDL statements. >> That doesn't preclude them from inferring a latch in other ways. >> >>> I read an >>> article about asynchronous FIFO written by two engineers one of whom >>> is Pete Alfke of Xilinx (it is the best article I have read in my >>> life). In the paper they say that they fail to generate two or 3 >>> latches in their design using Xilinx chip. >> No idea what you mean by this...but reading on >> >>> If so, it seems to me that >>> there is no reliable statement in VHDL to generate a latch for a FPGA >>> chip. >> Unless the underlying hardware has a hard latch available as a resource to >> use and most (if not all) FPGAs do not, then I would agree that there is no >> reliable way to generate a latch inside an FPGA in any language, not just >> VHDL. The lack of latches in FPGAs though has nothing at all to do with >> VHDL or any language it is simply recognition by the FPGA suppliers that >> there is very little demand for a hard latch inside the FPGA. A flip flop >> would have the exact same coding issues, the only reason it's not a >> 'problem' is because there are hard flip flops inside the FPGA. >> >> The 'problem' with inferring any storage element (latch, flip flop, big >> hunk-o-memory, fifo, etc.) is when the underlying hardware doesn't directly >> support the inferred element and it needs to be cobbled together from basic >> logic blocks. In the FPGA/CPLD world, it is very difficult to meet internal >> setup, hold time and 'no glitching' requirements between two arbitrary >> signals. >> >> Remember also, that you can build ANY logical element strictly from NAND >> gates or NOR gates....so in theory you could write your code using only >> these two building blocks. Were you to do so and target an FPGA, it would >> most certainly fail if that design had any sort of storage. >> >> >> >>> 3. If the example would generate a latch for signalA, how it is >>> generated? >> Same as any other logical description....it gets mapped to whatever internal >> resources exist in the device (LUTs, macrocells, flip flops, latches, >> whatever the target device supports). >> >> >> >>> KJ answered the question. If the equation KJ suggested is true, it >>> would like the following: >>> if (state = stateA_S and a = "000001") then >>> signalA <= '1'; >>> end if; >>> Finally I realized KJ saying is correct. >> You're welcome. >> >> Kevin Jennings > > Hi KJ, > 1. Q <= (C and D) or (not(C) and Q); > I have never seen such equation in my coding experiences and have no > idea how this equation would be written. The logic result is beyond a > reason. Could you please write it in equivalent latch equation in > informal VHDL? That equation is written exactly as-is and would work in theory. Glitches on Q while C goes from 1 to 0 may break the feedback loop or make it metastable in practice. Another VHDL way of putting it would be: Q <= D when C = '1' else Q; An equivalent VHDL process would be: process(c,d) begin if(c='1') then q <= d; end if; end process; Exactly what each of these would actually infer is tool- and hardware-specific. The only thing you can do is check your synthesis reports to determine exactly what was synthesized. This applies to all matters of getting HDL to map onto specific FPGA resources. > 2. FPGA of Xilinx chip really has latch primative and one may use it > using latch primative to call it. But it is hard to refer to it in > VHDL. I don't mean VHDL should have included latch statement, what I > mean is VHDL really lacks the statement element to refer to a latch in > a clear and reliable way and the lack can be easily corrected. Latches: "if somesig='1' then ... end if;" Latches(2): see equations and process above FFs: "if clk='1' and clk'event then ... end if;" FFs(2): "if rising_edge(clk) then ... end if;" That seems like plenty straight-forward VHDL to me. Latches are active on levels, FFs are active on edges. Simple. Xilinx devices do not have dedicated latches BUT they do allow you to program a slice FF to bypass HALF of it so it can be used as a latch. As far as power is concerned though, the whole FF is still connected to the clock so you most likely won't be saving any power here. BTW, the configuration logic that goes behind FPGA FFs uses more surface area than the FF itself and the "latch bypass logic" probably uses nearly as much power as a pure FF. To reach high clock speeds, FPGAs and ASICs need their pipeline storage elements to be able to forward values from D to Q with as little setup, hold and settling time as possible to maximize timing margins between clock edges. This is most effortlessly and reliably achieved with FFs, hence the dominance of FFs in the world of high-speed digital systems and the FF-oriented nature of FPGAs even though they cost a little more surface area and power. Simply put, FFs are the path of least unnecessary pain. If you want lower power FPGAs, some flexibility has to be sacrificed. If Xilinx stripped the latch option from slice FFs, it would reduce the slice FF cells' power and size by 15-20% while making them a little bit faster. I wonder how many would have a problem with this.Article: 116315
It is simply superb On Mar 6, 4:22 pm, "chipdesignart" <chipdesign...@gmail.com> wrote: > Hi Designers, > > The website dedicated for we(VLSI Chip designer's discussing about > trade-off's /problems solutions/ FAQ's)... > vlsi.chip.googlepages.com > > I found a very good website for VLSI Chip design, which has columns > for all the implementation challenges, ASIC FAQ's more relevant to > designers, VLSI Design flows, Design checklists, good lectures/courses/ > white-papers.... > > vlsi.chip.googlepages.com > > check this site out.... more over the Implementation challenges column/ > FAQ's will be very helpful and knowledgeable .... > > Digitally Your'sArticle: 116316
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> writes: > I use Makefile most of time. A return value of non-zero will cause > make to exit unless I put some checking into my Makefile. Your > suggestion solves one problem, but creates another. Grepping timing > score from the par report is pretty easy, so why bother to change the > behavior of the tool, which would make "make" users unhappy. > It will make new users happy. They expect an error to be an error, surely? Anyway, I think we'll end up with a command-line switch to keep us all happy! Actually we'll probably end up with that typical Xilinx solution of an environment variable kludge.. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116317
"Patrick Dubois" <prdubois@gmail.com> writes: >> Why do you dislike make? >> >> Personally, I just use a series of batch files... >> >> Cheers, >> Martin > > I don't like make mainly because of its obscure "language" and because > I found it very hard to debug a makefile. Granted, I'm no expert on > makefiles and that might be why I have trouble with it but others > seems to agree: > http://freshmeat.net/articles/view/1702/ > Fair enough. > Now the reason I'm looking for something more powerful than batch > files is because my project is modular. I compile most modules (10 at > the moment) into its own separate ngc file that I combine together > later in the flow. Compiling all these modules each time takes too > much time (which is why I separated them in the first place). > Ahh, yes I can see that being a problem! In that case, SCons looks like it could be a good route, it certainly looks a lot more flexible than make, but it may have a bigger learning curve (!) > Right now I just keep track mentally of which file I changed and > rebuild the corresponding module manually (by launching its batch > file). I would prefer a tool that keep tracks of file changes > automatically and rebuilds only the modules that are necessary, which > is what Make or SCons could do for me. > What source language are you using? I can see that it might be tricky to teach SCons how to deal with VHDL, given that entities and archs are unrealted by name to the file they exist in. Finding C dependencies by header file name is a little easier! But Make will be no easier! If using VHDL, maybe you could create a Compiler target for Emacs' vhdl-mode that runs XST (for example) instead of Modelsim's vcom etc. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116318
sweir@x2y.com writes: > Symon, you are welcome. An out of office junk filter is mandatory for > SI-List sanity. > I use gmane.org to lurk on SI-List - it allows you to use a proper newsreader, which makes life a lot nicer... -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116319
"RaKa" <rakesh.hemnani@gmail.com> wrote in message news:1173072195.301402.132460@30g2000cwc.googlegroups.com... > Hello Everybody, > > I am looking for some interesting project ideas for a Masters Project. > An idea/project that can be implemented on a Xilinx/Altera board and > can be "seen" working. > > I would appreciate any suggestions, at the least they would give me a > direction to think in. > I understand the must be seen working aspect of any project especially when you have to demonstrate it to non-FPGA knowledgeable supervisors/externals. However, don't forget that a future employer might ask you some different questions on your project. He might for example put more value on how you validated your code, ask you if you eyeballed some waveforms or did you write a proper selfchecking testbench, did you use any properties/assertions in your code, how did you derive the architecture, did you write any webpage/documentation/user guide, is your code commented/readable/maintainable, did you write any synthesis constraints, how did you handle async inputs, false/multi-cycle path etc etc. So for these reason I would select a smallish project something that you can implement in about 50% of your available time and then spend the other 50% on trying to answer/implement/study some of the above issues. Now for the visual aspect you could drive a monitor and do some image processing as mentioned by others however this might complicate your selfchecking testbench, so I would focus on something like a forward error correction code, or some communication protocol. You can use 2 UARTs (USB2serial cables are cheap and seem to work OK) to show the input and output datastreams. You can then use some switches to introduce errors/show error recovery/different scenarios etc. Just a thought, Hans www.ht-lab.comArticle: 116320
On 6 Mar 2007 23:49:43 -0800, "Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote: >I setup a CDC test configuration using ILA in Chipscope Pro ver >8.1.03i. There is activity on bus and on data lines in the Analyzer >but the system clock (BUFGP) of which the core is running is dead in >the Analyzer window even though I added the system clock as data to be >captured. > >I know the clock is there otherwise I would not be able to see data. I >am surprized as why the clock is stuck low. I like to see clock on top >just as in the conventional logic analyzer testsets for triggering and >referencing data. There is a seperate tab for clock during setup, but >wouldn't hurt adding it as data. Without a clock I am unable to >fathom anything else. > >What's happening here? > >Best regards. Clock should be connected to clock input. And if you *also* connect it to data, you will only see a constant value. Why? because sampling clock on the rising edge of itself, will always yield the same level. ZaraArticle: 116321
I sometimes connet the clockdv output (clock/2) of the clocks dcm to a data port. This is very helpful for debuging purpose.Article: 116322
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1173237015.878201.302510@p10g2000cwp.googlegroups.com... > 1. Q <= (C and D) or (not(C) and Q); > I have never seen such equation in my coding experiences and have no > idea how this equation would be written. The logic result is beyond a > reason. Could you please write it in equivalent latch equation in > informal VHDL? It's the same old transparent latch that we've been talking about all along. The following forms are exactly equivalent logic and will result in the exact same synthesized result. #1 -- Traditional form of writing a latch process(C, D) begin if (C='1') then Q <= D; end if; end process; #2 -- Another traditional form of writing a latch. Q <= D when (C = '1'); #3 -- Latch equations written as a sum of products Q <= (C and D) or (not(C) and Q); #4 -- Latch equation written in a sum of products form that includes a 'cover' term Q <= (C and D) or (not(C) and Q) or (D and Q); Try all four of the above out and run them through synthesis and you should get the exact same fitted equations for all 4. Of the four different forms, only #4 is written in a way that will not have timing issues that are caused simply by the implementation (over which you have no real control in an FPGA). However, the last term ".. or (D and Q)" is redundant and any synthesizer worth a dime will 'optomize the logic' and implement it as form #3. This 'optomization' though creates a logic hazard when 'C' switches from '1' to '0'. This logic hazard will in turn show up as a failure in the latch operation. Specifically, what you'll run into is that even if you have 'D' set up oodles of time before 'C' switches from '1' to '0', the output 'Q' can latch itself at either '1' or '0' (depending on the targetted part) because of differences in prop delay in computing the first two or terms or glitches in 'C'. That last "D and Q" term is absolutely required in order to even have a shot at inferring a latch that will actually work but since it is logically 'redundant' it will always get optomized away. If you hark back to Boolean Logic 101, you may recall that adding redundant terms is the method you employ to get rid of logic hazards. The FPGA LUT implementation leaves even more to the imagination as you wonder just what those RAM outputs are doing with this combinatorial loop and whether 'Q' will glitch and cause even more havoc since it would feed back to the address input of the LUT. The bottom line is - There are various forms of writing source code that infers a latch. - Whether a latch is a 'good' thing or a 'bad' thing depends on the targetted device itself and whether that device actually has a hard latch and a way to guarantee the timing and glitch requirements of 'D' and 'C'. - Inferring any storage element (flops, latches, memory) needs to be done in such a way that the storage is not implemented as a collection of LUTs/macrocells but instead uses hard storage resources of the device. > > 2. FPGA of Xilinx chip really has latch primative and one may use it > using latch primative to call it. But it is hard to refer to it in > VHDL. You'll still have trouble meeting and guaranteeing the timing and glitch requirements on 'D' relative to 'C' in order to get it to work correctly for arbitrary signals 'D' and 'C'. If it does work, it likely won't scale well (i.e. if you try to infer thousands of these as you would like to) > I don't mean VHDL should have included latch statement, what I > mean is VHDL really lacks the statement element to refer to a latch in > a clear and reliable way and the lack can be easily corrected. > I've shown above four different forms for inferring the exact same latch (i.e. synthesizes to the exact same thing). Which form you prefer (or if you prefer to make up your own) to use is up to you. Making up a new method though will not prohibit the earlier forms from being used and outlawing the other forms gets in the way of people who do use latches and are doing so in a way that they can control the various issues so you're not helping them by outlawing their method. Kevin JenningsArticle: 116323
Hi everyone, I would to interface a CMOS image sensor to my FPGA. I'm looking for low-end sensor and a matching lens. Nothing fancy or several mega pixels - just the bare minimum. Do any of you have a few links to vendors or distributors? It doesn't seem to be an "off the shelf" product. Thank you very much. Regards - SteinArticle: 116324
On 6 Mar, 07:22, "chipdesignart" <chipdesign...@gmail.com> wrote: > Hi Designers, > > The website dedicated for we(VLSI Chip designer's discussing about > trade-off's /problems solutions/ FAQ's)... > vlsi.chip.googlepages.com > > I found a very good website for VLSI Chip design, which has columns > for all the implementation challenges, ASIC FAQ's more relevant to > designers, VLSI Design flows, Design checklists, good lectures/courses/ > white-papers.... > > vlsi.chip.googlepages.com > > check this site out.... more over the Implementation challenges column/ > FAQ's will be very helpful and knowledgeable .... > > Digitally Your's Is that your website?
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