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On 29 Jul 2004 06:31:30 -0700, linical@yahoo.com (linical) wrote: > how can FPGA tossing give me random number with normal distribution? sheesh, haven't you heard of the Central Limit Theorem? :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 71751
Hi newsgroup people,
maybe someone can help me with regard to the following problem:
I am using an Altera Cyclone Device EP1C12F256C7.
When I program it via JTAG (I am not able to program it via Serial Configuration
Device yet) the PLL I instantiated in the MegaWizard does run if the PLL
does not have a reset input.
I have programmed a little design, some counters which are resetted.
It doesn't matter whether the counters are resetted or not I cannot see
anything going on at the debug pins of my FPGA.
So the question is what goes wrong.
I mean if it was a basic problem the PLL would not run.
If it was exclusevely an reset problem the counters WITHOUT reset would run
but they do not!
I have a watchdog which produces an asynchronous reset but then it does
not get the trigger signal out of the FPGA so that the watchdog resets
periodically. The trigger signal I generate in the FPGA is depedent on
the counters which are NOT resettet.
Here is some piece of my trigger generation:
signal l_count : integer range 0 to 15;
signal l_trigger_watchdog : std_logic;
Trigger_watchdog <= l_trigger_watchdog;
--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_count <= 0;
if rising_edge(Clk_30) then
l_count <= l_count;
if l_count=15 then
l_count <= 0;
else
l_count <= l_count + 1;
end if;
end if;
end process;
--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_trigger_watchdog <= '0';
if rising_edge(Clk_30) then
l_trigger_watchdog <= l_trigger_watchdog;
if l_count=0 then
l_trigger_watchdog <= not l_trigger_watchdog;
end if;
end if;
end process;
--------------------------------------------
--------------------------------------------
Maybe someone has experienced such similar problems.
Thank you for your help.
Kind regards
André V.
Article: 71752Yes, VHDL is all about "syntactic sugar". VHDL uses strong typing which means you can only use a signal as its declared type, the tool will not "figure out" what you mean, you *must* tell it explicitly. If you want a tool that will make assumptions, you should be using Verilog. To convert to an integer, you first must convert to a signed or unsigned type and then to an integer... registers(TO_INTEGER(UNSIGNED(address))) <= one_32bits_regs; To use these functions you should use the ieee.numeric_std library. Do you know how to add a library to your code? Use ieee.numeric_std.all; As to what you are trying to do, do you really need all 64 32-bit registers accessable at the same time? That is 2,048 FFs! Sylvain Munaut wrote: > > I don't read need the address at output, it's read from fpga pins ( I know, here I put it as signal but it's a in port in my design ). > How would I convert it to integer ? does that involves logic or it's just synctatic sugar ? > > Sylvain > > Manfred Balik wrote: > > You can't use a std_logic_vector as index - use an integer. > > If you need the address as output you have to convert it. > > Manfred > > > > "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> schrieb im > > Newsbeitrag news:4108e760$0$31480$ba620e4c@news.skynet.be... > > > >>Hello > >> > >>I'm wondering how configurations registers are usually implemented. By > > > > this I mean I have in my design value I want to be run-time configurable. So > > each of this value is read (and read only), and on the other side, there is > > an address / data / strobe bus. So that a controller can read/write a > > register given it's adress. > > > >>I'm looking for a space efficent way. I don't think I can use memory > > > > blocks for this since they are all read in // ... > > > >>What I've come up with so far is > >> > >>type reg_space is array (integer range <>) of std_logic_vector(31 downto > > > > 0); > > > >>signal registers : reg_space(63 downto 0); > >>signal address : std_logic_vector(5 downto 0); > >> > >> > >>Then to write a value in a process : > >> > >>registers(address) <= one_32bits_regs; > >> > >> > >>But that last statment is incorrect ... He doesn't wan address to index > > > > registers. > > > >> > >> > >>Sylvain > > > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71753
solosynergy@gmail.com (krishna) wrote in message news:<122eeb59.0407282304.782f2276@posting.google.com>... > is it possible to connect two entities with instantiating them as components. Why do you want to do that? Can you explain your intention?Article: 71754
ALuPin wrote: > > Hi newsgroup people, > > maybe someone can help me with regard to the following problem: > > I am using an Altera Cyclone Device EP1C12F256C7. > > When I program it via JTAG (I am not able to program it via Serial Configuration > Device yet) the PLL I instantiated in the MegaWizard does run if the PLL > does not have a reset input. > > I have programmed a little design, some counters which are resetted. > It doesn't matter whether the counters are resetted or not I cannot see > anything going on at the debug pins of my FPGA. > > So the question is what goes wrong. > > I mean if it was a basic problem the PLL would not run. > If it was exclusevely an reset problem the counters WITHOUT reset would run > but they do not! > > I have a watchdog which produces an asynchronous reset but then it does > not get the trigger signal out of the FPGA so that the watchdog resets > periodically. The trigger signal I generate in the FPGA is depedent on > the counters which are NOT resettet. > > Here is some piece of my trigger generation: > > signal l_count : integer range 0 to 15; > signal l_trigger_watchdog : std_logic; > > Trigger_watchdog <= l_trigger_watchdog; > > -------------------------------------------- > -------------------------------------------- > process(Clk_30) > begin > --if Reset='1' then > -- l_count <= 0; > > if rising_edge(Clk_30) then > l_count <= l_count; > > if l_count=15 then > l_count <= 0; > else > l_count <= l_count + 1; > end if; > > end if; > end process; > -------------------------------------------- > -------------------------------------------- > process(Clk_30) > begin > --if Reset='1' then > -- l_trigger_watchdog <= '0'; > > if rising_edge(Clk_30) then > l_trigger_watchdog <= l_trigger_watchdog; > > if l_count=0 then > l_trigger_watchdog <= not l_trigger_watchdog; > end if; > > end if; > end process; > -------------------------------------------- > -------------------------------------------- This code should work as far as I can tell. The statements where you assign the count and trigger to themselves are not needed. I think you may have included them for concern about generating latches if all cases are not covered. But this only applies to combinatorial logic. You are trying to infer sequential logic and so it is ok to have undefined cases. The default is that the values are held if the conditions are not defined (such as the else in the l_count=0 test). I suggest that you bring out all the signals to pins, including the clock. Then probe it all with a scope to see if anything is working. Also make sure that the pins you want are really being used. If nothing seems to work, check back to the synthesis equations to make sure your design is not being optimized away. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71755
does anyone know if there exists a pci-X open core (for 33/66/133 Mhz pci bus transfer rates) that will fit on a spartan-II fpga (or maybe even on the V2P if necessary). I am working with a virtex-II pro dev board and we like to reprogram the pci bus controller chip (which is a spartan 2), such that the i/o was much faster. If anyone can point me in the right direction, that would be most helpful. thanks -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science (will be updated soon) http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 71756
rickman wrote: > Yes, VHDL is all about "syntactic sugar". VHDL uses strong typing which > means you can only use a signal as its declared type, the tool will not > "figure out" what you mean, you *must* tell it explicitly. If you want > a tool that will make assumptions, you should be using Verilog. > > To convert to an integer, you first must convert to a signed or unsigned > type and then to an integer... > > registers(TO_INTEGER(UNSIGNED(address))) <= one_32bits_regs; Thanks that's what I missed ... I tried with only to_integer ( or conv_integer ) but haven't tried with unsigned before. > To use these functions you should use the ieee.numeric_std library. Do > you know how to add a library to your code? > > Use ieee.numeric_std.all; > > As to what you are trying to do, do you really need all 64 32-bit > registers accessable at the same time? That is 2,048 FFs! Yes, that's a lot of FFs. Hopefully the numbers were just picked up randomly. I need something like 10 8 bits registers, for values that are continuously needed. They other configurations options in my design are stored in dual port distributed ram. Sylvain MunautArticle: 71757
Bart, Allan, I've had this problem with odd length carry chains in adders as well. Adding two 20 bit numbers gave me a 21 bit result, but the top carry bit went 'bad'. Looking back at my code, I fixed it by adding a dummy signal set to '0' on the end of the input numbers with the syn_keep attribute, i.e. so it now gives a 21 bit result from two 21 bit inputs. (I should add I used Synplify for synthesis.) cheers, Syms. "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:beohg05lpj8mic8tplb4mhdvji0shbge2i@4ax.com... > On 29 Jul 2004 04:20:49 -0700, zeeman_be@yahoo.com (Bart De Zwaef) > wrote: > > Hi Bart, > > I have observed exactly the same symptoms, but with another > synthesiser (Synplify Pro). I think the problem is with MAP rather > than the synthesiser. MAP doesn't seem to handle the last bit in an > odd length carry chain well. > > My solution (as usual) was to create a module that instantiated the > unisim components directly (with RLOC attributes), so that I got > exactly what I wanted. > > BTW, this bug has been around for at least three years. At the time, > I was having a lot of trouble implementing a 17 and 33 bit adders. I > came to the conclusion that Xilinx's test suite probably only has even > length adders. > > Regards, > Allan.Article: 71758
If you are using it for University teaching/research, contact the Xilinx University Program (XUP) at http://www.xilinx.com/univ/ and they should be able to arrange a donation of the cores you need. Paul Geoffrey Wall wrote: > > does anyone know if there exists a pci-X open core (for 33/66/133 Mhz pci > bus transfer rates) that will fit on a spartan-II fpga (or maybe even on the > V2P if necessary). I am working with a virtex-II pro dev board and we like > to reprogram the pci bus controller chip (which is a spartan 2), such that > the i/o was much faster. If anyone can point me in the right direction, that > would be most helpful. > > thanks > > -- > Geoffrey Wall > Masters Student in Electrical/Computer Engineering > Florida State University, FAMU/FSU College of Engineering > wallge@eng.fsu.edu > Cell Phone: > 850.339.4157 > > ECE Machine Intelligence Lab > http://www.eng.fsu.edu/mil > MIL Office Phone: > 850.410.6145 > > Center for Applied Vision and Imaging Science (will be updated soon) > http://cavis.fsu.edu/ > CAVIS Office Phone: > 850.645.2257Article: 71759
I've grabbed the information in spreadsheet form by going here: http://www.xilinx.com/applications/web_ds_sp2e/pin_comp/ and comparing the device I need against itself. It's just a matter of deleting a few columns from there. There may be an easier source, but this one is handy. - John_H "Krishna Kumar" <krishk24@gmail.com> wrote in message news:e23e0547.0407281442.58c03b23@posting.google.com... > Hello > Does anybody know where to find the Spartan2E FG456 package file. I > need this file for creating a schematic part symbol. As an example for > a package file I was able to find for virtex 2 in the link > > http://www.xilinx.com/products/virtex/v2packages.htm > > Please let me know. > > thanks > Krishna KumarArticle: 71760
Hi, I am working on a project which involve ALTERA Cyclone Parts. The configuration device for this part is called EPCS1 or EPCS4 ALTERA supplies a SRUNNER software that is very poorly documented. I am specifically looking for the file format of input file to this SRUNNER code. The file is obtained by converting a *.pof file to a *.rpd file. The detailed layout of this file, hover is missing from all doc I have been looking at Any info on such would be greatly appreciated Regards Ephraim SchoenfeldArticle: 71761
Actually, what you are describing is a VHDL coding issue, not a MAP issue. If you want a 21 bit result from a VHDL add (I don't know Verilog well enough to say) you have to have at least one 21 bit input. VHDL won't assume that you expect a 21 bit result. Symon wrote: > > Bart, Allan, > I've had this problem with odd length carry chains in adders as well. Adding > two 20 bit numbers gave me a 21 bit result, but the top carry bit went > 'bad'. Looking back at my code, I fixed it by adding a dummy signal set to > '0' on the end of the input numbers with the syn_keep attribute, i.e. so it > now gives a 21 bit result from two 21 bit inputs. (I should add I used > Synplify for synthesis.) > cheers, Syms. > "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in > message news:beohg05lpj8mic8tplb4mhdvji0shbge2i@4ax.com... > > On 29 Jul 2004 04:20:49 -0700, zeeman_be@yahoo.com (Bart De Zwaef) > > wrote: > > > > Hi Bart, > > > > I have observed exactly the same symptoms, but with another > > synthesiser (Synplify Pro). I think the problem is with MAP rather > > than the synthesiser. MAP doesn't seem to handle the last bit in an > > odd length carry chain well. > > > > My solution (as usual) was to create a module that instantiated the > > unisim components directly (with RLOC attributes), so that I got > > exactly what I wanted. > > > > BTW, this bug has been around for at least three years. At the time, > > I was having a lot of trouble implementing a 17 and 33 bit adders. I > > came to the conclusion that Xilinx's test suite probably only has even > > length adders. > > > > Regards, > > Allan. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71762
One quick way to generate package files is to use the "partgen" utility that
comes with the Xilinx tools.
For example, to generate all the package files for the XC2S200E, enter the
following command in a DOS box or console window.
partgen -v 2s200e
You should see multiple *.pkg files in the current directory.
After the first line, all the fields are fixed width columns.
--
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC
"Krishna Kumar" <krishk24@gmail.com> wrote in message
news:e23e0547.0407281442.58c03b23@posting.google.com...
> Hello
> Does anybody know where to find the Spartan2E FG456 package file. I
> need this file for creating a schematic part symbol. As an example for
> a package file I was able to find for virtex 2 in the link
>
> http://www.xilinx.com/products/virtex/v2packages.htm
>
> Please let me know.
>
> thanks
> Krishna Kumar
Article: 71763Hi Rick, This was a while ago, so take this with a pinch of salt, but, thinking back, when I padded the input vectors with '0' to make everything 21 bits, the carry went 'bad'. I replaced the '0' with a kept dummy signal set to '0', which gave 'good' carry! As I said, that was many beers ago, so I may've recalled incorrectly. Cheers, Syms. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:41093DB5.C924297E@yahoo.com... > Actually, what you are describing is a VHDL coding issue, not a MAP > issue. If you want a 21 bit result from a VHDL add (I don't know > Verilog well enough to say) you have to have at least one 21 bit input. > VHDL won't assume that you expect a 21 bit result. > > Symon wrote: > > > > Bart, Allan, > > I've had this problem with odd length carry chains in adders as well. Adding > > two 20 bit numbers gave me a 21 bit result, but the top carry bit went > > 'bad'. Looking back at my code, I fixed it by adding a dummy signal set to > > '0' on the end of the input numbers with the syn_keep attribute, i.e. so it > > now gives a 21 bit result from two 21 bit inputs. (I should add I used > > Synplify for synthesis.) > > cheers, Syms.Article: 71764
Hi, In this thread: http://groups.google.com/groups?threadm=BC8772E1.5C19%25peter%40xilinx.com Peter A. suggested that a Xilinx Virtex2Pro MGT can be used as a high speed sampler. This requires disabling the CDR in the MGT, so that the receive clock is controlled solely by the reference frequency. UG024 says: "A... feature of CDR is its ability to accept an external precision clock, REFCLK, which ... acts to clock incoming data..." I can't work out how to get it to do that, so that it doesn't start using the CDR when the input data has transitions. Presumably there's an undocumented attribute that can turn the CDR off, but I didn't see one in FPGA editor. Any ideas? BTW, I don't actually want to build something using this right now. Regards, Allan.Article: 71765
On Thu, 29 Jul 2004 14:11:01 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Actually, what you are describing is a VHDL coding issue, not a MAP >issue. If you want a 21 bit result from a VHDL add (I don't know >Verilog well enough to say) you have to have at least one 21 bit input. >VHDL won't assume that you expect a 21 bit result. Rick, it was a timing issue due to poor mapping, rather than a functional issue. Regards, Allan.Article: 71766
Hi Jay, I was looking to purchase the Spartan-3 dev-board. I understand it comes with modelsim, is modelsim registered as a "time limited" product or "code size" ? thanks atts jaypt@hotmail.com wrote: > After I place/route the design and generate the *.bit file > how can I download the *.bit file into Spartan-3. Which program > should I use. I just bought the Spartan-3 starter kit from Xilinx > and there is no instruction on how to bring the bitstream from > my PC into the development board. What cable should I use to > connect the PC to the development board. Is there any Web which > explains in details about this process. The documentation which > comes with the kit does not explain how to do this. > > Thanks, > > JayArticle: 71767
Never heard of. Jonathan Bromley <jonathan.bromley@doulos.com> wrote in message news:<jlvhg0dfn6v8veloup19e0s24mfnmoet1p@4ax.com>... > On 29 Jul 2004 06:31:30 -0700, linical@yahoo.com (linical) wrote: > > > how can FPGA tossing give me random number with normal distribution? > > sheesh, haven't you heard of the Central Limit Theorem? > :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 71768
"buke2" <cubah@tlen.pl> wrote in news:ce7m97$16g$1@nemesis.news.tpi.pl: > Hello all, > anybody knows how can I extract equations from Xilinx schematic? > I tried in Schematic Editor: Option->ExportNetlist and VHD file has > been generated...but to get clear equations (Out=f(In)) I must > translate whole of file... > > Maybe somhere is tool for extracting euations from VHDL file? I know that the report file for a Xilinx CPLD lists the Boolean equations for the various outputs. If you don't have any FPGA-specific macros in your design, then you might be able to retarget for a CPLD just to get the equations. -- ---------------------------------------------------------------- Dr. Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 71769
Heard of Google? http://www.stat.sc.edu/~west/javahtml/CLT.html "linical" <linical@yahoo.com> wrote in message news:885ef3e9.0407291055.7913f75f@posting.google.com... > Never heard of. > > Jonathan Bromley <jonathan.bromley@doulos.com> wrote in message news:<jlvhg0dfn6v8veloup19e0s24mfnmoet1p@4ax.com>... > > On 29 Jul 2004 06:31:30 -0700, linical@yahoo.com (linical) wrote: > > > > > how can FPGA tossing give me random number with normal distribution? > > > > sheesh, haven't you heard of the Central Limit Theorem? > > :-)Article: 71770
Allan Herriman wrote: > > On Thu, 29 Jul 2004 14:11:01 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Actually, what you are describing is a VHDL coding issue, not a MAP > >issue. If you want a 21 bit result from a VHDL add (I don't know > >Verilog well enough to say) you have to have at least one 21 bit input. > >VHDL won't assume that you expect a 21 bit result. > > Rick, it was a timing issue due to poor mapping, rather than a > functional issue. That would be the problem the OP had. But the problem Symon described is a coding issue. But then he replied to my post and I may not have understood what he meant. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71771
Yeah, sorry Rick, I should clarify that when I said 'bad' I meant from a timing point of view, not logic. I find that the tools rarely, if ever, make logical errors these days. Maybe I'm just lucky? ;-) cheers, Syms. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:41095A10.6B315BF7@yahoo.com... > > That would be the problem the OP had. But the problem Symon described > is a coding issue. But then he replied to my post and I may not have > understood what he meant.Article: 71772
njoroge@stanford.edu (Nju Njoroge) writes:
>I have been using the Riscwatch box w/ RISCwatch ver. 5.1 software. I
>am running Linux on our embedded PPC405D. The trace captures the
...
>How can configure RISCwatch to access those interrupt address
>locations that need physical address? Anyone encountered this problem
>and found a way around it? I e-mailed IBM about it, but haven't gotten
>a response yet...
The most common solution to this problem is to use an Abatron BDI2000
instead...
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Web: www.denx.de
"More software projects have gone awry for lack of calendar time than
for all other causes combined."
- Fred Brooks, Jr., _The Mythical Man Month_
Article: 71773Lets take an example and see what the concensus is: Gate Count: 40K ASIC gates Speed: 50 MHz PinOut: 100 pins Other: ??? One Configuration: Spartan-III would be a suitable fit with $20 price tag (scaling to $10 with volume) + $3 prom. Altenatives from Altera? Actel (may be anti fuse?) Could some one fill in... -RajeevArticle: 71774
Hello, against the background of partial reconfiguration, I would like to determine the difference between two initial configurations (NCDs). Does any Xilinx tool support this? Regards, -- Dr. Thomas Reinemann www.uni-magdeburg.de/reineman IMAT Public key available Otto-von-Guericke-Universit=E4t Magdeburg Universit=E4tsplatz 2 39106 Magdeburg, Germany
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