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Eirik Seljelid wrote: > Hi. > > I have an old ABEL source code (no JEDECīs) for an 82S100/PLS100 FPLA. > Problem is that I can't find any company supporting ABEL compilers for > these chips anymore. That's because no one makes the chips anymore..... That said, I see you CAN still actually buy the PLS100, and I also see my PLD programmer still shows a PLS100 on the menu... > Xilinx, which aquired Synario/ABEL from Dataio, > does only support it's own families of FPGAS/CPLDS. ABEL support for > small PLDS has been taken over by Lattice also supporting only their own > PLD families. Anyone know if Xilinx released legacy ABEL compilers as > freeware, opensource or similar? Nope - Xilinx's response will be to tell you to take your ABEL source, and recompile for a CoolRunner CPLD. ( but that does not retrofit too easily into a PLS100 socket.) The Xilinx ABEL has a certain amount of inbuilt ability, and it looks like, if you really want to, you can get PLA and BLIF files from the current Xilinx ABEL flows. What you then need is the relevent Signetics PLS100 fitter, or you could look for the Signetics software - IIRC their SW called Amaze supported the PLS100, and it had a successor called SLICE, but both are ancient. Or, you could look for a device similar to the PLS100, but still in production, such as the ICT PA7536 or PA7540 ? ICT offer current software to support these devices. See http://www.anachip.com/eng/product/pld.php The 22V10 is still quite active (Atmel, ICT, Lattice), but has fewer total pins than a PLS100. -jgArticle: 72076
What about implementing an hitachi h8 mcu in an fpga? And attach exactly the same external components as in the rcx itself? then you have a "custom" rcx that you can add advanced hardware into. You can create a second microcontroller,statemachine whatever with a number of io/s and you can create som sort of software using the IR send / recv command in the h8 to do communication with second mcu? So that the ir port of the h8 is mapped to both IR and internal mcu-2. Create a protocoll so that you can sort out data packets to / from second mcu or packets that acutally come over IR. Thomas "Hal Murray" <hmurray@suespammers.org> wrote in message news:h_SdnSFMd-AdkojcRVn-hg@megapath.net... > >Yesterday I bought a LEGO mindstorms set (getting infantil in my old > >days...). After building the first robot, I want to substitue the RCX by > >an FPGA. Has anyone done this so far? > > Why? Do you need microsecond level timing on some control loop? > > In general, if you can do the problem in software, it's better > to use a uP rather than a FPGA. The developement software > is more user friendly. That makes it much faster to try a new > idea. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 72077
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:EA4Rc.45885$M72.9635@news.chello.at... > Yesterday I bought a LEGO mindstorms set (getting infantil in my old > days...). After building the first robot, I want to substitue the RCX by > an FPGA. Has anyone done this so far? > Not that I've seen. www.charmedlabs.com have lego + gameboy + fpga uses ecos Some verilog code for servos etc here http://www.fpga4fun.com/ AlexArticle: 72078
"Derek Simmons" <Derek_SImmons@msn.com> wrote in message news:14030831.0408060846.73ab7ffe@posting.google.com... > Hi, > > I'm looking for recommendations for a power supply for development > boards with Xilinx VirtexE parts (ie. XCV405E, XCV300E) that require > 2.5 V, 3.3 V and 5 V. I'm looking for something cheap or a website > that explains how to build such a beast. > > I'm also interested in hearing anybody's experiences of what works and > doesn't. > > Thanks, > Derrke Simmons national http://www.national.com/appinfo/power/ http://www.national.com/appinfo/webench/power/SS/SS.cgi?flow=power&step=0A enter your requirementsArticle: 72079
Ok, so I think the answer is "in general, the tools do not yet support the Virtex 4 parts". I understand that you have a special program for "early access". But the question was in the context of doing a comparison. Unless the OP was one of the "early adopters" he would not be able to do the comparison. Austin Lesea wrote: > > Rick, > > If you subscribed to the early access program, you would be using tools > to develop your Virtex 4 design. > > Since that is a select few (one might even say insignificant number > compared to the total number of users), I would not expect anyone out > there to know about it, unless they were a customer who had expressed an > interest in being an early adopter of the latest technology (also > because if someone was part of the program, they sign the agreement not > to divulge). > > Once the product is announced, and all software enabled, the good news > is that there were many who had gone through it before you did, and > helped hammer out all of the bugs. > > We greatly appreciate those who volunteer to be early access customers, > and we hope that they feel that we have done everything we can to have > supported them, as this is definitely something that benefits everyone. > > Austin > > rickman wrote: > > Pete Fraser wrote: > > > >>"rickman" <spamgoeshere4@yahoo.com> wrote in message > >>news:41133277.590BD487@yahoo.com... > >> > >> > >>>How exactly is Virtex II considered "old" technology. Virtex 2 is the > >>>newest, fastest parts that Xilinx has. Virtex2pro may be a bit > >>>newer/faster, but they are not the same generic parts, they all include > >>>Power PC CPUs internally driving up the cost considerably. > >>> > >> > >>I guess "old" was the wrong term. > >>I was just pointing out that it might be more appropriate to compare > >>StratixII with Virtex4. > > > > > > Is that possible? Is Virtex4 supported by the current tools? > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72080
Peter Alfke wrote:
>
> > From: rickman <spamgoeshere4@yahoo.com>
>
> > Virtex 2 is the
> > newest, fastest parts that Xilinx has. Virtex2pro may be a bit
> > newer/faster, but they are not the same generic parts, they all include
> > Power PC CPUs internally driving up the cost considerably.
>
> Not true. The Virtex-IIPro fabric is almost identical with Virtex-II, with
> PowerPC and Multi-gigabit transceivers added to it. But the more advanced
> processing makes V-IIPro both faster and -lo and behold- even cheaper than
> the same logic in Virtex-II.
> So you can ignore ("throw away") the PPC and the MGTs, and V-IIPro is still
> less expensive than Virtex-II. If you use the PPC and/or the MGT, it is just
> that much more of a bargain.
> Just one of the benefits of Moore's Law and aggressive process innovation...
Yes, you can ignore and throw away the PPC. But you can't get the part
for the same price as not having the PPC. So comparing the V2P would
not be very apples and oranges. Of course there are lots of ways a V2
to StradixII is not apples to oranges, but in terms of the current parts
designed for speed and in the same price range, I think this is the best
comparison until V4 is actually out (or at least in the current release
of the software).
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 72081Mike Treseler wrote: > > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408051935.4b2c1d96@posting.google.com>... > > > Rick--Thanks very much for your offer to help. I hand coded FSM's for > > years before StateCAD came along. The advantage of StateCAD is > > accurate visual documentation to support checkout, less room for human > > error, repeatability when making changes, and productivity. > > I might buy that if simulation were not available, but > I have to agree with Rick. Consider coding in text, writing > a standard testbench and thus eliminate the > dependence on an obsolete tool. If he does not have speed issues and has a complex state diagram, then I can see his preference for a tool. I personally can code in VHDL and understand my FSM very well. But certainly working from a diagram is very useful. So, to each his own. > > The > > current project I'm doing has six packed pages with over a hundred > > states. I'll trade hours of tedious error-prone hand coding for the > > click of a mouse any day. > > Six pages of circles and arrows might fit on one > page of code and comments. My experience is that the code written for easy understanding is slightly verbose and can be a bit inefficient. To gain the best efficiency, you need to do hand optimizations that can lead to errors. But a non-optimized coding is still likely as good or better than generated code from a tool. But I would still expect it to be at least as many pages or more than the state diagrams. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72082
Brad Smallridge wrote: > > Just got my Xilinx Spartan 3 board operational. One part of the board sends > digital data to a video DAC at 48 MHz. I did a priliminary program to send > a test pattern to this DAC but the results change with a modification to the > VGACLK'event and VGACLK='1' line. If I change the '1' to a '0' I get better > results. I suppose I should now go Spartan 3 specific and use the Xilinx > DCMs? Can someone point me to beginners doc on clock distribution and DCMs? > I am printing the 68 page XAPP462 as I write this post but sheesh what a > horse! What do you mean "better results"? Sounds to me like you have a timing issue between your data and clock. What is the timing relationship between the two? Is the DAC clock feeding into the FPGA or out from the FPGA? What edge of the clock is the DAC reading data on? What edge of the clock is the FPGA sending the data on? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72083
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:1qgRc.2273$zS6.270874@news02.tsnz.net... > Eirik Seljelid wrote: > > Hi. > > > > I have an old ABEL source code (no JEDECīs) for an 82S100/PLS100 FPLA. > > Problem is that I can't find any company supporting ABEL compilers for > > these chips anymore. > > That's because no one makes the chips anymore..... > > That said, I see you CAN still actually buy the PLS100, and I also > see my PLD programmer still shows a PLS100 on the menu... > > > Xilinx, which aquired Synario/ABEL from Dataio, > > does only support it's own families of FPGAS/CPLDS. ABEL support for > > small PLDS has been taken over by Lattice also supporting only their own > > PLD families. Anyone know if Xilinx released legacy ABEL compilers as > > freeware, opensource or similar? > > Nope - Xilinx's response will be to tell you to take your ABEL source, > and recompile for a CoolRunner CPLD. > ( but that does not retrofit too easily into a PLS100 socket.) I would design a small PCB for the new CPLD that would plug in to the old device socket. LeonArticle: 72084
"Lawrence D. Lopez" <lopez-NOSPAM@mv.mv.com> wrote in message news:41126496.4020808@mv.mv.com... > I was wondering if someone could tell me > what is free and what is not. > > I've purchased (and it's on the way) the $99 > Spartan-3 development kit and I'm wondering > if any additional expenses are invoked by > using the various IP property on xilinx's web > pages. > > Larry > picoblaze is free. Think someone has made a 16 or 32 bit version http://tinyurl.com/5qgts opencores.org picoblaze ide http://www.mediatronix.com/pBlazeIDE.htm http://www.nialstewartdevelopments.co.uk/downloads.htm AlexArticle: 72085
Jim Granville wrote: > Eirik Seljelid wrote: > >> Hi. >> >> I have an old ABEL source code (no JEDECīs) for an 82S100/PLS100 FPLA. >> Problem is that I can't find any company supporting ABEL compilers for >> these chips anymore. > > > That's because no one makes the chips anymore..... > > That said, I see you CAN still actually buy the PLS100, and I also > see my PLD programmer still shows a PLS100 on the menu... > >> Xilinx, which aquired Synario/ABEL from Dataio, does only support it's >> own families of FPGAS/CPLDS. ABEL support for small PLDS has been >> taken over by Lattice also supporting only their own PLD families. >> Anyone know if Xilinx released legacy ABEL compilers as freeware, >> opensource or similar? > > > Nope - Xilinx's response will be to tell you to take your ABEL source, > and recompile for a CoolRunner CPLD. > ( but that does not retrofit too easily into a PLS100 socket.) > > The Xilinx ABEL has a certain amount of inbuilt ability, and it looks > like, if you really want to, you can get PLA and BLIF files from the > current Xilinx ABEL flows. > > What you then need is the relevent Signetics PLS100 fitter, or you > could look for the Signetics software - IIRC their SW called Amaze > supported the PLS100, and it had a successor called SLICE, but both > are ancient. > > Or, you could look for a device similar to the PLS100, but still > in production, such as the ICT PA7536 or PA7540 ? > > ICT offer current software to support these devices. > See http://www.anachip.com/eng/product/pld.php > > The 22V10 is still quite active (Atmel, ICT, Lattice), but has fewer > total pins than a PLS100. > > -jg > > > > Thanks for answering. The 82S100 is now in production reintroduced to the marked by QP Semi. Anyway, this is not an issue for me as my organisation has 82S100's in-house in adequate numbers. My project consist of replacing an older version of the programmed chip with a newer one on a limited number of circuit cards. I have already considered the PA7536, but I find it way easyer to get an older version of ABEL, compile the code for 82S100 and burn the chips. EirikArticle: 72086
> >Yesterday I bought a LEGO mindstorms set (getting infantil in my old > >days...). After building the first robot, I want to substitue the RCX by > >an FPGA. Has anyone done this so far? > > Why? Do you need microsecond level timing on some control loop? Mean reason: Just for fun ;-) Secondary reason: Get a testbed for some control programming in Java on my Java processor. > In general, if you can do the problem in software, it's better > to use a uP rather than a FPGA. The developement software > is more user friendly. That makes it much faster to try a new > idea. I will use the FPGA only for interfaces to the sensor (sigma-delta ADC) and the motor (PWM output with readback of voltage levels during the off time). I will put the schematics for the sensor and motor interface with some VHDL code on a webpage when I got it work. Martin -- ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 72087
> In general, if you can do the problem in software, it's better > to use a uP rather than a FPGA. The developement software > is more user friendly. That makes it much faster to try a new > idea. It depends how far you want to go w/ your robot. One of the LEGO extension sets includes a Logitech USB Camera. Unfortunately, the camera is connected to the PC via the USB cable (limiting the movemens of your robot), then few pieces of information are sent back to the RCX for robot control. We can't call really it an autonomous agent, can't we? It would be a better idea to handle the camera directly from the robot itself. You would need a processor to handle the USB protocol stack, but an FPGA would be nice to compute in real-time the images that you capture in order to improve the robot capability to react to what it sees. In such a case, the processor would indeed offer more flexibility but wouldn't be able to compute the huge amount of data so effiently. Therefore, an approach incl. a processor + an FPGA would be nice. EricArticle: 72088
I will try out SP3. Thanks for your reply. I guess, did you write all the ultra-long lines in the xilinx warnings and fatal errors? For example, this line, "The problem in Map effects the hierarchy preservation of the design but does not effect the functionality or other aspects so it would not cause any issues until hierarchy is attempted to be reconstructed by the netgen program which can cause the type of errors that you saw and disallow hierarchy reconstruction."... Best Regards, Kelvin "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message news:4113A90E.4080506@no_xilinx_spam.com... > > > > Kelvin, > > I just confirmed that this is the type of error that has been > addressed by the patch and it was included as a part of Service Pack 3 > so I believe this has been fixed. If you want to verify whether this > problem does still exist for you, you should re-run the design through > the software after installing service pack 3 starting at least the Map > phase since the fix for this resides in that portion of the flow. The > problem in Map effects the hierarchy preservation of the design but does > not effect the functionality or other aspects so it would not cause any > issues until hierarchy is attempted to be reconstructed by the netgen > program which can cause the type of errors that you saw and disallow > hierarchy reconstruction. > > If for some reason you still see this problem with Service Pack 3 > or a newer version, just contact me or the Xilinx hotline and we would > like to get to the bottom of the problem. > > > -- Brian > > > > > > Kelvin wrote: > > Anyway, maybe it is because I didn't upgrade my software. I am using 6.2.02i > > only. > > The error is pasted below, though my partial implementation and assembly had > > no error. > > > > > > Kelvin > > > > > > C:\projects\bt11a_jul28\top_bt\assemble>netgen -sim -ofmt > > verilog -w -ism -sdf_anno true -ngm top_sdr_map.ngm top_sdr.ncd > > Release 6.2.02i - netgen G.30 > > Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. > > > > Loading device database for application netgen from file "top_sdr.ncd". > > "top_sdr" is an NCD, version 2.38, device xc2v6000, package bf957, > > speed -6 > > Loading device for application netgen from file '2v6000.nph' in environment > > C:/Xilinx6.2. > > The STEPPING level for this design is 0. > > ERROR:Anno - Cannot correlate logic element > > '"Mmux__n0004_inst_mux_f6_0/MUXF6" > > (tag=32161 in view "FRAGCOVERED")' is with this component 'bus_left(0)' - > > cannot continue hierarchical correlation) > > ERROR:Anno - > > - > > - This application found errors in the Ngm and/or Ncd data files > > - KEEP_HIERARCHY was corrupted and ignored (database will be flattened) > > - > <snip> >Article: 72089
Derek Simmons wrote: > I'm looking for recommendations for a power supply for development > boards with Xilinx VirtexE parts (ie. XCV405E, XCV300E) that require > 2.5 V, 3.3 V and 5 V. I'm looking for something cheap or a website > that explains how to build such a beast. XCV405E, XCV300E ... it looks like small FPGAs. I don't know if it will help but on the other range of the Xilinx Family (Virtex-II and Spartan-3 > 1Mgates), we use Texas Instruments DC/DC converters (search for Swift Technology) to generate the various supply voltages. The main advantage is to have a power conversion efficiency around 90% and therefore not to dissipate that much power during the conversion itself (which is nice if you have to supply a few A). Moreover, they have a software tool that you can douwnload which will give you the schematics around the converters (capacitances, resistors, ...) as well as the precise references of all active/passive components. I've no interest in supply voltage and therefore this tool makes the job a lot easier :-) All the boards that we have designed work pretty well w/ it. EricArticle: 72090
John Smith wrote: > I worked on 15 big designs, already coded, targeting both virtexII > and StratixII. All the designs were in verilog and I used > Xilinx XST and Altera QNS at the front end. I spent lot > of time to see the quality of results from the synthesis > tools. For 11 designs, QNS won both in area and final > fmax. XST was not even comparable in the quality of results. > QNS compiler seems to do very good job compared to > XST. Also, QNS does very good job in removing redundant logic > and registers. So in my experience, QNS is a much better logic synthesis > tools compared to XST. It would have been nice to detail precisely all versions of the development tools and all device characteristics that you used to be sure that you don't compare an old XST w/ an old technology w/ a small FPGA to a new QNS w/ a new technology w/ a big FPGA ;-) For a professor, you're quite vague on the conditions of your experiments. EricArticle: 72091
Mike, I don't have a copy of C code for the current project. I have from other projects. It's just a case statement. Switch on current state and inputs. Outputs are a function of next state. Nothing complex. The only complexity is volume, volume of states, volume of inputs and outputs, and volume of decisions. The tool gets them right every time, and at the speed of my cpu. All I need to do is get the diagram correct. Since I am a visual person, this is both easy and enjoyable for me. Yes, the code is occasionally verbose. There are different areas of efficiency. How much memory does the executable take up? How fast does it run? How much production shedule does it take to write and test the code? How much paper does the source code use when you print it out? I like to think that I look at the problem at hand and concentrate on improving efficiency where and when I need it. I get in trouble when my purist side wastes efficiency in one area to obtain efficiency in an area where I don't need it. Some people can hand code, fix all the errors, make changes, and deliver the result very quickly. Some people get bogged down in the tedium and procrastinate unless they have a tool. To each engineer his own. To each problem at hand, it's own best solution. For this project that I'm on right now, the "tool" is the best approach. Simulation is immensely helpful, but again, I simulate against the diagram. Even if I hand-optimize, I still go back and simulate against the diagram. So the tool does only one thing for me, eliminate the tedious step, and it does it exceptionally well. To say that StateCAD is obsolete is to say that C is obsolete, because StateCAD is alive and thriving generating VHDL and Verilog for thousands of people. Xilinx paid LOTS of money to buy this "obsolete" technology and embed it into their tool set to generate VHDL and Verilog. But you're right, they don't generate C. If C is obsolete, then please let me know where I can get a VHDL compiler so I can start using VHDL to program my Motorola DSP56F803 cpu. I didn't intend the thread to be a debate the pros and cons of the tool, but it brings me to answer your second question. I'm putting the C code into the body of my 56F803 code. I write a shell that reads the ADC's/I/O and writes to the outputs. The shell loops continuously around the FSM. Behaviour of the controller is defined by the diagram. Very sweet. Very simple. Only the diagram is very complex. Don't get me wrong, I LOVE a good debate. And I understand the issues on the subject. I hand-coded for years and drew counless diagrams in MacDraw before I made the transition to the "tool." I learned the hard way all the drawbacks of the tool, but also welcomed the automation that eliminated the tedium and human errors of the pre-tool days. For the problem in my lap now, the tool is the way to go. Does anybody know where I can get my hands on a copy of StateCAD 4.11?? Mike Mock > > Do you have the generated C code from the previous revision? > What are you doing with C code? > > Good Luck, > > -- Mike TreselerArticle: 72092
> It depends how far you want to go w/ your robot. One of the LEGO > extension sets includes a Logitech USB Camera. Unfortunately, the camera > is connected to the PC via the USB cable (limiting the movemens of your > robot), then few pieces of information are sent back to the RCX for > robot control. Yes a camera module on the robot would be nice. I have a simple digital module (M4088 with OmniVision's image sensor OV5017) that I wanted to connect to the FPGA some time ago. I will probably do it now for the LEGO robot ;-) > > We can't call really it an autonomous agent, can't we? It would be a > better idea to handle the camera directly from the robot itself. You > would need a processor to handle the USB protocol stack, but an FPGA > would be nice to compute in real-time the images that you capture in > order to improve the robot capability to react to what it sees. The camera module I mentioned is far simpler to connect. You don't need an USB stack, just digital signals. > > In such a case, the processor would indeed offer more flexibility but > wouldn't be able to compute the huge amount of data so effiently. > Therefore, an approach incl. a processor + an FPGA would be nice. > As processor I will use my Java processor inside the FPGA, but the NIOS would also be fine. MartinArticle: 72093
Eirik Seljelid wrote: > Thanks for answering. The 82S100 is now in production reintroduced to > the marked by QP Semi. Anyway, this is not an issue for me as my > organisation has 82S100's in-house in adequate numbers. My project > consist of replacing an older version of the programmed chip with a > newer one on a limited number of circuit cards. I have already > considered the PA7536, but I find it way easyer to get an older version > of ABEL, compile the code for 82S100 and burn the chips. Wow, a PLS100 data sheet with June 2004 on it :) Google did find what looks like (most of?) Amaze, here http://www.filelibrary.com/Contents/DOS/80/ - in case you have problems finding an old ABEL with the 82S100/PLS100. You could also try direct fuse editing :) -jgArticle: 72094
The last XSE (Xilinx Student Edition) was based on ISE 4.2. Does Xilinx plan on updating XSE, or are they dropping it in favor of WEBPACK? WEBPACK doesn't have the nice Core-Generator.Article: 72095
Hallo, I wonder if anyone has had any success using RocketIO in full 8b/10b bypass mode in RX path ? First a small BUG: The Arch wizard is faulty and the generated core will not synthesize if simulation language is VHDL ( the generated VHDL can be manually fixed, optionally if the simulation language is verilog then the generate module does synthesis ok). This bug only appears when generating an core with 1 byte datapath, 8/10b bypass and using VHDL as simulation lang. In most other cases the Arch wizard is OK. Well when the RocketIO receiver is in 8b/10b bypass and all smart features disabled I would expect it to behave like simple deserializer - but it doesnt seem to be so. The receive data (with open input or even short circuit input) seems to be either some random noise or 20 bit constant. Any ideas what could cause this and if there is any cure against such behaviour? Or maybe its normal functionality of MGTs ? thanks in advance Antti PS if someone from Xilinx is not on vaccation I would appreciate an reply :)Article: 72096
"Lawrence D. Lopez" <lopez-NOSPAM@mv.mv.com> wrote in message news:41126496.4020808@mv.mv.com... There are various reference designs for the Spartan-3 Starter Kit Board available at the following link. http://www.xilinx.com/products/spartan3/s3boards.htm#RF The MicroBlaze Master System does require the Xilinx Embedded Development Kit (EDK), which sells for a suggest US$495 retail price. The MicroBlaze 32-bit RISC core and various IP functions ship with the Xilinx (EDK). The EDK includes both free IP and some evaluation IP of advanced functions. http://www.xilinx.com/products/spartan3/boards/S3_Digilent_MASTER.zip Here are some links regarding MicroBlaze and the associated IP. MicroBlaze 32-bit RISC Processor Core http://www.xilinx.com/microblaze IP Cores included with the Xilinx EDK http://www.xilinx.com/ise/embedded/edk_ip.htm If your system needs only a simple processor, the PicoBlaze 8-bit RISC microcontroller core is available as a free reference design. The "Digital Clock PCB Monitor" design for the Spartan-3 Starter Kit uses the PicoBlaze controller. http://www.xilinx.com/products/spartan3/boards/Clock_and_PCB_monitor.zip Here are few links related to PicoBlaze. PicoBlaze 8-bit RISC Microcontroller http://www.xilinx.com/picoblaze PicoBlaze User Guide http://www.xilinx.com/bvdocs/userguides/ug129.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72097
While I don't know for sure, I doubt there will be any more Student Editions. University-related folks can contact the Xilinx University Program (XUP) at http://www.xilinx.com/univ/ for donations to support their teaching/research. Paul mwrew wrote: > > The last XSE (Xilinx Student Edition) was based on ISE 4.2. > Does Xilinx plan on updating XSE, or are they dropping > it in favor of WEBPACK? > > WEBPACK doesn't have the nice Core-Generator.Article: 72098
I would suggest running it past the comp.robotics.misc group I know a few that are running robots with FPGAs but I don't keep track on the LEGO stuff.Article: 72099
It's running now. Not all my pins were soldered correctly. And a timing variable was off to boot. I may still want to use the DCM however. To answer your questions: > What do you mean "better results"? Sounds to me like you have a timing > issue between your data and clock. What is the timing relationship > between the two? Well right now I'm a happy camper. > Is the DAC clock feeding into the FPGA or out from the > FPGA? An FAE suggested I run an outside clock to the FPGA and to the DAC. > What edge of the clock is the DAC reading data on? Rising > What edge of > the clock is the FPGA sending the data on? I switched it back to rising with this sort of VHDL: if( VGACLK'event and VGACLK='1') Thanks for your help. What's with your web site? > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
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