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And make sure you have a pull up resistor external.Article: 71576
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:40FFF1EF.8728981A@yahoo.com... > You may not get a 2 ns rise time depending on the type of device you use > for a buffer. A faster logic family normally has a faster rise time. > Check the data sheet. If you are going through any standard logic > device as a buffer and you still have 40 ns rise time, there is > something else wrong, like maybe the scope you are measuring it with? Or the probes? I've made myself a pair of otherwise-not-too-good probes I use for high speed stuff: one meter of RG178*; On the scope end it's terminated with 50 ohm in the plug, on the measurement end there's 950 ohm in series. They have 1/20 gain and low impedance, true, but they've proved to be far 'truer' than anything else I've used when soldered to the target (100 ps risetime with no ill behaviour), even Tektronix' tip-grounded probes. Do NOT use a spiral-cut metal film resistor as series resistor. 4*240 ohm 1206 SMT's are good on pcb with groundplane, 2*475 ohm 'flying' is also good. /Kasper *because it's 1.9 mm thick and PTFE so it doesn't melt even when resoldered for the umphteenth time, and it's overall nice stuff.Article: 71577
> We use a couple of Rocky Mountain Logic Ant16 USB logic analyzers. Works > very well and fits in your pocket! > > http://www.rockylogic.com/products/ant16.html > > I've only used one at a time and have never had more than 12-13 channels > going at once, but suits our purposes on our under 100MHz fpga boards. Love > working on my board on my laptop with Byteblaster, serial port, and Ant16 a > blazin'. > Hi Ken, I was actually thinking of purchasing one of the Ant16 analyzers too, but I couldn't find any reviews so I was hesitant. So you don't find having only 16 channels limits your work? I am trying to debug a memory bus so I thought that 16 channels would be inadequate. I was also wondering if you know anyone who's tried maybe using more than one Ant16 analyzer at a time, ie. if you plug in 2 Ant16s would the software recognize both at the same time? Thanks! ErnieArticle: 71578
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<40fe1ee5$0$7126$db0fefd9@news.zen.co.uk>... > "ernie" <ernielin@gmail.com> wrote in message > news:d7fe9825.0407191638.58b29e0c@posting.google.com... > > Hi, > > > > Can anyone recommend any good (and cheap) 32-channel analyzers? By > > cheap I mean less than or approximately $1000. It would be nice if > > the software supported complex triggering and the analyzer had > > decently fast sampling rates. Sample depth is not really a critical > > issue but more is obviously better. > > Ernie, what do you mean by 'decently' fast? 100Msps, 500Msps? > > > Nial. > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone Based 'Easy PCI' proto board > www.nialstewartdevelopments.co.uk Hi Nial, Well, I'm thinking at least 100 Msps...I'm not trying to capture any really high-speed signals. Thanks! ErnieArticle: 71579
Dave wrote: > I have used the Ant8 logic analyzer and for the money it is good > value. Obvisouly having only 8 channels limits what you can do. The > sample depth of the Ant8 is quite small and so it is only suitable > for slow signals. It depends, but modest folk though we are, we sometimes brag about getting 500MHz from a Spartan-2 ;-) Of course, Peter A has done way better than that for a frequency counter. As I recall, he got most of the way to 1GHz in a Xilinx 4K part several years ago. > I haven't checked this, but I think the Ant16 has > only half the sample depth of the Ant8. Ant8: 3K deep, Ant16: 2K deep.Article: 71580
Bruno Cardeira wrote: > Hello! > Sorry for the previous question. > My card is done... and I have no external pull-up!! (I was confused by > the information in a older version of the xc9500 datasheet):( . My > question now is: > => Can the device get hot because of a floating input (the output that > drives the CPLD sometimes is in tri-state)? Can I solve this problem > only in software using something like a bidirectional pin driving the > pin internally with Logic "0" or Logic "1" (only when the output from > the other IC is in tri-state)? Yes, it can get hot, either by oscillation or by cross-conduction of the P and N FETs at that input, if it floats right about 1/2 the supply voltage. Well, many of the boards I've designed accumulate added resistors tack soldered onto the traces until the next manufacturing run of boards. There's not much you can do about it. JonArticle: 71581
Hi Ed, > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, > do you know any suppliers in the UK? If you don't need to get your hands on an actual piece of silicon immediately, take a look at Altera's MAX2 family. Essentially it's an SRAM FPGA with built-in config memory. The first engineering samples appear to be out, but it might be a few months until volume production. I've heard they are pretty attractively priced. http://www.altera.com/max2 Best regards, BenArticle: 71582
This bloke's published some good stuff. Check out http://www.emcesd.com/1ghzprob.htm cheers, Syms.Article: 71583
Bill Austin <biau@altavista.com> wrote: > To aid debug with Xilinx chipscope, I've added some temporary signals > to the design that are only for diagnostic purposes. However, these > signals get optimized away in the XST -> map -> PAR tool chain. > > Looking for ways to preserve the diagnostic signals so they can be > hooked up with the Chipscope Inserter tool. A few years ago, I had problems with the Xilinx tools optimizing out my state counter. Our final solution (although not pretty) was to bring one of the wires from the counter out as an output from the Verilog module. This output was never hooked up to anything, but it prevented the buggy tools from breaking our state machine. (It would appear the optimizations were not done accross modules.) Just an (ugly) suggestion, NathanArticle: 71584
"ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407221009.53f06e40@posting.google.com... > > We use a couple of Rocky Mountain Logic Ant16 USB logic analyzers. Works > > very well and fits in your pocket! > > > > http://www.rockylogic.com/products/ant16.html > > > > I've only used one at a time and have never had more than 12-13 channels > > going at once, but suits our purposes on our under 100MHz fpga boards. Love > > working on my board on my laptop with Byteblaster, serial port, and Ant16 a > > blazin'. > > > > Hi Ken, > > I was actually thinking of purchasing one of the Ant16 analyzers too, > but I couldn't find any reviews so I was hesitant. So you don't find > having only 16 channels limits your work? I am trying to debug a > memory bus so I thought that 16 channels would be inadequate. > > I was also wondering if you know anyone who's tried maybe using more > than one Ant16 analyzer at a time, ie. if you plug in 2 Ant16s would > the software recognize both at the same time? > > Thanks! > Ernie Hello, I have used the Ant8 logic analyzer and for the money it is good value. Obvisouly having only 8 channels limits what you can do. The sample depth of the Ant8 is quite small and so it is only suitable for slow signals. I haven't checked this, but I think the Ant16 has only half the sample depth of the Ant8. The software doesn't allow multiple Ant8/16 devices, so it wouldn't be much use for 32bit applications. As it's USB based the data does not arrive continuously, so trying to combine devices would most likely fail. To conclude, the Ant8/16 logic analyzers are very good value for money, but they are limited (in my opinion).Article: 71585
Hi Ernie, I don't know. I guess I'm lazy and I don't usually hookup all the address or data lines. The lower 2-5 is usually plenty for me. (I usually just want to know if the address and data are stable before WEn or something, or how long my interupt latency is, etc.) Besides, have you priced a stand alone unit? Even on ebay they're very expensive. My needs are probably modest, but the 2ns resolution has been enough for my detailed timing and backing off to 10 or 20 seems to do fine for seeing the big picture. I think the max sampling is 500MHz. I don't remember what I paid for it but my hardware consultant practically kidnapped my first one (even though he has a big HP LA) so I got another one for me. I do wish they had one that was a little better for a little more money (mainly could use a deeper buffer) but I don't see anything better that is worth it for me. I'm sure they are for others. I have the new pico DSO on the way that is only 2 channel but has 1MB of buffer with 10 GSps. Ken "ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407221009.53f06e40@posting.google.com... > > We use a couple of Rocky Mountain Logic Ant16 USB logic analyzers. Works > > very well and fits in your pocket! > > > > http://www.rockylogic.com/products/ant16.html > > > > I've only used one at a time and have never had more than 12-13 channels > > going at once, but suits our purposes on our under 100MHz fpga boards. Love > > working on my board on my laptop with Byteblaster, serial port, and Ant16 a > > blazin'. > > > > Hi Ken, > > I was actually thinking of purchasing one of the Ant16 analyzers too, > but I couldn't find any reviews so I was hesitant. So you don't find > having only 16 channels limits your work? I am trying to debug a > memory bus so I thought that 16 channels would be inadequate. > > I was also wondering if you know anyone who's tried maybe using more > than one Ant16 analyzer at a time, ie. if you plug in 2 Ant16s would > the software recognize both at the same time? > > Thanks! > ErnieArticle: 71586
After I place/route the design and generate the *.bit file how can I download the *.bit file into Spartan-3. Which program should I use. I just bought the Spartan-3 starter kit from Xilinx and there is no instruction on how to bring the bitstream from my PC into the development board. What cable should I use to connect the PC to the development board. Is there any Web which explains in details about this process. The documentation which comes with the kit does not explain how to do this. Thanks, JayArticle: 71587
Drew wrote: > I am facing this chellenge for a long time now. I have TTL compatible > clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD, > which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032) > will also give around 40 ns rise/fall time I guess. I need rise/fall > times of < 2ns for my application. I have tried different things > including trying to buffer the clock but still doesnt work. I am sure > many people have come across this problem. Anybody has a solution(s)! 20MHz is 50ns, so the clock better have rise and fall times less than 25ns each. Maybe your scale is off? -- glenArticle: 71588
Hi all. I am working with the Xilinx xcv300e and I was told that if I do not assign a reset value to registers they will be set to 0 when the device is programmed, so there must be an implicit global reset. Now I noticed that in the vhdl model generated both by the XPS and ICE for simulation purposes some of the instantiated registers without an explicit reset state in the vhdl source code are set to 1 and other are set to 0 and this facts has a big impact on the logic because the initial state of the device is different from the one it was supposed to be in. Does anyone know how to solve this problem? Is it only a difference between the simulation models and the real device? How the Xilinx tools decide which registers have to be reset and which register have to be set at startup? Thanks in advance, AndreaArticle: 71589
"Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message news:40ffff50$0$159$edfadb0f@dtext02.news.tele.dk... > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:40FFF1EF.8728981A@yahoo.com... > > You may not get a 2 ns rise time depending on the type of device you use > > for a buffer. A faster logic family normally has a faster rise time. > > Check the data sheet. If you are going through any standard logic > > device as a buffer and you still have 40 ns rise time, there is > > something else wrong, like maybe the scope you are measuring it with? > > Or the probes? > I've made myself a pair of otherwise-not-too-good probes I use for high > speed stuff: > one meter of RG178*; On the scope end it's terminated with 50 ohm in the > plug, on the measurement end there's 950 ohm in series. They have 1/20 gain > and low impedance, true, but they've proved to be far 'truer' than anything > else I've used when soldered to the target (100 ps risetime with no ill > behaviour), even Tektronix' tip-grounded probes. This technique is described in "High Speed Digital Design, A Handbook of Black Magic" by Howard Johnson. A good book to have for general high speed digital work. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 71590
Hi anyone out there,
we have designed a board with XILINX Virtex II Pro using the
RocketIO / MGT serial high speed transceivers.
Recently we experienced a problem with bit error rate (BER) and
measured the signal quality of the MGT serial links with a 20Gsample
scope and 5GHz differential probe. We found a very poor signal
waveform and got an almost closed eye diagram.
We analyzed this phenomenon and now we assume, that the signal
degradation is caused by high reflections on the line. The overshoot
and undershoot amounts to 50% of the singal swing. It seemed, that
the MGT receiver's input termination does not work properly.
Then we tried a TDR ("time domain reflectometer") measurement
to check the impedance characteristics of our board even into
the MGT's termination. The board traces are fine. Some impedance
mismatches are to be seen at vias, AC-coupling capacitors and the
Virtex II Pro package. But we think, these are not too bad, the
mismatch is in the range of 20%.
Does anyone have experience with Virtex II Pro RocketIO?
Did anyone measure signal quality or eye diagrams on such a link?
May the impedance mismatches cause the high ringing we found?
Can anyone imagine the reason for the reflections though the signal
path's impedance seems to be not so bad?
At the moment I don't have a clue.
Thank you for any hint!
Michael
Article: 71591Yeah, But almost half of us is using the parts,thus paying to produce that crap ;o)) On Wed, 21 Jul 2004 22:50:37 -0400, "Jerry" <nospam@nowhere.com> wrote: >Well I sat through an hour of market talk so I could fill out the survey in >hopes of winning a digital camera >only to have the presentation close with no survey presented. WHAT A LOAD >OF CRAP. >Article: 71592
Michael,
At the speeds of the MGT signals, just about anything can be a 'bump in
the road', and cause reflections.
No, the termination in the receiver is not perfect, (nothing is
perfect), but it is just fine regardless. Thousands of customers have
pcb's working at 3.125 Gbs error free, so it is more likely that you
have a pcb issue in your board.
I suggest you immediately contact your local FAE, and arrange to go
visit one of our RocketLabs locations, where we have all of the
equipment to troubleshoot just such an issue, and the FAEs associated
with the RocketLab are all trained and familiar with the equipment, and
how to address the issues.
One of the most common mistakes made in measuring the input impedance,
or return loss of the 100 ohm differential receiver, is that they
measure it single ended (50 ohm) and fail to take into account that a
differential return loss measurement is not a trivial or simple thing to
characterize accurately. For example, two single ended 50 ohm traces
are NOT 100 ohms differential (they are less if they are routed together
as they should be to be differential). Bad mismatch right there!
This goes for TDR as well. Unless it is a true differential TDR
measurement, you are not measuring what you need to measure (eg the Tek
CSA8000 is the only true differential TDR scope that I know of, although
I think Agilent now has one as well -- check! does it send two impulses
(or steps) at the same time of opposite voltages? If not it isn't
differential).
As well, the time resolution fo the TDR may be much faster than the rise
time of the MGT signal, and may be showing issues that do not affect the
MGT operation (ie a mis-match at 20 GHz is not an issue, as the signal
has no energy at 20 GHz).
Save yourself time and money, and go use the services that we provide to
get your problems solved. After all, we wnat to sell you chips, not
have you endlessly troubleshooting.....
Austin
Michael Mustermann wrote:
> Hi anyone out there,
>
> we have designed a board with XILINX Virtex II Pro using the
> RocketIO / MGT serial high speed transceivers.
> Recently we experienced a problem with bit error rate (BER) and
> measured the signal quality of the MGT serial links with a 20Gsample
> scope and 5GHz differential probe. We found a very poor signal
> waveform and got an almost closed eye diagram.
> We analyzed this phenomenon and now we assume, that the signal
> degradation is caused by high reflections on the line. The overshoot
> and undershoot amounts to 50% of the singal swing. It seemed, that
> the MGT receiver's input termination does not work properly.
> Then we tried a TDR ("time domain reflectometer") measurement
> to check the impedance characteristics of our board even into
> the MGT's termination. The board traces are fine. Some impedance
> mismatches are to be seen at vias, AC-coupling capacitors and the
> Virtex II Pro package. But we think, these are not too bad, the
> mismatch is in the range of 20%.
>
> Does anyone have experience with Virtex II Pro RocketIO?
> Did anyone measure signal quality or eye diagrams on such a link?
> May the impedance mismatches cause the high ringing we found?
> Can anyone imagine the reason for the reflections though the signal
> path's impedance seems to be not so bad?
>
> At the moment I don't have a clue.
> Thank you for any hint!
>
> Michael
Article: 71593"Ed" <Ed@nospam.com> wrote in message news:cdjh0q$uvr$1@news8.svr.pol.co.uk... > Hi, > > Does anyone have any experience in programming Altera FPGA's? In particular > a FLEX8000. What development environment do you use and how much does it > cost? Do any free development environments exist for it (VHDL or Verilog)? > Also, is the programming hardware expensive? > Sure, quite a lot of people have LOTS of experience in programming Altera FPGA's. Millions of FPGA chips that Altera sells are somehow being used and programmed by people, right? Back to your question. FLEX8000 series are now outdated and it is strongly advised not to start a new design with them as you may not be able to find them in the market with ease. However, if you already have a number of them in stock, surely you can use them with ease. The flagship design software of Altera, Quartus, does not support these old devices and you should try their old series of the design software named "Max Plus II". There is a free version of it available on the Altera's website but it only supports two devices from this series: EPF8452A and EPF84282A. For the other devices of the 8000 series you need the full version of the Max Plus II but buying it is not a good idea as it is now replaced by Quartus and will not be evolved any longer. The free version of the software does not have a VHDL or Verilog compiler and synthesizer and only supports schematics and also altera's own language "AHDL". However, if you already have a third-party synthesizer like Synplify, you can use them as they support this series. You don't program a Flex8000 device. They are SRAM based devices that read the configuration data when they power on. Altera makes small, 8 pin serial EEPROMs that you can program them with the programming files from Max Plus II and then connect them to the 8000 device. The old EEPROMs of altera needed special programmers (or you could use an Universal Programmer) but there is also a new series of these devices (based on Flash memory) that can be programmed using a simple JTAG cable. One example is EPC1 device. For prototypoing, you can ofcourse forget about the programming and just use a JTAG cable to directly configure the 8000 device from a computer. You can build a JTAG cable by yourself and you can find the details and schematics in Altera's application notes. Anyway, the best advice I can give you is to forget about the Flex8000 series and switch to a new family like Cyclone (or alternatively Spartan series from Xilinx). One big advantage will be that the freely available developement programs from both Xilinx and Altera come with a VHDL/Verilog compiler/synthesizer and you need not to worry about the availability of the device for a couple of years. Regards ArashArticle: 71594
"Amit Olkar" <arolk@hotmail.com> wrote in message news:7747d0b4.0407220313.3d33410c@posting.google.com... > I am an M.Sc. Instrumentation Science student in Univ. of Pune,India. > I am supposed to cover six 1/2 hr. seminars on FPGAs & CPLDs. I would > like to know more infromation about what an FPGA or CPLD comprises of > completely. If you know of any such resource/white paper, pls reply > here or mail me at : arolk@hotmail.com > I am covering VHDL, Desigin considerations for FPGAs and its Boards, > and a few case studies. If you have any info. regarding this pls reply > or mail me. I think one very accessible and good starting point would be to read the data-sheets of some the FPGA and CPLD families offered by Altera and Xilinx. These two companies are the big players in the market and together, I think they sell more than 90% of all FPGAs and CPLDs. For each family of their devices they have one big data-sheet that reviews the whole architecture of the device with details of the logic-cells, the routing and I/O pins. These data-sheets are freely available from both companies websites.Article: 71595
Hi Jay,
1) along with the kit you will receive a JTAG Cable (I received)
which connects to the jtag connector (J7) and your pc parallel
port. After hooking it up you can program by using impact.
2) In order to program the fpga use - your_project.bit file
for programming the xilinx flash(XF02..) use your_project.mcs.
programming procedure :
a) power up the board and connect the programming cable between J7
(be
careful with the polarity .. connect such that the names match on
the cable and the connector match).
b) now open impact software and right click and select Initialize
chain(3rd item).
c) the software will detect two devices (spartan - 1st from left and
the second is xcf02);
d) if you want to program the fpga then when spartan is highlighted
select
your_project.bit and after assigning the file right click on the
fpga and
selset program.
e) if you want program the xilinx flash then select your_project.mcs
and program
f) this is quite rough description, just play around with board and
you can figure it out!
any problems let me know.
regards
rao
jaypt@hotmail.com (jaypt@hotmail.com) wrote in message news:<bf356a7d.0407222053.72d527d4@posting.google.com>...
> After I place/route the design and generate the *.bit file
> how can I download the *.bit file into Spartan-3. Which program
> should I use. I just bought the Spartan-3 starter kit from Xilinx
> and there is no instruction on how to bring the bitstream from
> my PC into the development board. What cable should I use to
> connect the PC to the development board. Is there any Web which
> explains in details about this process. The documentation which
> comes with the kit does not explain how to do this.
>
> Thanks,
>
> Jay
Article: 71596ernielin@gmail.com (ernie) wrote in message news:<d7fe9825.0407221009.53f06e40@posting.google.com>... > > We use a couple of Rocky Mountain Logic Ant16 USB logic analyzers. Works > > very well and fits in your pocket! > > > > http://www.rockylogic.com/products/ant16.html > > > > I've only used one at a time and have never had more than 12-13 channels > > going at once, but suits our purposes on our under 100MHz fpga boards. Love > > working on my board on my laptop with Byteblaster, serial port, and Ant16 a > > blazin'. > > > > Hi Ken, > > I was actually thinking of purchasing one of the Ant16 analyzers too, > but I couldn't find any reviews so I was hesitant. So you don't find > having only 16 channels limits your work? I am trying to debug a > memory bus so I thought that 16 channels would be inadequate. > > I was also wondering if you know anyone who's tried maybe using more > than one Ant16 analyzer at a time, ie. if you plug in 2 Ant16s would > the software recognize both at the same time? I haven't tried the Ant16 yet, but I would be surprised if you could span more than 16 signals for a trigger when using more than one. This would require some sort of hardware support and I see nothing but USB coming out the back. > > Thanks! > ErnieArticle: 71597
Xilinx flip-flops without a preset or set input start are initialized with '0'
on configuration by default. Flip-flops with either an async set (preset) or a
synchronous set (set) are initialized to '1' by default. If these are
instantiated, the defaults can be overridden with INIT= attributes.
Andrea Sabatini wrote:
> Hi all.
>
> I am working with the Xilinx xcv300e and I was told that if I do not assign
> a reset value to registers they will be set to 0 when the device is
> programmed, so there must be an implicit global reset. Now I noticed that in
> the vhdl model generated both by the XPS and ICE for simulation purposes
> some of the instantiated registers without an explicit reset state in the
> vhdl source code are set to 1 and other are set to 0 and this facts has a
> big impact on the logic because the initial state of the device is different
> from the one it was supposed to be in.
>
> Does anyone know how to solve this problem? Is it only a difference between
> the simulation models and the real device? How the Xilinx tools decide which
> registers have to be reset and which register have to be set at startup?
>
> Thanks in advance,
>
> Andrea
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 71598On Fri, 23 Jul 2004 08:03:05 -0700, Austin Lesea <austin@xilinx.com> wrote: >Michael, > >At the speeds of the MGT signals, just about anything can be a 'bump in >the road', and cause reflections. > >No, the termination in the receiver is not perfect, (nothing is >perfect), but it is just fine regardless. Thousands of customers have >pcb's working at 3.125 Gbs error free, so it is more likely that you >have a pcb issue in your board. > >I suggest you immediately contact your local FAE, and arrange to go >visit one of our RocketLabs locations, where we have all of the >equipment to troubleshoot just such an issue, and the FAEs associated >with the RocketLab are all trained and familiar with the equipment, and >how to address the issues. > >One of the most common mistakes made in measuring the input impedance, >or return loss of the 100 ohm differential receiver, is that they >measure it single ended (50 ohm) and fail to take into account that a >differential return loss measurement is not a trivial or simple thing to > characterize accurately. For example, two single ended 50 ohm traces >are NOT 100 ohms differential (they are less if they are routed together >as they should be to be differential). Bad mismatch right there! > >This goes for TDR as well. Unless it is a true differential TDR >measurement, you are not measuring what you need to measure (eg the Tek >CSA8000 is the only true differential TDR scope that I know of, although >I think Agilent now has one as well -- check! does it send two impulses >(or steps) at the same time of opposite voltages? If not it isn't >differential). I've used an Agilent 54754A dual 18.4GHz TDR plugin in an 86100A scope for testing 10Gbps connections. I *think* it does a true differential measurement. [ I don't have the documentation handy. ] >As well, the time resolution fo the TDR may be much faster than the rise >time of the MGT signal, and may be showing issues that do not affect the >MGT operation (ie a mis-match at 20 GHz is not an issue, as the signal >has no energy at 20 GHz). Yes, but better time resolution means better spatial resolution, allowing you to work out what went wrong with your board design. (I found this out the hard way.) Regards, Allan.Article: 71599
On 23 Jul 2004 10:15:08 -0700, raonpc@gmail.com (pablo aimar) wrote: >Hi Jay, > 1) along with the kit you will receive a JTAG Cable (I received) > which connects to the jtag connector (J7) and your pc parallel > port. After hooking it up you can program by using impact. > 2) In order to program the fpga use - your_project.bit file > for programming the xilinx flash(XF02..) use your_project.mcs. > > programming procedure : [snip...snip...] Thanks for the post, rao. I'm not the OP but I've used enough development boards to know that what seems simple once you've done it is often not at all obvious on the first time through. It's looking like a rainy weekend here and I was planning to give that board a little workout, myself (should be fun). -- Rich Webb Norfolk, VA
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