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Hello I am trying to select a FPGA from the Xilinx spartan 2E family of devices to implement a PCI core. To be specific I am looking at lowest speed grade of Xilinx XC2S300E-6-FG456 . This device is not listed in the list of devices in the Xilinx 33 MHz PCILogicCore datasheet. Only the PQ208 version of the device is listed. Would it be safe to assume that the FG456 version would meet the timing of the PCI interface. Has anybody implemented a PCI core in the device that I am talking about? Please let me know. Any comments and suggestions towards device selection would also be appreciated -Krishna Kumar DSP Systems Engineer Signalogic Inc Dallas, TXArticle: 71601
Nathan Hunsperger <njh@soda.csua.berkeley.edu> wrote in message news:<cdpp8q$bbe$1@agate.berkeley.edu>...
> Bill Austin <biau@altavista.com> wrote:
> > To aid debug with Xilinx chipscope, I've added some temporary signals
> > to the design that are only for diagnostic purposes. However, these
> > signals get optimized away in the XST -> map -> PAR tool chain.
> >
> > Looking for ways to preserve the diagnostic signals so they can be
> > hooked up with the Chipscope Inserter tool.
>
> A few years ago, I had problems with the Xilinx tools optimizing
> out my state counter. Our final solution (although not pretty) was
> to bring one of the wires from the counter out as an output from
> the Verilog module. This output was never hooked up to anything,
> but it prevented the buggy tools from breaking our state machine.
> (It would appear the optimizations were not done accross modules.)
>
> Just an (ugly) suggestion,
> Nathan
Thanks, Nathan. That approach was considered. Eventually, however, it
was found that a "keep" constraint could be attached to the signal.
The constraint can be associated with the signal in a few ways. The
one that I used sucessfully was to declare "keep" as a VHDL attribute
and then specify it for the signal in question:
signal diagnostic_sig : std_logic;
attribute keep : string;
attribute keep of diagnostic_sig : signal is "true";
That kept the signal around through XST synthesis. Then, when the
chipscope was inserted, the signal was available.
The description in the Constraints Guide said that the purpose of
"keep" applied to a signal is to inhibit the tools from pulling it
into, for example, a LUT. However, "keep" also seems to work for
keeping an unconnected signal from being optimized awaye. (The
description of "keep" in the XST document left me unsure as to the
usage and syntax, so I was glad that the constraints guide at least
made the syntax clear.)
A technique that didn't seem to work was to drive the diagnostic
signal into one input of a two-input AND gate, then feed the AND
output back to the other input -- i.e. a tight combinatorial feedback
loop leaving a piece of worthless logic but no floating signal.
However, I may have made mistakes when doing this. Does anyone know if
this should work?
Article: 71602> Would it be safe to assume > that the FG456 version would meet the timing of the PCI interface. Has > anybody implemented a PCI core in the device that I am talking about? > Please let me know. Any comments and suggestions towards device > selection would also be appreciated XC2S300E-6-FG456 supports PCI 64/33 and I don't expect any problems with PCI 32/33. PCI 32/33 LogiCORE only includes UCF file (pin out) for supported devices. Try contacting your FAE or hotline to obtain UCF file for PCI 32/33 targeting FG456 device. Regards VikramArticle: 71603
Hi,buddy: i have all vendor EDA tools and the following IP cores.if u need pls contact me. IP core list(all cores are silicon proven. it incldues RTL) ************************** 1>10M/100M/1000M/10G Ethernet MAC 2>USB1.0/USB2.0/USB-OTG 3>PCI,PCI-X,PCI-Express 4>JPEG,MPEG4,MJPEG 5>ARC600 series DSP 6>8051 series,Z80. 7>SD-MMC 8>ARM LCD controller ........... ticino276@hotmail.comArticle: 71604
> Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? There are regularly batches of Altera MAX7xxxx on Ebay for about £1/device. As they are not S sevices, you need a special programmer WimArticle: 71605
Hey
i am pretty green at this VHDL...
can someone tell me the error in this code.. :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity Test is
port(
b: in std_logic;
a: out std_logic_vector(7 downto 0));
end Test;
architecture eksempel of Test is
signal a_old,a_new : std_logic_vector(7 downto 0);
begin
test_if:process(b)
begin
if b='1' then
a_new <= a_old + 1;
end if;
a<=a_new;
end process test_if;
end eksempel;
it was suposed to add 1 to A
regards Kasper
Article: 71606We (Synplicity) have a tool called Identify that solves this problem. You do your instrumentation at the RTL level in terms of RTL constructs - trigger if I reach this line of code in my state machine and that bus has a specific value. This avoids any issues with optimizations changing or removing logic in your design. We also support an incremental flow where you can change signals you are watching without needing a P&R run. Other debugging tools are equivalent to the software notion of writing in C and debugging assembly. Identify is a true source level debugger for hardware. Ken McElvain Bill Austin wrote: > To aid debug with Xilinx chipscope, I've added some temporary signals > to the design that are only for diagnostic purposes. However, these > signals get optimized away in the XST -> map -> PAR tool chain. > > Looking for ways to preserve the diagnostic signals so they can be > hooked up with the Chipscope Inserter tool.Article: 71607
news@sulimma.de (Kolja Sulimma) wrote in message news:<b890a7a.0407190943.4aa1f25c@posting.google.com>... > > This one is a little larger (51mm x 44mm) but also less expensive: > > http://shop.trenz-electronic.de/catalog/product_info.php?products_id=43 > > It was designed in a way that you can cut off one of the B2B > connectors to obtain an area of about 51mm x 31mm and still have 60 > user I/Os. > > Kolja Sulimma Thanks for the link Kolja, that was one of the smallest ones I've seen for sale with such a large gate count. But I only have a couple millimeters leeway from the 40mm x 30mm x 10mm dimensions so I won't be able to use it, unfortunately. Do you know of any smaller boards than this one? -DAGArticle: 71608
> can someone tell me the error in this code.. :
[...]
> it was suposed to add 1 to A
I would say your code adds 1 to a_old ... your
problems are:
- a_old is not set ... there is no startup-init nor any
other assignment
- what should be the output of A if b = '0' ??
you need a flipflop description for a counter
if rising_edge(b)
a_out <= a_out + 1;
end if;
there are many tutorials on the web ... perhaps you
should read one ...
thinking in "hardware" is very different from sequential
programming - you need to learn that for vhdl ...
bye,
Michael
Article: 71609
I believe that the phrase:
a_new <= a_old + 1;
should be:
a_new <= a_old + "0000001";
Didn't check the rest...
Doesn't he need the use list the IEEE.STD_LOGIC_ARITH.all; too?
Don
"Repzak" <repzak@GEDhotmail.com> wrote in message
news:4102799b$0$66476$14726298@news.sunsite.dk...
> Hey
>
> i am pretty green at this VHDL...
>
> can someone tell me the error in this code.. :
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use ieee.std_logic_unsigned.all;
>
>
> entity Test is
> port(
> b: in std_logic;
> a: out std_logic_vector(7 downto 0));
> end Test;
>
>
> architecture eksempel of Test is
> signal a_old,a_new : std_logic_vector(7 downto 0);
> begin
>
>
> test_if:process(b)
> begin
>
> if b='1' then
> a_new <= a_old + 1;
> end if;
> a<=a_new;
> end process test_if;
>
> end eksempel;
>
>
> it was suposed to add 1 to A
>
> regards Kasper
>
>
Article: 71610Good evening, everybody, Now - before I get cracking on creating a VHDL model of Xilinx's Rocket I/O MGT - has anyone else done this already? And would they be willing to share it out of the goodness of their heart? Cheers, Tim.Article: 71611
> there are many tutorials on the web ... perhaps you > should read one ... Hey... Thats defentlig true... i also have some books and some urls, but a lot to take care of in the first place i need more some simple code... btw i am using protel / nexar... but there are so much to read, i need to get going a litle to try and read and try... i think i got some of the problems... my next is pushbutton bouncing... ): KasperArticle: 71612
I'm designing a CPLD using the block diagram / schematic editor in Quartus II Version 4.1 Web Edition. Does anyone know a way to export the block diagram as an image? As far as I can see, the only way is to take a screen shots or else print to file.Article: 71613
On Sat, 24 Jul 2004 21:35:56 +0000, Tim wrote: > Good evening, everybody, > > Now - before I get cracking on creating a VHDL model of Xilinx's Rocket I/O MGT > - has anyone else done this already? And would they be willing to share it out > of the goodness of their heart? > > Cheers, > Tim. There are SWIFT models provided by Xilinx.Article: 71614
Hi Andrew, Print to file is your best bet. Exporting the block diagram as an image is not available at the present time. I will pass this request on to the right folks. - Subroto Datta Altera Corp. "Andrew Holme" <ajholme@hotmail.com> wrote in message news:966757eb.0407241646.48d695f6@posting.google.com... > I'm designing a CPLD using the block diagram / schematic editor in > Quartus II Version 4.1 Web Edition. > > Does anyone know a way to export the block diagram as an image? As > far as I can see, the only way is to take a screen shots or else print > to file.Article: 71615
Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator - bit of a bugger if you've only got Modelsim XE.Article: 71616
"Subroto Datta" <sdatta@altera.com> wrote in message news:okHMc.491$uC7.328@newssvr19.news.prodigy.com... > Hi Andrew, > > Print to file is your best bet. Exporting the block diagram as an image > is not available at the present time. I will pass this request on to the > right folks. Windows Metafile would be useful. It can them be pasted into a document and will scale nicely. The Pulsonix PCB software I use has this facility. LeonArticle: 71617
"Don Golding" <dgolding@sbcglobal.net> wrote in message
news:KBAMc.96743$9g3.68705@newssvr29.news.prodigy.com...
> I believe that the phrase:
> a_new <= a_old + 1;
> should be:
> a_new <= a_old + "0000001";
>
> Didn't check the rest...
> Doesn't he need the use list the IEEE.STD_LOGIC_ARITH.all; too?
>
> Don
>
> "Repzak" <repzak@GEDhotmail.com> wrote in message
> news:4102799b$0$66476$14726298@news.sunsite.dk...
> > Hey
> >
> > i am pretty green at this VHDL...
> >
> > can someone tell me the error in this code.. :
> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.all;
> > use ieee.std_logic_unsigned.all;
> >
> >
> > entity Test is
> > port(
> > b: in std_logic;
> > a: out std_logic_vector(7 downto 0));
> > end Test;
> >
> >
> > architecture eksempel of Test is
> > signal a_old,a_new : std_logic_vector(7 downto 0);
> > begin
> >
> >
> > test_if:process(b)
> > begin
> >
> > if b='1' then
> > a_new <= a_old + 1;
> > end if;
> > a<=a_new;
> > end process test_if;
> >
> > end eksempel;
> >
> >
> > it was suposed to add 1 to A
> >
> > regards Kasper
> >
> >
>
>
I think that's the problem as well. You could use:
a_new <= a_old + '1'; -- note the ' '
You really want some sort of reset. Also, you can just use a single signal
to hold the temporary A value (I have called it a_sig). You can then change
your process to read:
test_if: process(b)
begin
if b'event and b = '1' then -- rising edge of b
if RST = '0' then
a_sig <= (others => '0'); -- make a_sig all zeros
else
a_sig <= a_sig + '1'; -- increment a_sig
end if;
end if;
end process test_if;
a <= a_sig; -- put this line outside of your process (a will always
equal a_sig).
Hope that helps.
Article: 71618"Ed" <Ed@nospam.com> wrote in message news:<cdm3g3$809$1@news5.svr.pol.co.uk>... > Hi, > > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? If you do not require large quantities only CPLD are available in that quantity. (Even a XC2S15-5VQ100C costs 10$ if you buy only a few pieces) CPLDs start from approximately 1GBP and are available in the UK from digikey and other stores as. If it is for a hobby project that does not need an ongoing supply for chips I still have a surplus of 10 pieces XC4010XL and 180 pieces XC4013XL that I would sell to you for 5GBP each. I also have software that supports these chips. If you need only a single prototype you should buy a low cost development board from www.trenz-electronic.de or one of its US competitors like xess or digilent. Kolja SulimmaArticle: 71619
On Sun, 25 Jul 2004 08:10:33 +0000, Tim wrote: > Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator > - bit of a bugger if you've only got Modelsim XE. The performance is also awful. My testbench takes a 10 to 1 performance hit when using the RocketIO SWIFT models (I use them in both NCverilog and ModelSim, it cripples both of them). Would Peter or Austin please explain why Xilinx decided to use SWIFT models instead of a plain Verilog model. The secrets in a SerDes are at the transistor level not at the logic level. A nice fast bus functional Verilog model would have been prefered by all.Article: 71620
Hi, all , When simulating the behavioral model, it is ok, but when I simulating the post-translate vhdl model, the simulation can't generate valid results (output are all uncertain state U). from the warning, it seems the UnitUnderTest has not been affiliated, Could you help explain what happens ? thx, ** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component 'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I do have this on the entity. # ** Warning: (vsim-3473) Component 'uut' is not bound. best regards, JimmyArticle: 71621
Jimmy wrote: > Hi, all , > > When simulating the behavioral model, it is ok, but when I simulating the > post-translate vhdl model, the simulation can't generate valid results > (output are all uncertain state U). from the warning, it seems the > UnitUnderTest has not been affiliated, Could you help explain what happens ? > thx, > > ** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component > 'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I > do have this on the entity. > If I understand what you are saying, then the problem is that your testbench is setting that generic, but the generic does not exist on the post-translate (I assume post-synthesis?) model. That would be expected; generics are resolved at synthesis time, and do not appear in the post synthesis models. Take a look at the generated file. -- My real email is akamail.com@dclark (or something like that).Article: 71622
Are there any FPGA parts available today that can contain a 32-bit, free-running counter running at 1GHz and a 32-bit storage register to take a snapshot of the count and read it to a slower external interface? The Xilinx Virtex II Pro seems to go up to about 325MHz... Thanks. DaveArticle: 71623
ajholme@hotmail.com (Andrew Holme) wrote in message news:<966757eb.0407241646.48d695f6@posting.google.com>... > I'm designing a CPLD using the block diagram / schematic editor in > Quartus II Version 4.1 Web Edition. > > Does anyone know a way to export the block diagram as an image? As > far as I can see, the only way is to take a screen shots or else print > to file. Two choices. 1. Get the screen image sized and shaped to suit your needs. Do a print screen ten open wordpad and do a paste. You've got the screen shot as an image file. 2. Get a PDF printer driver. Lots of shareware you can try before you buy I use WIN2PDF. THe print to the pdf driver and you've got a pdf file that you can view and print. Good Luck George www.embedded-designer.comArticle: 71624
> Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to take a > snapshot of the count and read it to a slower external interface? I doubt any FPGAs can count that fast ... not directly - you could use 4 counters running with different clocks (shifted by 90 degrees) at 250 MHz ... - you could use the Rocket-IO SerDes ... de-serialize your gate-signal and process the datawords at a lower frequency .. bye, Michael
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