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On 31 Oct 2006 01:19:57 -0800, "daver2" <davidroberts@siemens.com> wrote: > >Andy wrote: >> The original design was verified for the timing and behavior >> (specifically glitch-free behavior) of hard NOR gates within the gate >> array fabric that it was implemented on. >> >> Change the NORs to luts, and change the timing (radically), and you no >> longer have a reliable design, no matter how reliable the original was. >> >> Combinatorial feedback loops in FPGAs are bad medicine. >> >> If the original design had macros for every flop built out of NORs, you >> could replace those macros with rtl code for conventional flops, and >> then ISE would be happy, and so would you/your design. Alternatively, to (a) remain true to the original design (and prevent ISE from optimising out "redundant" terms etc) AND (b) to overcome synthesis speed issues, consider a hierarchical implementation. If you can identify a latch or flop made from NOR gates, implement ONLY that latch from NOR operations as a complete design unit in ISE. It shouldn't take long to synthesise a few gates! The result will be a .ngo file representing that component. Then instantiate that latch or flop - not the NOR gates - in the next readily identifiable level of the design (e.g. a counter) as a "black box" component. You can force it to be a black box with "black box" attributes; alternatively you can simply make the counter a separate project, and omit the design file for the flop. Simply tell the place and route tools where to look for pre-compiled cores, or copy the flop's .ngo file into the counter's project directory. When synthesising the counter, ISE cannot then try to optimise down into the flop. This (a) massively reduces synth time since the counter is composed largely of simple black boxes, and (b) _should_ preserve the design intent (including gate delays) intact. Routing delays may still be a problem, though you can floorplan your components to reduce this. And so on up to the top level, if you can see the design structure in terms of black boxes. A side benefit is, if you decide to give in and use conventional flops, you can substitute an .ngo file containing that flop for the NOR one. - BrianArticle: 111251
> Can anyone suggest a good stream cipher algorithm for hardware > implementation. Look for 'Self Shrinking Generator', compact and no known attacks yet WimArticle: 111252
On 2006-10-31, Ben Jones <ben.jones@xilinx.com> wrote: > In fact, register duplication rarely makes timing better; in fact in many > high-performance pipelined designs, it can make it much worse (explanation > available on demand). I guess I'll bite and see if my understanding is close to what you have in mind: My feeling is that register duplication could worsen a design with combinatorial logic followed by a flip flop. This means either that the combinatorial logic has to be duplicated (which would enlarge the design and perhaps slow down the circuit due to extra routing, or by only duplicating the flip flop which will certainly demand extra routing since it is normally possible to place a FF directly after a LUT using only high speed dedicated routing. On the other hand, I can't really see that register duplication will make the performance much worse (unless the synthesizer makes very bad choices of course) so you might have something else in mind. /AnderasArticle: 111253
I have a EDK based design with 8 MB of external flash memory on the PLB via the plb_emc core. This is for a Virtex II Pro using EDK/ISE 7.1i, latest service packs. The flash is addressed at 0xFF800000 - 0xFFFFFFFF. Thus our plan is to have the processor reset vector in the flash and execute directly from flash. I am able to successfully use the XPS flash programming tool to burn the flash on my board in most cases I have tried. It reports the CFI info properly. However I have observed these failures (that seem to me to be related). 1. If I try to burn a full 8MB image, I get an immediate parameter check that the file is larger than the flash. I have carefullly examined the file and it is exactly 8MB (8388608 bytes). If I make it 16 bytes smaller and use an offset of 0 it burns OK. 2. Using the "16 bytes less than 8MB" image, if I set the offset to 16, the burn fails with the error message below about not erasing correctly. Offsets between 0 and 15 (inclusive) work correctly (except as noted in number 4). 3. Using a 256KB image, I can burn it at any offset (well I think so - I haven't tried them all :) ) up to 0x7BFFFF. This is up to but not including the last byte of the flash address space. If I use an offset of 0x7C0000 (This is the configuration I really need, a 256K image at the high end of flash address space. I must include the reset vector.) it fails with the error message below. 4. With either size image, the offset seems to be modulo 4 i.e. offsets of 0, 1, 2, and 3 all start at the first byte of the flash address space. I suppose this is not necessarily wrong, but it is unexpected. The error message reported is: Flashwriter Application reported and error: The flash block erase operation errored out! I opened a web case with Xilinx and was told this: 0xFFFFFFFF is hard-coded for the reset vector and cannot be accessed. It cannot be overwritten. That is why you are getting this error. This seems wrong to me. I say this for the following reasons: 1. I can load an FPGA design with BRAM at address 0xFFFFFFFC and then write any value I want to that address using a simple PPC program. 2. I can load an FPGA design with Flash at address 0xFFFFFFFC and the program that location successfully with my own test code running on the PPC 3. If I load an FPGA design that places the flash at 0x08000000, the XPS tool errors out in the same way as I described in the original problem statment. It reports an error trying to erase blocks, if the programming range includes the last 32 bit word. Does anyone have any insight or experience that could help here? Thanks, SteveArticle: 111254
I only claimed that you lose 80% of the performance improvement of the next generation (I mean differentally), not 80% of the whole performance. This debate can go on and on. I suppose we both made our points... Peter On Oct 31, 12:33 pm, "KJ" <Kevin.Jenni...@Unisys.com> wrote: > > To take an example, and using your numbers, are you suggesting that the > performance of a Xilinx DDR controller implemented using the Wishbone > interface would be 80% slower than the functionally identical DDR > controller that Xilinx has? If so, why is that? If not then what > point were you trying to make? > > >Article: 111255
I have used the LAN91C111 in the past with an Altera chip and isn't a bad solution if you don't want high performance. LAN91C111 isn't a cheap chip from my experience so watch out if you are cost sensative. There isn't much choice in stand alone non-PCI chips so if you want much choice with a stand alone then you might consider implementing a PCI host interface. For a cost sensitive volume production item it is hard to beat a low cost PCI Ethernet chip on cost but off course you need to add the cost of the PCI interface in the FPGA. For a FPGA MAC solution there is a choice from all the vendors and not a lot to choose between. FPGA MACs can be quite large and tend to need a larger end device to support them so do examine the core datasheet before committing to this approach. There some technical advantages as other posts have mentioned. A nice Xilinx alternative if you are not penny pinching is the Virtex-4 FX12. We have put this in a very compact processor system with a pile of other sexy things and I was well impressed. Something like it might make our product line one of these days. Depending on your pricing it can be actually reasonably close in cost to a low cost FPGA + non-PCI Ethernet chip. This chip has dual channel 10/100/1000 capability and if you find it useful an embedded PowerPC as well. John Adair Enterpoint Ltd. Todd wrote: > Hi all > > I'm a design engineer trying to evaluate the large number of > possibilities for adding Ethernet to our embedded system. > > So far I've been very impressed by the Altera Cyclone II with NIOS II > and free lightweight TCP/IP stack. Adding Ethernet appears to amount > to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). > > Anyone have experience with using the Cyclone II merely for Ethernet? > Should I try to put the MAC inside the FPGA and just use an external > PHY? > > Any recommendations for a communication protocol between the FPGA and > my DSP? SPI seems the most obvious choice for reasonably high > bandwidth (>6 Mbps). Right now my DSP runs from a 1.5 Mbps UART so > mimicking this data flow would save me a bunch of assembly code > changes. However, I'd like to send more data back to the host so could > use upwards of 6 Mbps. > > Also, I'm interested in general recommendations for System on a > Programmable Chip (SOPC), which Altera is obviously highly interested > in advancing. It seems very attractive since I could eventually get > rid of the DSP by simply creating a second NIOS II processor within the > FPGA and porting my assembly code to C. The upgrade path is > straightforward and indefinite since Altera will keep coming up with > even better FPGAs. Any caveats or warnings? Lastly, are there major > reasons I should be considering Xilinx instead? > > Thanks in advance for the help! > -ToddArticle: 111256
Have you tried the distributors, including DigiKey? Peter Alfke On Oct 31, 10:12 am, Jon Elson <e...@pico-systems.com> wrote: > Hello, all, > > Does anyone know where I can get just a few (5 - 10) Xilinx > XCS30-3TQ144C chips? Anybody who has them wants to sell me > a minimum of a hundred or more. I just need a few to make > repairs on equipment in the field. I just got a board back > from a customer who had a lightning strike, and I had to salvage > a chip off a test module to get his unit repaired. > > If anyone has a few of these chips laying around, I'd be glad to > pay the going rate for them, too! I can probably use other speed > ranges or temp ranges as well. I'm in the US, but that shouldn't > make much difference, I seem to be buying my Xilinx chips from > Australia these days! > > Thanks much in advance. > > JonArticle: 111257
The original subject was metastability, and the second subject was unreliable operation when an asynchronous signal is, in parallel, synchronized in more than one flip-flop, where even the most minute delay/set-up-time difference can cause severe problems. Peter Alfke On Oct 31, 1:08 pm, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2006-10-31, Ben Jones <ben.jo...@xilinx.com> wrote: > > > In fact, register duplication rarely makes timing better; in fact in many > > high-performance pipelined designs, it can make it much worse (explanation > > available on demand).I guess I'll bite and see if my understanding is close to what you have > in mind: > > My feeling is that register duplication could worsen a design with > combinatorial logic followed by a flip flop. This means either that > the combinatorial logic has to be duplicated (which would enlarge the > design and perhaps slow down the circuit due to extra routing, or > by only duplicating the flip flop which will certainly demand extra > routing since it is normally possible to place a FF directly after a LUT > using only high speed dedicated routing. > > On the other hand, I can't really see that register duplication will make > the performance much worse (unless the synthesizer makes very bad choices of > course) so you might have something else in mind. > > /AnderasArticle: 111258
Hi, I have seen a scope which has 1 Mohm 30 pF input impedance and frequency response 0 to 12MHz (+/- 3dB) My question: What is the difference between input impedance and frequency response?Article: 111259
nnn wrote: > Hi, > I have seen a scope which has > > 1 Mohm 30 pF input impedance > > and frequency response > > 0 to 12MHz (+/- 3dB) > > My question: > > What is the difference between input impedance > and frequency response? input impedance has to be driven, and so will prsent power transfer to the voltage mesurement equipment, and the 3db response of the line by wobble matching the graticule scale, will be the bandwidth. the line driver has its own input impedance, which can only be driven by limited power. ok?Article: 111260
Peter Alfke <peter@xilinx.com> wrote: > Have you tried the distributors, including DigiKey? > Peter Alfke For the 5 Volt Xilinx series, none of the part is on stock at Digi, and all have quite high minimum order -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 111261
These two have nothing to do with each other. The 1 megohm is a dc load and means that you can measure dc voltages with very little loading. The 30 pF is in parallel, and loads down any ac input. How much it loads down is determined by the driving impedance (nowadays often a few 100 Ohms or even less in digital circuitry) and the frequency. The 12 MHz describe the roll-off frequency seen, even when you drive it with a perfect high-frequency signal. BTW, these specifications are ok for audio work, but be careful when you debug fast digital logic. You might be driving blind... Peter Alfke ============== On Oct 31, 1:56 pm, <nnn> wrote: > Hi, > I have seen a scope which has > > 1 Mohm 30 pF input impedance > > and frequency response > > 0 to 12MHz (+/- 3dB) > > My question: > > What is the difference between input impedance > and frequency response?Article: 111262
Thanks for your reply. It does seem like I sould start with an easy filter first and work up to the filter I want to built. Something Tim Wescott said perplexes me, though. Filtering and then decimating does sound like it will be computationally cheap, but I wonder just what is the advantage of decimating a control variable? I'm fixed at 200kHz sampling, and the process I'm interested in controling is at 200 Hz. Having 200 kHz bandwidth makes the noise larger, (it should be a constant in volts per root hertz, so more bandwidth means larger noise in volts). It seems to me that filtering to 200 Hz is the correct way to reduce the bandwidth and thus reduce the noise in volts. Minimizing the noise is an important concern for controling the process quickly. It's not clear to me (and I'm sure this is my fault for not being better informed) that decimating is an equivalent way of reducing the bandwidth. What effect will decimating have on noise as expressed in volts? And this brings up a broader question I've hand in the back of my mind. Is it better to sample as high as possible and then filter down to the desired bandwidth? Or is it better to sample as needed, and the gains of sampling like mad and filtering like crazy are minimal. Forget the practical aspects of limited memory and large files. I do have a hardware anti-aliasing filters. Your notes made some good points, anti-aliasing is always an important concern! Will Tim Wescott wrote: > will.parks@gmail.com wrote: > > > Hi, > > > > I had a very general question. > > > > I'd like to design a low-pass filter, and I was wondering what the > > general lay-out for one was. > > Tee hee. > > filter > .------. > signal in | | signal out > ---------->| |-----------> > | | > '------' > > What? This isn't helpful? That's probably because you could write a > book about what to put in the 'filter' block. > > Common things would be an IIR linear filter or an FIR linear filter, but > there are other options (including the decimation you mention later), > and just "IIR or FIR" covers quite a bit of ground. > > > > I'm currently using a National Instruments FPGA module. They sell a > > filter design kit for $1,000 and I'm wondering if I can avoid buying > > it. > > Yes you can, but you have to know what you're doing. Ultimately you'll > have to know what you're doing to really use the NI package as well, > unless your capabilities far outstrip your requirements. Those sorts of > packages are great for getting something working in the lab early, but > without knowing what they do you can't effectively get that last 10% > worth of performance that makes the difference between a product that's > a disaster and a product that's a success. Of course, if you _do_ know > what they do, you don't need them. > > "Understanding Digital Signal Processing" by Rick Lyons would be a big > help, but you need answers faster, I assume. > > > > The National Instruments FPGA I'm currently using comes with one FIR > > filter example which uses 4 shift registers (plus the imput) and three > > coefficients to filter the signal by a factor of 10 (200kHz -> 20kHz). > > Which in itself is strange, since the window is only 5 points wide? > > > > I need to filter it down to 200 Hz for my application. I'm afriad of > > programming 500 shift registers. Even if I did something clever with > > the FIFO, in the end, there's a lot of multiplication, which is very > > costly. > > You aren't saying what you're filtering down _from_, but your mention of > 500 shift registers (I assume you mean a 500 tap delay line) implies > that you're sampling at somewhat less than 100kHz (if you're sampling at > exactly 100kHz you need to read > http://www.wescottdesign.com/articles/Sampling/sampling.html). I'll > assume that you are sampling at 25kHz -- if you use one multiplier you'd > only need to clock it at 12.5MHz, which is a pretty un-challenging clock > speed. You'd still need that 500-tap delay line, however. > > > > It seems like some kind of decimation strategy is my only hope? but > > this is certainly not the same as filtering, and the primary objective > > is to reduce the noise in real time. > > Decimation is not filtering, but if you filter then decimate you can > reduce both the necessary processing (you only have to run through that > 500-tap filter once for each output sample, not once for each input > sample) and have less data for following stages to slog through. > > Using a sinc^n filter has two advantages: it's light on processing > resources, because all the 'multiplies' are by 1 or 0, and it sounds > damn impressive when you throw the name at the boss. It works _very_ > well in an environment where you're down sampling, because the filter > has natural nulls at anything that would alias down to DC, and that's > where you're usually most interested in what's going on. > > > Or is there something similar to > > the FFT that divides and conqueres, breaking it up into smaller parts > > to get it done. > > In theory you reach a point where it's more efficient to filter by > performing an FFT on a block of data, windowing it by your desired > filter function, then performing an IFFT back to the 'real world'. Rick > Lyon's book goes into this. > > In practice this sort of optimization is very problem-dependent; using > some sort of simple filter-and-decimate may take significantly less > resources. > > > > So I was wondering what the general strategy was for such filters. > > > > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com > > Posting from Google? See http://cfaj.freeshell.org/google/ > > "Applied Control Theory for Embedded Systems" came out in April. > See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 111263
nnn, Input impedance is the load the measurement places on the node being measured. In the case you mention, a 1 megohm resistor, with a 30 pF capacitor in parallel. If this is a 50 ohm impedance signal source, then the 1 megohm is not affecting anything (1 megohm in parallel with 50 ohms is still very very close to 50 ohms), but 30 pF and 50 ohms is about a 1 nanosecond time constant, so the capacitive load means the probe itself will significantly load down signals above 100 MHz (Z=1/2*pi*f*c = 53 ohms for 100 MHz !!!). 'Bandwidth' is where the measurement "rolls off" or is no longer accurately able to detect the amplitude at that frequency. '0 to 12 MHz +/- 3dB' means (to me) that the amplitude you measure can be off by 2:1 anywhere in the 12 MHz bandwidth, which is really lousy (bad). Typically, a scope bandwidth is stated as +/- 0.5 dB from 0 to 1 GHz (for example), with a roll off of -3 dB at 1.5 GHz. Basically telling you this scope would be fine for signals with frequencies below 1 GHz, or rise times longer than 1 nanosecond. If you try to measure anything faster than that, the measurement will not be accurate, and you will not see what is really there, only will see a low pass filtered version of what is there. Austin nnn wrote: > Hi, > I have seen a scope which has > > 1 Mohm 30 pF input impedance > > and frequency response > > 0 to 12MHz (+/- 3dB) > > My question: > > What is the difference between input impedance > and frequency response? > > >Article: 111264
jacko wrote: > nnn wrote: >> Hi, >> I have seen a scope which has >> >> 1 Mohm 30 pF input impedance >> >> and frequency response >> >> 0 to 12MHz (+/- 3dB) >> >> My question: >> >> What is the difference between input impedance >> and frequency response? > > input impedance has to be driven, and so will prsent power transfer to > the voltage mesurement equipment, and the 3db response of the line by > wobble matching the graticule scale, will be the bandwidth. the line > driver has its own input impedance, which can only be driven by limited > power. > > ok? > Huh? (in response to what Jacko wrote) x-posted to s.e.b where this is more appropriate. The input impedance of the measurement device specifies the load it presents to the signal being measured. It is important to know for a number of reasons. The +/-3dB response is specified as that is how bandwidth is normally specified (-3dB is a half power point). In this case, it specifies that the amplitude response of the scope is within 3dB between DC and 12MHz. I would suggest a google search for some basics (although s.e.b. can be an appropriate forum too). Cheers PeteSArticle: 111265
Peter Alfke wrote: > These two have nothing to do with each other. > The 1 megohm is a dc load and means that you can measure dc voltages > with very little loading. > The 30 pF is in parallel, and loads down any ac input. How much it > loads down is determined by the driving impedance (nowadays often a few > 100 Ohms or even less in digital circuitry) and the frequency. > The 12 MHz describe the roll-off frequency seen, even when you drive it > with a perfect high-frequency signal. > > BTW, these specifications are ok for audio work, but be careful when > you debug fast digital logic. You might be driving blind... > Peter Alfke > ============== > On Oct 31, 1:56 pm, <nnn> wrote: >> Hi, >> I have seen a scope which has >> >> 1 Mohm 30 pF input impedance >> >> and frequency response >> >> 0 to 12MHz (+/- 3dB) >> >> My question: >> >> What is the difference between input impedance >> and frequency response? > A 12MHz scope isn't good even for low speed digital logic (with the way low speed is nowadays specified ;) The general rule of thumb is the scope should have at least 3 times the bandwidth of the measured signal, so 4MHz tops in this case - that's low speed nowadays. Cheers PeteSArticle: 111266
If you are adding 32 bits, can't you just use the next higher sum bit as carry? Maybe that's too obvious... Peter Alfke On Oct 31, 1:13 am, "Tim" <guene...@crypto.rub.de> wrote: > Hi there, > > I am working on a high-speed (500 MHz, Virtex 4, speedgrade -12) and > multi-precision adder (unsigned) capable to compute 256 bit additions > using the DSP48 slices. I am using a sequential adder design, thus > passing a chunk with the lowest bits to a DSP adder slice fist (each > chunk is only 32 bit for internal reasons), continuing up to the > highest bits of the input computing a 32 bit result each clock. When > implementing the carry logic between the chunks, I just came across > with its funny realization in the DSP slice. You can either use the > fabric to determine the carry yourself (1) or use the inverted MSB from > the output P[47]/PCIN[47] (2). Using the fabric (1) for carry > implementation requires the additional CARRY_IN register to preserve > the maximum clocking speed of 500MHz making it necessary to wait for > the carry until the computation of the next chunk can start. Option (2) > seems not to be applicable to my problem due to the inverted carry > signal which is useless for my scenario. Does anybody have a good > solution to this? > > Thanks already in advance! > Cheers, TimArticle: 111267
Austin Lesea <austin@xilinx.com> wrote: >nnn, > >Input impedance is the load the measurement places on the node being >measured. In the case you mention, a 1 megohm resistor, with a 30 pF >capacitor in parallel. If this is a 50 ohm impedance signal source, >then the 1 megohm is not affecting anything (1 megohm in parallel with >50 ohms is still very very close to 50 ohms), but 30 pF and 50 ohms is >about a 1 nanosecond time constant, so the capacitive load means the >probe itself will significantly load down signals above 100 MHz >(Z=1/2*pi*f*c = 53 ohms for 100 MHz !!!). In addition to this: If you use a 1:10 probe, the signal gets attenuated 10 times, but also the input capacitance of the oscilloscope gets attenuated 10 times. So instead of 30pf, your circuit will see a load of 3pf which decreases the load on the circuit under test 10 times. The downside is that you'll need to calibrate the capacitor inside probe. Most oscilloscopes provide a 1kHz square wave output to do this calibration (you have enough pointers to use Google to learn more on this subject). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 111268
PeteS wrote: > jacko wrote: > > nnn wrote: > >> Hi, > >> I have seen a scope which has > >> > >> 1 Mohm 30 pF input impedance > >> > >> and frequency response > >> > >> 0 to 12MHz (+/- 3dB) > >> > >> My question: > >> > >> What is the difference between input impedance > >> and frequency response? > > > > input impedance has to be driven, and so will prsent power transfer to > > the voltage mesurement equipment, and the 3db response of the line by > > wobble matching the graticule scale, will be the bandwidth. the line > > driver has its own input impedance, which can only be driven by limited > > power. > > > > ok? > > > > Huh? (in response to what Jacko wrote) > > x-posted to s.e.b where this is more appropriate. > > The input impedance of the measurement device specifies the load it > presents to the signal being measured. It is important to know for a > number of reasons. > > The +/-3dB response is specified as that is how bandwidth is normally > specified (-3dB is a half power point). In this case, it specifies that > the amplitude response of the scope is within 3dB between DC and 12MHz. > > I would suggest a google search for some basics (although s.e.b. can be > an appropriate forum too). > > Cheers > > PeteS And the OP can also look at the ultimate scope reference for newbies, "The XYZs of Oscilloscopes" from the folks at Tektronics. He'll have to fill out a quick questionaire before downloading: http://www.tek.com/Measurement/programs/301913X312631/ Cheers ChrisArticle: 111269
> Huh? (in response to what Jacko wrote) > > x-posted to s.e.b where this is more appropriate. Yes I know, my isp doesn't carry sci.electronics so I thought I'd try here. I'll use Google posting next time to sci.electronics. > > The input impedance of the measurement device specifies the load it > presents to the signal being measured. It is important to know for a > number of reasons. > > The +/-3dB response is specified as that is how bandwidth is normally > specified (-3dB is a half power point). In this case, it specifies that > the amplitude response of the scope is within 3dB between DC and 12MHz. > The point is this, if 12MHz is the 3dB cutoff, then we get an input impedance of 1/(2pi*f*c)= 1/(2*3.14*12M*30p)=442ohms where are these 442ohms are they between the plus and minus? and where is the 30pF are they between the plus and minus? what is so special about 442ohms?Article: 111270
John Adair wrote: > There isn't much choice in stand alone non-PCI chips... We used the STMicroelectronics STE100P PHY. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111271
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:ei8iuu$elg$1@lnx107.hrz.tu-darmstadt.de... > Peter Alfke <peter@xilinx.com> wrote: >> Have you tried the distributors, including DigiKey? >> Peter Alfke > > For the 5 Volt Xilinx series, none of the part is on stock at Digi, > and all have quite high minimum order > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- XCS30XL-4TQG144I (or C) are both in stock at Digikey but the -3 speed grades have the 60pc minimum order. Can you get by with the different speed grade?Article: 111272
nnn wrote: [...] > > > The point is this, if 12MHz is the 3dB cutoff, then we get an input > impedance of > 1/(2pi*f*c)= 1/(2*3.14*12M*30p)=442ohms > > where are these 442ohms are they between the plus and minus? and > where is the 30pF are they between the plus and minus? what is > so special about 442ohms? Yes, at 12MHz, the 30pf is looking like 442 ohms between the plus and minus. Yes, the 30p is between the plus and minus. It actually consists of distributed strays and real capacitance along the long path from the input socket to the first amplifier transistor. Yes ... They are both the same thing. 30pf acts like a 422ohms resistor up at 12.00MHz. Nothing remotely special about that 442ohms. You just can as validly say the input looks like 1/4Mohm at 20kHz. It's simply an indication of how quickly the loading effects increase when frequencies goes up and there's stray capacitance about. Thus the reason people pay out good money for those 10:1 divider probes, or the very expensive FET probes. (why oh why is it always "-3dB" when we're really interested in when the trace has shrunk to 70%. Is it only the immortal industry gods who are allowed to posess those special dB calibrated scopes? and then in deference, us mere mortals pretend we have them as well . )Article: 111273
First addressing the broader question: The A/D converter will have a noise floor specified in dBFS. This noise floor is what you would integrate over the filtered bandwidth to determine the total Signal to Noise Ratio. If you use a much higher bandwith, the total noise power will increase proportionately but you filter that back out and you're back to where you started. Typically the moise increases when you start to approach the device limits; using a 1 MS/s A/D at 1 kS/s versus 5 kS/s may make no difference but 500 kS/s to 800 kS/s may be noticeable. At particularly low frequencies, you may see an uptick in the noise floor as other noise sources start to invade your signal chain such as schott noise. On another subject, decimation could be a good thing. Imagine being able to evaluate your position on the road as you're driving at 60 frames per second video rates. Do you need to adjust your steering at 60 Hz? No. Your adjustments are partly dictated by the response of your system. There's no sense in providing 200 kS/s of adjustments to a system with 200 Hz response. You can, but there will be no gain as driving isn't improved with faster corrections. - John_H <will.parks@gmail.com> wrote in message news:1162334446.598731.231140@m7g2000cwm.googlegroups.com... > Thanks for your reply. It does seem like I sould start with an easy > filter first and work up to the filter I want to built. > > Something Tim Wescott said perplexes me, though. Filtering and then > decimating does sound like it will be computationally cheap, but I > wonder just what is the advantage of decimating a control variable? > > I'm fixed at 200kHz sampling, and the process I'm interested in > controling is at 200 Hz. Having 200 kHz bandwidth makes the noise > larger, (it should be a constant in volts per root hertz, so more > bandwidth means larger noise in volts). It seems to me that filtering > to 200 Hz is the correct way to reduce the bandwidth and thus reduce > the noise in volts. Minimizing the noise is an important concern for > controling the process quickly. > > It's not clear to me (and I'm sure this is my fault for not being > better informed) that decimating is an equivalent way of reducing the > bandwidth. What effect will decimating have on noise as expressed in > volts? > > And this brings up a broader question I've hand in the back of my mind. > Is it better to sample as high as possible and then filter down to the > desired bandwidth? Or is it better to sample as needed, and the gains > of sampling like mad and filtering like crazy are minimal. Forget the > practical aspects of limited memory and large files. > > I do have a hardware anti-aliasing filters. Your notes made some good > points, anti-aliasing is always an important concern! > > WillArticle: 111274
> Input impedance is the load the measurement places on the node being > measured. In the case you mention, a 1 megohm resistor, with a 30 pF > capacitor in parallel. If this is a 50 ohm impedance signal source, > then the 1 megohm is not affecting anything (1 megohm in parallel with > 50 ohms is still very very close to 50 ohms), but 30 pF and 50 ohms is > about a 1 nanosecond time constant, so the capacitive load means the > probe itself will significantly load down signals above 100 MHz > (Z=1/2*pi*f*c = 53 ohms for 100 MHz !!!). > > 'Bandwidth' is where the measurement "rolls off" or is no longer > accurately able to detect the amplitude at that frequency. > > '0 to 12 MHz +/- 3dB' means (to me) that the amplitude you measure can > be off by 2:1 anywhere in the 12 MHz bandwidth, which is really lousy (bad). I think the 12MHz is the 3 dB point. At this point the input voltage will only register on the scope screen as 50% of it's actual value. 3 dB must be with respect to a certain load, I suppose 50ohms or perhaps 75ohms i'm not sure, which doesn't make sense, as at 12MHz 30pF=463ohms
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