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To all,
I have created a Master peripheral and use SOPC builder to connect
to an SDRAM controller contained within the library provided for the
1s10 NIOS development kit. When I developed my Master peripheral, I
had used the Avalon Bus Specification manual and developed a state
machine that uses the signals required to interface with the Avalon
Bus (ie. WaitRequest, Read_N, readdata, readdatavalid etc...). The
Master peripheral state machine allows for either a READ or a WRITE.
However, I have noticed that no data is either written too or read
from the Avalon Bus (a.k.a. to the SDRAM). I have put some
additional ports, to trace the state machine states and I do verify
that I am cycling through the states correctly until the state
machine gets stuck in a given state. The LOC_POINTER output port
allows me to verify the state machine's current state condition. The
reason for my code being stuck is that my transition back to an IDLE
state depends on the Avalon Bus signals (ie readdatavalid or
waitrequest). If these don't change then I remain in the same state.
Furthermore when I validate this using the development board, the
values returned on the READ phase seems to always be a HIGH,
eventhough I am provisioning the contents of the memory with some
other value. It is apparent that this code is not working in either
WRITE or READ.
Does someone know who to probe within the SOPC environment what these
signals are? I want to ensure that the signals are at least getting
to the Avalon Bus interface. Any other suggestions on what I'm not
understanding with regards to the Avalon Bus?
For your reference, here's a copy of my Master Peripheral code (state
machine) in VHDL which I hope does not contain any invalid errors
based on my understanding of the Avalon Interface:
ENTITY Master_Memory_RW IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC; -- Reset state machine
RW_CTL : IN STD_LOGIC; -- Read = 1, & Write = 0
ACTION : IN STD_LOGIC; -- State machine status variable (1 = go to
read/write, 0 = do nothing)
WAITREQUEST : IN STD_LOGIC; -- Allows Master to wait until data is
available from Avalon Bus
READDATAVALID : IN STD_LOGIC; -- To handle cases of latency for Read
transfers from Avalon Bus; This will allow Master to perform other
tasks while waiting for read data.
INP_ADDR : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- User Input
Address INP_BA : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- User Input
Bank
INP_DATA : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- User Input Data
READ_DATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Input data line
BYTEENABLE_N : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
WRITE_DATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Output data
line
EXT_WRITE_DATA : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); -- Output data
line
EXT_MEM_ADDR : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Memory address
sent to Avalon Bus
EXT_BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); -- Bank Address to be
used with Byte Enable line for Avalon Bus
EXT_WRITE_N : OUT STD_LOGIC; -- Write enable bit to the Avalon Bus
EXT_READ_N : OUT STD_LOGIC; -- Write enable bit to the Avalon Bus
LOC_POINTER : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END ENTITY Master_Memory_RW;
-- Architecture Body
ARCHITECTURE main_rtl OF Master_Memory_RW IS
-- State Machine Definitions
TYPE EXCHANGE_STATE IS (INIT, IDLE, READ, WRITE, DATA_CAPTURE);
SIGNAL state, nextstate :EXCHANGE_STATE;
BEGIN
state_register: PROCESS (CLK, RESET)
BEGIN
IF (RESET = '1') THEN
state <= INIT;
ELSIF (CLK'EVENT AND CLK = '1') THEN
state <= nextstate;
END IF;
END PROCESS state_register;
rw_control: PROCESS (state)
BEGIN
CASE state IS
WHEN INIT =>
BYTEENABLE_N <= "1111";
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";
EXT_MEM_ADDR <= "ZZZZZZZZZZZZ";
EXT_BA <= "ZZ";
EXT_WRITE_N <= 'Z';
EXT_READ_N <= 'Z';
LOC_POINTER <= "0000";
nextstate <= IDLE;
WHEN IDLE =>
BYTEENABLE_N <= "1111";
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";
EXT_MEM_ADDR <= "ZZZZZZZZZZZZ";
EXT_BA <= "ZZ";
EXT_WRITE_N <= 'Z';
EXT_READ_N <= 'Z';
-- User action to either perform a READ/WRITE operation
IF ACTION = '1' THEN
LOC_POINTER <= "0010";
IF RW_CTL = '1' THEN
nextstate <= READ;
ELSE
nextstate <= WRITE;
END IF;
ELSE
LOC_POINTER <= "0001";
nextstate <= IDLE;
END IF;
WHEN READ =>
BYTEENABLE_N <= "0000";
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";
EXT_WRITE_N <= '1';
EXT_READ_N <= '0';
-- Validate if Avalon Bus has issued a WAIT state
-- Capture Data from Bus only when WaitRequest is
-- deasserted.
IF WAITREQUEST = '1' THEN
nextstate <= READ;
ELSE
nextstate <= DATA_CAPTURE;
END IF;
LOC_POINTER <= "0011";
WHEN WRITE =>
BYTEENABLE_N <= "0000";
WRITE_DATA <= "00000000000000000000000000000" & INP_DATA(2 DOWNTO
0);
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
EXT_WRITE_DATA <= "ZZZ";
EXT_WRITE_N <= '0';
EXT_READ_N <= '1';
IF WAITREQUEST = '0' THEN
nextstate <= WRITE;
ELSE
nextstate <= IDLE;
END IF;
LOC_POINTER <= "0100";
WHEN DATA_CAPTURE =>
BYTEENABLE_N <= "0000";
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_N <= '1';
EXT_READ_N <= '0';
IF READDATAVALID = '0' THEN
EXT_WRITE_DATA <= READ_DATA(2 DOWNTO 0);
nextstate <= DATA_CAPTURE;
ELSE
EXT_WRITE_DATA <= READ_DATA(2 DOWNTO 0);
--EXT_WRITE_DATA <= "ZZZ";
nextstate <= IDLE;
END IF;
LOC_POINTER <= "0101";
END CASE;
END PROCESS rw_control;
END ARCHITECTURE main_rtl;
Article: 71451"Ray Andraka" <ray@andraka.com> wrote in message news:40F5B093.70E01445@andraka.com... > I'm coming a little late to this conversation, but perhaps this has not been > considered. I sincerely doubt it is a configuration problem. Much more likely, you are not > coming out of reset at the end of configuration cleanly. The global reset must be Hi Ray, didnt notice some more replies to my post, thanks! well let me again explain the situation: its Virtex2, it has Microblaze with 32k BRAM, I am using both impact and Chipscope to download the bitstreams. The bitstream is known good, but in some cases after download one hard coded register is read by microblaze like giving wrong readback. The readback is constant for given configuration attempt. And the wrong read value persists after any number of hardware reset. Only goes away after new reconfiguration. The wrong read value comes from an verilog wire (that has an assigned constant value). I still do not see how the clocking or reset problem could do that. If the bitstream is loaded again the problem disappears. If the same bitstream is loaded from configuration memory there is never a problem. BRAMs are initialized, flip flops are initialized ok, or they are not relevant in the current problem. If the FPGA is not able to start with errors during actual configuration download, I would say this problem should never have occoured. Ray - if you notice my plea to give information about Xilinx Auto-CRC has been left un-responded. Virtex 2 bitstream does not include normal CRC as it used be in spartan II/E. Its replaced with AutoCRC. But there is no information how it is calculated anywhere in any public documents! Xilinx says that the old CRC was not good enough and did not catch all errors during configuration !! But I bet the new one is not much better! AnttiArticle: 71452
hmurray@suespammers.org (Hal Murray) wrote: > FPGAs generally need to have their program loaded at power up time. > That usually requires a few wires going in the back side. Where are > you going to get them on your PDA? Flash based FPGAs exist. They allow direct use after Power-up _and_ provide a possibility to reprogram the FPGA.Article: 71453
johnjakson@yahoo.com (john jakson) wrote in message > > I suspect that for large asics, a better aproach is to design clocked > subsystems with pseudo async interfaces so any no of free cycles can > pass by between clocked blocks. Its still really a synced design with > sync handshakes but more tolerant of delays that are in clock periods. > Still thats hard too. You're talking about "Asynchronous Communicatiing Processes" ... Systems that communicate over Clock domains by handshaked signals. Can save a lot of energy, if your system can be divided into parts running at different clock speeds. > Mind you with Xilinx talking up 500MHz and my timing reports giving me > many single wire nets in 1-4ns zone, maybe FPGAs will have to do same > thing. Using multiple independant clock domains and communicate via handshakes? I think lots of FPGA Designs are doing that already. Just look at the increasing number of available dedicated clock nets in large FPGAs. Someone gotta need them :-) Besides that, speed is not the only (wanted or unwanted) advantage of asynchronous designs. Power is another one. Have you recently taken a look into a state of the art PC? What good is the integration of the several million transistors of a Pentium4 when you need a cooling plate, the size of a big mans fist plus an extra fan? (Not to mention the power supply.) I wonder, besides any asynchronous stuff, if the same space could hold a bunch of (slow) low power SoC microcomputers, working together as known from grid computers. Remember the old days, when a '386 was just a bare PLCC on the PCB and from that time on all the higher speed and integration started cooling plates to grow like fungi on the motherbords. Well, it's starting to get philosophical here...but, I was just wondering. :-) > > Whats a C-Element? A special kind of latch designed for use in asynchronous designs (as mentioned in "Logic Synthesis of Asynchronous Controllers and Interfaces" (Springer, ISBN 3-540-43152-7) Unfortunately there is no commonly known terminology for asynchronous building blocks. regards Eilert BackhusArticle: 71454
Hello, I am getting follwing warning while I simulate (Post Lay out simulation) my design using Modelsim # ** Warning: */DFC1B SETUP Low VIOLATION ON D WITH RESPECT TO CLK; # Expected := 1 ns; Observed := 0 ns; At : 67127 ns # Time: 67127 ns Iteration: 4 Instance: /testbenchcmedmain/uut/mdec2_u2_reg_0 I was not getting this warning in Post Synthesis simulation but I am getting this warning in post layout simulation. I am using Actel Libro IDE for the synthesis and lay out. Is this warning related to setup time?Article: 71455
> AVnet Spartan-3 evaluation kit > ------------------------------ > > Pros: '400 part used :-) > Two oscillators, socketed > Lots of IO's available > Ethernet, VGA, PS2, RS232, Leds etc. > Could potentially be a PCI card > > Cons: Only 1 MByte RAM > Not clear if the memory is 32-bit wide > Price is $399 > Memory is 32 bits wide. I just got the usermanual from their FAE. And I'm going to buy it during the week ;) The great plus of this card is that it has a lot of stuff already on board.Article: 71456
Which EDK version do you use ? Could you paste your MHS file ?Article: 71457
Prasanth Kumar wrote: > > On Fri, 2004-07-16 at 12:03 +0200, Sylvain Munaut wrote: > > chuk wrote: > > > Any one know of the most efficient method (seed and space wise) of > > > implementing conversion of ones to twos and twos to ones compliment??? > > > Currently using addition and subtraction, but this is very > > > waist-full!!! > > > thanks > > > C > > I'd say with XOR and +/-1. > > The shortcut from doing 2's compliment is to invert the bits after the > first 1 starting from the right. So for example: > > 10011100 (original value) > VVVVV^The first 1 from the right > 01100100 (2's compliment) > > Thus you can create an chain of 'or' gates connected to 'xor' gates to > invert the bits after the first 1 bit starting from the right. It is > possible to do this work in parallel but without implementing it, I > don't know if it will actually be faster than a straightforward addition > since most FPGAs have fast ripple-carry adders. I don't think this method is really a short cut other than if you are doing it using paper and pencil. This is the same calculation that the inverters and adder does. The OP is really just trying to find a way to not have to do the addition, but in reality there is no way around it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71458
Hello I'm searching for a FPGA board for about $500 with an "audio in" and "audio out" port... adequate for audio processing applications. I thought of a Virtex II fpga, but can be another one from XILINX.... Can anyone recommend a board like this ? Regards, Timo DammesArticle: 71459
Hi Drew, This is taken from the Quartus II online help and should answer your questions. This is copy-n-paste from the Quartus II Help file. (do "Search" for "simulating bidirectional pin" from the Quartus II Help) ======================================================================== Guidelines for Simulating Bidirectional Nodes See Also Using Vector Files with the Simulator When simulating a vector file that contains bidirectional nodes, use the following guidelines: A bidirectional node is represented in a Vector Waveform File (.vwf) by two channels: one channel represents the input to the bidirectional node, the other channel represents the output from the bidirectional node. You can enter the input channel into the VWF by adding the bidirectional node to the VWF using the Node Finder dialog box, or you can insert the bidirectional node into the VWF using the Insert Node or Bus command (Edit menu). If the Automatically add pins to simulation output waveforms option is turned on, the Simulator automatically creates the corresponding output channel for the bidirectional node, named <bidir node name>~result, after simulation is complete. This channel contains the logic levels of the output channel during simulation. Alternatively, you can manually create the output channel and specify the expected logic levels for the output channel. If you manually create the channel, you must name the channel <bidir node name>~result, and follow the additional guidelines below about specifying the logic levels of bidirectional nodes. Hope this helps. - Subroto Datta Altera Corp. "Drew" <dhruvish@gmail.com> wrote in message news:ad2011c0.0407160527.71e3fbac@posting.google.com... > Hello all, > > I am kind of confused how is bidirectional pin displayed in the > Waveform Simulation. In my waveform file I have A as an bidirectional > pin but when I run simulation one more pin name appears called > A~result. I guess that's the output and the other one which is > displayed as A is input in simulation. But I need to know more like, > are those pins supposed to be displaying same waveform? If not which > one is a true waveform. I am trying to find some help on this in > Quartus but I cannot see it. > > Your help is appreciated > DrewArticle: 71460
Hi, I have the following question concerning PLL use in Altera Cyclone devices: In normal mode it said that the PLL phase aligns the input reference clock with the clock signal at the ports of the registers that is clock used for FPGA internal registers. Functional simulation shows that PLL input clock (30MHz) and PLL output clock (90MHz) (which is NOT used for I/O pin!) are phase aligned that is three clock periods of Clock_out fit into the period of Clock_in. But when doing timing simulation Clock_out is not phase aligned with the input clock but there is a delay. But why? I have compensated the PLL for the Clock_out so why is there a delay at all in the simulation? I would appreciate your help. Kind regardsArticle: 71461
ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407182337.570d1070@posting.google.com>... > johnjakson@yahoo.com (john jakson) wrote in message > > > > > I suspect that for large asics, a better aproach is to design clocked > > subsystems with pseudo async interfaces so any no of free cycles can > > pass by between clocked blocks. Its still really a synced design with > > sync handshakes but more tolerant of delays that are in clock periods. > > Still thats hard too. > You're talking about "Asynchronous Communicatiing Processes" ... > Systems that communicate over Clock domains by handshaked signals. > Can save a lot of energy, if your system can be divided into parts > running at different clock speeds. > > > > > Mind you with Xilinx talking up 500MHz and my timing reports giving me > > many single wire nets in 1-4ns zone, maybe FPGAs will have to do same > > thing. > Using multiple independant clock domains and communicate via > handshakes? > I think lots of FPGA Designs are doing that already. > Just look at the increasing number of available dedicated clock nets > in large FPGAs. Someone gotta need them :-) > Besides that, speed is not the only (wanted or unwanted) advantage of > asynchronous designs. Power is another one. > Have you recently taken a > look into a state of the art PC? What good is the integration of the > several million transistors of a Pentium4 when you need a cooling > plate, the size of a big mans fist plus an extra fan? (Not to mention > the power supply.) My family is all too aware of AthlonXP heat output, looking to kill it one day with a Transputer or 2, but 1 should suffice. After all it only surfs & plays net TV. > > I wonder, besides any asynchronous stuff, if the same space could hold > a bunch of (slow) low power SoC microcomputers, working together as > known from grid computers. Yes, thats what I am working on, Inmos did this 20yrs ago, probably 20yrs too early. I keep doing the same engineering calculation, Intel ups the freq of x86 by 30x and gets 30x perf over the p100. BUT transister count also went up (big no) and heat,noise,space too. That used to be called bad engineering. Notice that bridge builders today build lighter bridges today than IKB did many yrs ago. The intel supporters will pooh pooh that analysis but if you have distributed cpus & local memory and know how to use them (Transputer people do), you also get far more total memory b/w than pushing it all up 1 pipe. Also no reason to be limited to std DRAM, theres RLDRAM available with 20n RAS times. And with MTA architecture, branching & memory delays are better hidden than single threaded cpus with ever bigger caches. > > Remember the old days, when a '386 was just a bare PLCC on the PCB and > from that time on all the higher speed and integration started cooling > plates to grow like fungi on the motherbords. > Yes been along time since I saw computer fanless. my old BBC & QL still got quite warm though! > Well, it's starting to get philosophical here...but, I was just > wondering. :-) > > > > > Whats a C-Element? > A special kind of latch designed for use in asynchronous designs (as > mentioned in "Logic Synthesis of Asynchronous Controllers and > Interfaces" (Springer, ISBN 3-540-43152-7) > Unfortunately there is no commonly known terminology for asynchronous > building blocks. > > regards > Eilert Backhus regards johnjakson_usa_comArticle: 71462
[snip] > >> Xilinx says that the old CRC was not good enough and did not catch all > >> errors during configuration !! But I bet the new one is not much better! > >> > >> Antti > > > > If I read this right, you are saying that read-back does show the > >error, and that error persists on many read-backs until re-config ? > > Good question. Antti, when you say that "readback" is consistent, are > you referring to the MicroBlaze's readback of that one register, or > are you saying that you are seeing an error when you perform a > bitstream readback? > > Bob Perlman > Cambrian Design Works Microblaze starts, i.e. DCM works, BRAMs init ok, etc... I press HW reset and RTL revsison registers (hard-wired) reads 23.27 as example not 1.21 as it is wired to return. this wrong readback 23.27 persists after any number of hardware reset (reset to microblaze and all registered logic). after reconfing the problem is away. Some other time the wrong readback maybe differently wrong but again it remains constant until reconfig. And yes it looks like there are chances that V2 bitstream can be starting even if it had errors during download. And yes i would like xilinx to document AutoCRC function ;) AnttiArticle: 71463
Does anyone have a simple way to embed the date and time that a module is compiled into a wire or register in Verilog? I could use a Perl script to create an `include file with the proper `define statements, but I'm wondering if anyone has a cute way to do this purely in Verilog. FYI - I'm using Xilinx XST for synthesis. Thanks! John PArticle: 71464
Hi everybody,
I would like to know if someone has already build a IDE or ATA controler
on a FPGA (any kind Xilinx or Altera) ? The contoler has to been
fully compliant at least with the with the ATA 4 normalisation.
If yes what are the conditions to access to the code ?
Thanks
Article: 71465john jakson wrote: > > ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407182337.570d1070@posting.google.com>... > > johnjakson@yahoo.com (john jakson) wrote in message > > > > > > > > I suspect that for large asics, a better aproach is to design clocked > > > subsystems with pseudo async interfaces so any no of free cycles can > > > pass by between clocked blocks. Its still really a synced design with > > > sync handshakes but more tolerant of delays that are in clock periods. > > > Still thats hard too. > > You're talking about "Asynchronous Communicatiing Processes" ... > > Systems that communicate over Clock domains by handshaked signals. > > Can save a lot of energy, if your system can be divided into parts > > running at different clock speeds. > > > > > > > > > Mind you with Xilinx talking up 500MHz and my timing reports giving me > > > many single wire nets in 1-4ns zone, maybe FPGAs will have to do same > > > thing. > > Using multiple independant clock domains and communicate via > > handshakes? > > I think lots of FPGA Designs are doing that already. > > Just look at the increasing number of available dedicated clock nets > > in large FPGAs. Someone gotta need them :-) > > Besides that, speed is not the only (wanted or unwanted) advantage of > > asynchronous designs. Power is another one. > > > Have you recently taken a > > look into a state of the art PC? What good is the integration of the > > several million transistors of a Pentium4 when you need a cooling > > plate, the size of a big mans fist plus an extra fan? (Not to mention > > the power supply.) > > My family is all too aware of AthlonXP heat output, looking to kill it > one day with a Transputer or 2, but 1 should suffice. After all it > only surfs & plays net TV. Then why don't you dial down the clock and save all that heat? The Athlon will run at lower voltages as well when you slow it down. The entire system can run cooler and you might even be able to get rid of the fan altogether. I did that with a Celeron. Of course I dialed it back up after I ran the test. I need the speed for FPGA work. > > I wonder, besides any asynchronous stuff, if the same space could hold > > a bunch of (slow) low power SoC microcomputers, working together as > > known from grid computers. > > Yes, thats what I am working on, Inmos did this 20yrs ago, probably > 20yrs too early. I keep doing the same engineering calculation, Intel > ups the freq of x86 by 30x and gets 30x perf over the p100. BUT > transister count also went up (big no) and heat,noise,space too. That > used to be called bad engineering. Notice that bridge builders today > build lighter bridges today than IKB did many yrs ago. > > The intel supporters will pooh pooh that analysis but if you have > distributed cpus & local memory and know how to use them (Transputer > people do), you also get far more total memory b/w than pushing it all > up 1 pipe. Also no reason to be limited to std DRAM, theres RLDRAM > available with 20n RAS times. And with MTA architecture, branching & > memory delays are better hidden than single threaded cpus with ever > bigger caches. The only problem is the same one Motorola ran into, all the code is written for the Intel architecture. You can say you have a better solution, but it really is not practical for a typical app. One CPU (even a monster Intel with heatsink) is much easier to design a system with than 30 Transputers. Of course you get higher memory bandwidth, you have a dozen more pins to memory! > > Remember the old days, when a '386 was just a bare PLCC on the PCB and > > from that time on all the higher speed and integration started cooling > > plates to grow like fungi on the motherbords. > > > > Yes been along time since I saw computer fanless. my old BBC & QL > still got quite warm though! I bought a Walmart special with a Via CPU (I forget the name of it). It was not fanless, but I unhooked the fan and it idled nearly at room temp and only got up to about 55-60C when running a heat test program. That is a little hot, but with a better cooling design I believe it could be kept under 50C. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71466
David wrote: > Hi everybody, > > I would like to know if someone has already build a IDE or ATA controler > on a FPGA (any kind Xilinx or Altera) ? The contoler has to been > fully compliant at least with the with the ATA 4 normalisation. > > If yes what are the conditions to access to the code ? > > Thanks > opencores.net Never tried it myself thoughArticle: 71467
Fellow comp.arch.fpga users, I'm trying to obtain information die sizes for various Xilinx FPGAs in the Virtex, Virtex-II Pro, Virtex-II, and Spartan-III families. I am using this information in my Master's thesis to approximate the physical lengths of long wires, and how they have been scaling with delay. Any pointers will help. Thanks. -RyanArticle: 71468
Initially programming by Parallel Cable 4 from parallel port to header on the board. We are hoping to have a more elegant and cheaper solution in a few months. John Adair www.enterpoint.co.ukArticle: 71469
Cost isn't set yet but likely to be £299 / E499 / $ 499. We have not set a specific production date for these yet. We would like to put a few XC3S1500 specific enhancements into the design over and above the larger chip size. However if there is enough demand we will accelerate the production cycle but this may be limited by delivery times on XC3S1500 silicon. We now have a rolling delivery of XC3S400 so once we are past the initial demand Broaddown2-400 will be a stock item. Broaddown2-1500 should be become a stock item in about 3-4 months on the current schedule. If you need a solution earlier contact me offline and I will see what can be done. -- John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.ukArticle: 71470
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<cc234l$2on$1$830fa7b3@news.demon.co.uk>... > >> "Daragoth" <daragoth@kuririnmail.com> wrote in message > >> news:317379a8.0406302118.32829ee1@posting.google.com... > > >>> -The most important thing is that it all fits within a 40 mm x 30 > >>> mm x 10 mm volume or less. > > Should be possible. The boards here: > > http://www.rockylogic.com/files/AntGuts_LoRes.jpg > > are 50mm x 30mm. The one on the left has an XC2S50E on the reverse > side, and the power supply is a switcher. The other board has an > XC2S30 on the reverse side, and a linear power supply. This one is a little larger (51mm x 44mm) but also less expensive: http://shop.trenz-electronic.de/catalog/product_info.php?products_id=43 It was designed in a way that you can cut off one of the B2B connectors to obtain an area of about 51mm x 31mm and still have 60 user I/Os. Kolja SulimmaArticle: 71471
I am looking for boards that are comparable to the ADM-XRC-II. It is a high performace PMC designed for supporting development of applications using Xilinx's Virtex-II. Here is a link to AD's product: http://www.alpha-data.com/adm-xrc-ii.html I am not too familiar with these sort of devices, and I was wondering if anyone could recommend some alternative boards.Article: 71472
Thanks a lot Subroto, I am having one more doubt now. If I place an Oscilloscope on the Bidirectional Pin, what would I see? Will it be any form of combination of A and A~result or it will be A~result only. Can I use MAX3000 family EPLD for this sort of application? Thanks, DhruvishArticle: 71473
The Memory Corner on xilinx.com ( http://www.xilinx.com/products/design_resources/mem_corner/index.htm ) has good information on timing analysis for ZBT designs, along with some new Spartan-3 app notes. Most of the data sheet and speed file parameters are relative to the pins on a given logic block (including device pins for the IOB block). An example is Tiockp, which is measured from the clock input on the IOB to the output pin. Some parameters are between two device pins, such as Tickofdcm, which includes the clock input IOB, the path through the DCM and the clock routing, and finally the Tiockp block delay to the output pin. If that's the path you're going to use, it's much more meaningful to have all the delays added together for you than just looking at individual block delays. You are correct that typically higher drive provides higher performance, but there can be exceptions. Note that we have made some modifications to these numbers in the latest speed file and for your device the 16 mA and 24 mA outputs are slightly faster than 12 mA. The speed file is always the most specific and the most accurate, and was just updated in v1.32 from Advance for the XC3S200 -4, which is now in production. Andrew wrote: > Hi, > Im calculating the memory bandwidth achievable when interfacing a > Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT > SRAM (128k x 36bit). In general I have found the Spartan 3 datasheet > very good (I like the text/description column in the switching > characteristics section of the datasheet) but in the following > instance I am stuck (probably due to my lack of understanding rather > than the datasheet.) > > To do the memory bandwidth timing calculation I need to know the > following FPGA IOB timing: > 1)the clock to out delay for the IOB OFF(output flipflop) and > 2)setup time for the IOB IFF(input flipflop). > > Finding 1) from the datasheet: > I found table 12 on page11 of the DC and switching characteristics > section. The "pin to pin clock to output time for the IOB output path" > is Tickofdcm = 2.59ns. (DCM in use) But then when I look deeper into > the datasheet I also find table 17 on pg 16 called Timing for the IOB > output path. Tiockp gives a clock to output time of 4.18ns. What is > the difference between these two timing paramaters? What I want to > know is the time from a rising edge on OFF's OTCLK to the data bit > appearing at the FPGA Pin on the PCB. > > Finding 2) from the datasheet: > Table 13 on pg 12 is called "pin to pin setup and hold times for the > IOB input path". Tpsdcm = 2.72ns is the relevant parameter. > But then table 14 "Setup and hold times for the IOB input path" show > Tiopick = 1.32ns. Which of these two timing parameters should I use? > what is the difference? > > Notes: > The IO standard used is LVCMOS25 > I am using Spartan 3 datasheet DS099, march 4, 2004. > > I also noticed an interesting thing in table 19, output timing > adjustments for IOB, LVCMOS25 FAST. The 16mA and 24mA drivers are > slower than the 12mA drivers? I expected them to be faster. > > Also noticed the datasheet seems to be "advance product specification" > which according to the datasheet is described as "These specifications > are based on simulations only...." Scary stuff. Is there a more > appropriate place I should be getting my timing numbers from, e.g. > download latest speed files and use timing analyzer? Is the > documentation just out of date? They must have characterized the > production silicon right? > > Regards > Andrew -- Marc Baker Xilinx Applications (408) 879-5375Article: 71474
John, No, I've always done this with Perl. I've also used Perl & Data2MEM to include the P&R time into the download bitstream. The times are loaded into a BlockRAM which is the character storage for my debug VGA driver. Very useful when working with those (sometimes forgetful, bless 'em) software guys! Cheers, Syms. "John Providenza" <johnp3+nospam@probo.com> wrote in message news:349ef8f4.0407190727.2a35fff9@posting.google.com... > Does anyone have a simple way to embed the date and time > that a module is compiled into a wire or register in Verilog? > > I could use a Perl script to create an `include file with the > proper `define statements, but I'm wondering if anyone has > a cute way to do this purely in Verilog. > > FYI - I'm using Xilinx XST for synthesis. > > Thanks! > > John P
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