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chi_huageng@yahoo.com (chi) wrote in message news:<232ce803.0403030517.24169493@posting.google.com>... > Hello, > > I'm using Nios Development Kit (general purpose, APEX). Is it > outdated? It seems hard to find reference. All references are talking > about Cyclone and Stratix. I even could not find the software > development tutorial for APEX. I'm new to this tool suit. Does anyone > have good suggestions to shorten time to hand on? Thanks! > > Chi Hello Chi, The Nios Software Development Tutorial is available on the Altera website at: http://www.altera.com/literature/tt/tt_nios_sw.pdf along with the associated files. The tutorial and files are also installed with the Nios product in the <nios install dir>\tutorials\Nios_HW_Tutorial_Apex_20KE200. In addition the Nios Hardware Tutorial is also availabe on the Altera literature page. Best Regards, SabrinaArticle: 67501
I had much bad experience dealing with 6000s...my designs tend to use only three thousands of slices but i had to do partial reconfigurations with it...it always took more than 7 hours just to do one P&R. those got-nothing-to-do senior engineers always complain as if it was my mistake,,, :-( just think about it, a wire route through from left to right of a 6000 gives a delay nearly 10ns, so if your inputs & outputs are far apart on the silicon, it will take long time to find optimal routing...Try to locate IOs close to each other, give an exact location for each register with LOC & do a floor planning, set reasonable timing. Kelvin "Hunter" <imad694@yahoo.com> wrote in message news:705e663d.0403092330.115c7ac@posting.google.com... > Hi, > > I have written a very small design to control some LEDs in order to > check out the XC2V6000-4ff1517 FPGA on a board that I am bringing up. > > The code has only 92 signals that are to be routed. The Synthesis, > Translation and mapping steps take just 25 seconds. However, the PAR > takes about 20 minutes. I would like to know what the ISE6.1 (SP3) is > doing in all that time? > > Any suggestion to improve this will be very welcome. > > Thanks, > HunterArticle: 67502
WebPACK downloads back to v3.3 are available at http://www.xilinx.com/ise_classics/ Sumit Gupta wrote: > My design which used to work fine with ISE 4.2 is not working at all > with ISE 6.2. While I debug it to figure out what went wrong, is it > possible for people to download old version of ISE webpack from > somewhere ? > > Sumit > ------ > http://www.c-nit.net -- Marc Baker Xilinx ApplicationsArticle: 67503
Thanks Salman and Joshua. It was helpful. Kumar "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2004.03.05.21.50.17.149660@polybus.com>... > On Fri, 05 Mar 2004 16:22:45 -0500, salman sheikh wrote: > > > kumar wrote: > >> Hello everyone, > >> > >> I have a verilog design that is tested and works properly with > >> ModelSim simulator. I have synthesized it with Xilinx Project > >> Navigator tool using XST. I want to verify if the design works > >> properly(after synthesis) before I can go on with downloading the BIT > >> stream onto a Xilinx FPGA board. > >> I could not find a way to do this. Could anyone please help me in this > >> matter. > >> Thanks a lot, > >> Kumar > > > > Just simulate it with the same testbench you used to test the verilog > > design (i.e. use the post place and routed generated verilog file with > > back-annotated timing file (sdf file) with your testbench and you should > > then now how good it really works. > > > > Salman > > ngd2ver converts an ngd file back to verilog, you can plug the gate level > verilog file back into your testbench. Simulating a gate level netlist is > painfully slow especially with a slow simulator like ModelSim. Unless you > suspect that you've had a synthesis error there is no reason to do a gate > level simulation. Even if you suspect a synthesis problem you are better > off trying to narrow it down using ChipScope then trying to do a gate > level simulation.Article: 67504
rickman <spamgoeshere4@yahoo.com> wrote in message synth. > snipped > OH!!! My experience is that the synth tools do a lousy job of > estimating total delay. You can expect your routed delays to be twice > that or more. If you are seeing 400 MHz post synth, you will be lucky > to get 200 MHz after routing. If you don't floorplan well, you may see > <100 MHz. > Hi Rickman I spent much more time on the PR side. Without any effort the Post-Place & Route Static Timing report gives the following using 6.13 again. ================================================================================ Timing constraint: Default period analysis for net "ck_BUFGP" 6233 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 8.030ns. -------------------------------------------------------------------------------- which is pretty poor at 125MHz. But then the ucf is very partial and no effort spent on the planning, just default everything. A similar experiment on just a registered 12b adder gives 5.5ns or 170MHz when 1st synth est is also 311MHz. IE smaller blocks no planning gives 50% of synth est. On the v2pro, results much better, closer to 215MHz for cpu datapath v 304MHz est, ie 70% also no floorplanning. This block has far too many IOs for any sp3 for Webpack to complete to PR. I was under the impression the synth reports might have been weighted down to include some wiring penalty reflecting typical design as most ASIC synth setups usually do, but seems not. sp3 synth estimate is esp optimistic, seems to give same synth results as v2pro but 60% the PR results. The 6.2 edition is even more optimistic as I said but I am sure there's an anomoly there too. While the cpu is incomplete, many of the modules I might like to P/R also have too many 32b busses that break the sp3 pad count. The v2pro PR lets me try these cells to completion but only adds to false confidence. Looks like V2Pro can with some effort reach 70% of synth est, maybe more with ucf and practice. looks like sp3 only reach 50% of est, maybe more with ucf. Just lots more work, and not as cheap/mip as 1st hoped. I will have to learn alot more about PR on individual blocks into tiles and then glue them together at a higher layer if thats possible. When the architecture is finally checked out I will be able to break it up into smaller pieces and see what can be achieved for all the families. I think I spent too much time reading the Xilinx glossies instead of tring all the tool options, but I guess 215 isn't too shabby for v2pro to start. regards johnjakson_usa_comArticle: 67505
Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0403121110.44e2ece3@posting.google.com>... > johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0403111600.2664b309@posting.google.com>... > > > `define wid 4 > > > > module Add32( > > input ck, input [`wid-1:0] a,b, output [`wid-1:0] o); > > > > reg [`wid-1:0] ra,rb,rz; > > assign o = rz; > > > > always @(posedge ck) > > begin > > rz <= ra+rb; ra <= a; rb <= b; > > end > > endmodule > > Why are you using `define rather than parameters? > > --a Just a 1 min test, code isn't part of cpu. Params used in some places but theres not much code in total.Article: 67506
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0403120150.54c15479@posting.google.com>... > johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0403110735.71e1b6e8@posting.google.com>... > > jon@beniston.com (Jon Beniston) wrote in message > > > > The timing report is essentially > > > > same as before, no special warnings but some improvement in compile > > > > time I was looking for. > > > > > > Is that post-synthesis or post-layout? > > > > > > > Post synth. > > As another poster has mentioned, expect to see a big drop off in > performance after layout. I have noticed that sp3 synth results are > significantly more optimistic than for other archs. As I am finding also. Why would Xilinx set up the synth files to be so far out of line for sp3 though, not always possible to PR blocks when port count is way over sp3 pad count even 208. Well atleast the datapaths went through PR at 215MHz on the v2pro -7 with no floor planning, if I can get that to 250Mhz guess I'd be happy with that. Mind you I should have dug alot deeper before posting 300MHz, it will probably be 200+ for v2pro instead. > > Don't have Symplify or full ISE budget, but would gladly accept a free > > license if anyone is listening. email at bottom. > > Most EDA companies will let you do a months eval for free. Very handy > if you time it just right. > I will when time permits. > > Not a big fan of GPL. If no $ licenses are forthcoming, I will fold > > the them both into MIT/BSD and let the world rip into it. > > I meant offer it under dual licenses. One GPL the other $$$. If you > use the LGPL there is less chance that people will be willing to pay. > I'm all for open source, but there still should be a way to earn a > decent living.. > Agreed regards johnjakson_usa_comArticle: 67507
Hello,
I'm looking for a prototyping board designed for complete system
development that is fairly inexpensive. I'm looking for a board with
video, audio, USB, PS/2, serial, ethernet, SDRAM, etc. I'm also
looking for a board that will give relatively good performance. I
first looked to BurchED's board but the promised Spartan3 version has
yet to come out (contrary to last year's late december estimation) and
as conversion rates between the US and Australia are going up, the
board, complete with needed expansion modules, would total about $700
(this would be using a Spartan2 and not include SDRAM, USB, ethernet,
or audio). BurchED says the Spartan3 version (if it's still going to
be released) will cost even more. After a lot of looking around I
found MJL and their Cyclone/Stratix Development Kits. They are priced
between $700-$800 and offer all of the required features plus room for
expansion (only drawbacks are the 10BaseT ethernet and no readily
avaliable IDE expansion module {like BurchED}). Although a good
prototyping board is essential I want to make sure that it isn't
crippled by a FPGA with poor performance. I haven't had much
experience with modern FPGA devices and have had no experience at all
with any of Altera's offerings.
*Could someone please give their input on to which FPGA (device
family) seems to be the best idea for the development of a system
(capable of loading an operating system from disk and executing
applications) centered around a soft RISC processor?
*What level of performance could I expect (comparison between say the
FPGA and a hard CPU of the past)? What type of CPU clock rate do you
think I could expect to get (comparison between say VirtexII,
Spartan2/3, Cyclone, Stratix)?
*Both Xilinx and Altera seem to make perfectly capable devices. If I
were to go with Altera (and most likely the MJL board) would you
reccomend the extra money to go with the Stratix (plus SRAM and more
room for expansion)? If I went with Xilinx (and most likely the
BurchED board) would you reccomend waiting for the Spartan3 or is the
Virtex family worth the extra money?
*Also, if anyone knows of a better fpga/board combination, please let
me know!
I'd appreciate any input,
Thanks!
Article: 67508"Sergio" <sgarcia_castillo@hotmail.com> wrote in message news:57a9a185.0403121213.5395570c@posting.google.com... > Hi , does any body know how many uAmps a single input configured as > LVTTL for Spartan-3 families sink from the driver in both, high and > low levels????... > > thank you > > Sergio The input is supposed to be capacitive, only. So, per the spec, the steady-state current should be in the microamps (or lower). HOWEVER, we are using Spartan-3's (engineering samples) and they seem to be drawing milliamps, on banks with VCCO=3.3V. That is, an output must sink milliamps of current (as if there's a strong pullup at the Spartan input). I'm not directly involved with this particular design so I don't know if this is indeed true (I suspect it is, from what I've seen). Xilinx has stated that the ES Spartan-3's were not designed to run with VCCO at 3.3V (for LVTTL), but will withstand it for a certain length of time. The production parts have been modified to support this. Perhaps this is the reason why (assuming it's true). Austin? Peter? Any comments? BobArticle: 67509
John wrote: > > Hello, > I'm looking for a prototyping board designed for complete system > development that is fairly inexpensive. .... > *Could someone please give their input on to which FPGA (device > family) seems to be the best idea for the development of a system > (capable of loading an operating system from disk and executing > applications) centered around a soft RISC processor? You might want to ask John Jakson about that :) He seems to be working on exactly that. Personally, I think you will find more difference in the tools (don't ignore this very important issue) and availability than you will any real issues of performance. Your design and target optimizations will dictate the performance much more than the device family you choose. So pick one based on other issues than performance, then make sure you get your hands on good tools and learn to work with the parts and the tools in an optimal manner. > *What level of performance could I expect (comparison between say the > FPGA and a hard CPU of the past)? What type of CPU clock rate do you > think I could expect to get (comparison between say VirtexII, > Spartan2/3, Cyclone, Stratix)? Again, talk to John Jakson. He just learned the difference between a synthesis speed report and a P&R speed report. :) But I would expect to see a 5x to 10x difference between an FPGA and an ASIC in the same technology. When you ask about the "past", that all depends on how far in the past. John seems to be finding his designs working between 200 and 300 MHz. At those speeds, you will find memory bandwidth will be the bottleneck. Remember, you can put a lot of logic on these chips, but you won't ever get much cache in comparison to the 512 MB and 1 GB they are making today in CPUs. > *Both Xilinx and Altera seem to make perfectly capable devices. If I > were to go with Altera (and most likely the MJL board) would you > reccomend the extra money to go with the Stratix (plus SRAM and more > room for expansion)? If I went with Xilinx (and most likely the > BurchED board) would you reccomend waiting for the Spartan3 or is the > Virtex family worth the extra money? You didn't say how much extra money it costs! In general, I don't think you will find your designs will fit or run better in the higher priced families. The high dollar parts mainly are either larger, or they have special features (like very high speed serial IO) that you likely don't need. Just make sure your FPGA is large enough for the design you are building. If you want to wait for the Spartan 3, be prepared for a long wait. They have been promising chips for months now and most people are still waiting. Don't blame BurchED, they likely aren't getting the chips they were promised. You might consider building a board that has an FPGA and can plug into a socket A, 478 or one of the other standard x86 sockets. Then you can run your CPU in any motherboard. Go with a socket 940 and you can design your own memory controller! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67510
hello,I am a user of ML300, and have one question.
I wanna write some data to the PLB DDR SDRAM from my IP which is master of OPB bus.
the following is my code:
assign IP2Bus_MstWrReq = write_req ;
assign IP2Bus_MstBusLock = write_req ;
assign IP2Bus_MstBE = write_req ? 4'b1111 : 4'b0000;
assign IP2Bus_Addr = write_req
? {16'b0,low_addr,2'b00}
: 32'b0;
assign IP2IP_Addr = write_req ? 14'b01000000000010 : 14'b00000000000000;
FDRS fdrs_write_req(
.C (Bus2IP_Clk),
.D (write_req),
.R (Bus2IP_MstLastAck),
.S (~empty),
.Q (write_req)
);
low_addr is initialized by zero, and at the posedge of Bus2IP_MstLastAck, increment it.
always @( posedge Bus2IP_MstLastAck or posedge Bus2IP_Reset )
begin
if( Bus2IP_Reset )
low_addr = 14'b00000000000000;
else
low_addr = low_addr + 1 ;
end
so the range which should have data is from 8'h00000000 to 8'h0000FFFF.
Now there is some trouble!
there is no data in the first address of ddr (8'h00000000),
but in the address 8'h00010000 of ddr , there is valid data.
Please tell me , what is wrong ?
Article: 67511Stewart Smith wrote: <snip> > Thank you for taking time to respond > Have looked into the link you suggested and, no problem for me to use > this type of device, in fact they have them in stock at uni which is > handy. This definitely seems a step in the right direction. You could also check if they have, or can easily get (Digikey?), the Atmel ATF750CL. http://www.atmel.com/dyn/resources/prod_documents/doc0776.pdf That has the same package(s) and tool flow as the 20V8 you use now, but has 20 D/T registers, and allows multiple clocks. (Also lower standby, but that's not likely to be too critical). -jgArticle: 67512
Stewart Smith wrote: <snip> >>Look into Rate Multipliers : These have Fo = N/Base output, so >>a 4 bit binary one can start at 1/16 fi, and step thru 2/16,3/16 >>up to 16/16 Fi, in linear frequency steps >> >>Rate Multiplier info is not easy to find, so here is one ref : >>http://focus.ti.com/docs/prod/folders/print/sn7497.html >>-jg > > Thank you for taking time to respond > Have looked into the link you suggested and, no problem for me to use > this type of device, in fact they have them in stock at uni which is > handy. This definitely seems a step in the right direction. I was meaning that you use the device as a Logic example/Template, and code what you need in the PLDs... -jgArticle: 67513
Hi Pszemol, In the <project>.map.rpt file there is a table that translates between state names and states, something like this: +-------------------------------------------+ ; State Machine - state ; +-------------------------------------------- ; Name ; state~22 ; state~21 ; state~20 ; +----------+----------+----------+----------+ ; state.S0 ; 0 ; 0 ; 0 ; ; state.S1 ; 1 ; 0 ; 1 ; ; state.S2 ; 1 ; 1 ; 0 ; +----------+----------+----------+----------+ ... what this says is that when (state~22, state~21, state~20) is (000) we are in state.S0; when (state~22, state~21, state~20) is (1, 0, 1) we are in state state.S1, and so on. Our state machines are always one-hot encoded, so another way of looking at the same information is to say that when state~22 is 0 we are in state.S0; when state~20 is 1 we are in state.S1, and when state~21 is 1 we are in state~21 (one-hot with first bit inverted). Hope this helps. - Subroto Datta Altera Corp. "Pszemol" <Pszemol@PolBox.com> wrote in message news:c2s7fq.640.0@poczta.onet.pl... > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:c2s00e$jo7$1@news.netpower.no... > > There are also often occasions where a module (VHDL, Verilog or schematic) > > produces outputs that are not used in the rest of the system, or which have > > inputs that don't get used in the module, but you want to keep them for > > consistency or flexibility. Is there any more general way to disable such > > warnings? > > Funny you have mentioned this one because I have a lot of worrying warnings > messages like this one (I have exchanged the long path to the chip with X mark): > > "Warning: Reduced register X|rxcntlsm:u1|state~34 with stuck data_in port to stuck value GND" > > The module 'rxcntlsm' is a state machine for UART receiver written in VHDL. > During the synthesis, Quartus unfortunately converted state names to numbers and > I am confused what states are creating problems, or are they problems at all. > Can you help me with this? There is some reference to states and its numbers > but it is not clear which one is which (again edited messages with "X" mark): > > Info: Encoding result for state machine X|rxcntlsm:u1|state > Info: Completed encoding using 15 state bits > Info: Encoded state bit X|rxcntlsm:u1|state~34 > Info: Encoded state bit X|rxcntlsm:u1|state~33 > Info: Encoded state bit X|rxcntlsm:u1|state~32 > Info: Encoded state bit X|rxcntlsm:u1|state~31 > Info: Encoded state bit X|rxcntlsm:u1|state~30 > Info: Encoded state bit X|rxcntlsm:u1|state~29 > Info: Encoded state bit X|rxcntlsm:u1|state~28 > Info: Encoded state bit X|rxcntlsm:u1|state~27 > Info: Encoded state bit X|rxcntlsm:u1|state~26 > Info: Encoded state bit X|rxcntlsm:u1|state~25 > Info: Encoded state bit X|rxcntlsm:u1|state~24 > Info: Encoded state bit X|rxcntlsm:u1|state~23 > Info: Encoded state bit X|rxcntlsm:u1|state~22 > Info: Encoded state bit X|rxcntlsm:u1|state~21 > Info: Encoded state bit X|rxcntlsm:u1|state~20 > Info: State X|rxcntlsm:u1|state.wait_start uses code string 000000000000000 > Info: State X|rxcntlsm:u1|state.synch uses code string 000000000000011 > Info: State X|rxcntlsm:u1|state.wait_data uses code string 000000000000101 > Info: State X|rxcntlsm:u1|state.sample_data uses code string 000000000001001 > Info: State X|rxcntlsm:u1|state.wait_parity uses code string 000000000010001 > Info: State X|rxcntlsm:u1|state.sample_parity uses code string 000000000100001 > Info: State X|rxcntlsm:u1|state.wait_stop1 uses code string 000000001000001 > Info: State X|rxcntlsm:u1|state.sample_stop1 uses code string 000000010000001 > Info: State X|rxcntlsm:u1|state.wait_stop2 uses code string 000000100000001 > Info: State X|rxcntlsm:u1|state.sample_stop2 uses code string 000001000000001 > Info: State X|rxcntlsm:u1|state.db1_data uses code string 000010000000001 > Info: State X|rxcntlsm:u1|state.db1_parity uses code string 000100000000001 > Info: State X|rxcntlsm:u1|state.db1_stop1 uses code string 001000000000001 > Info: State X|rxcntlsm:u1|state.db1_stop2 uses code string 010000000000001 > Info: State X|rxcntlsm:u1|state.overrun uses code string 100000000000001 > > How do I read the above? > The warning about "reducing register state~34" repeats for state~33, > state~32, state~31 and state~30 as well, which is even more worrying...Article: 67514
Ray Andraka <ray@andraka.com> wrote in message news:<405124C2.90A6538A@andraka.com>... > Just plug the darned thing into your computer's UPS and be done with it! > > Allan Herriman wrote: > Even more fun when tiny fingers reprogram everthing to xxxx state. When I get to move house next time to a new semi custom design, it will be cat5/6 AND 1 ups power line for light loads like vcr/clocks in every room if the builder will let me. I just never bothered to learn to program anything except proper computers. johnjakson_usa_comArticle: 67515
>>Nicholas C. Weaver wrote: >> >>>Although careful design can get the forwarding path very short. EG, >>>the Nios described in FPGA 2004 has a 2 LUT level for the entire ALU, >>>including forwarding path, by clever use of features. > > ACM subscribers can get the paper. I don't know of the slides being > online somewhere. Thanks. That was indeed a very interesting and enlighting read. IMO it's one part clever sharing of logic and one part clever use of the cascade chain for multiplexers. I wonder if you could configure LUTs in such a manner from plain Verilog source (and what's "Quartus-Native Synthesis")? How do you get access to the cascade chain? The second question this raises is how this applies to the other Altera products, in particular Cyclone and Stratix II. As far as I could tell, the Apex and Cyclone are very similar (identical?) in architecture, whereas Stratix 2's ALMs should render some of these tricks unnecessary. Very impressive stuff. /TommyArticle: 67516
> My point is that for me, the price of my time for evaluating a product > is to provide a tool that I can do *useful* work with as part of the > eval. This precludes 100 pins or 30 day limits. This is just my > opinion. I am sure you will find lots of users who are willing to spend > their time and money to eval a tool. > I've looked at many Layout products over the years. I believe I can assess if a product has possibilities within a couple of hours - many times far less for the horror products. For those passing the 2 hour tests I can assess upto 90% of the capability within 8 hours. For the other 10%, yes maybe you have to layout a decent size board and that might take a week using a full evaluation... I would say the Pulsonix demo and evaluation period is more than adequate to assess the capabilities. Still, I guess I'm biased as I use Pulsonix. IMO it's about the best product around and beats OrCAD, PADS and Protel hands-down. I tried Eagle again this week and what a shock! It looks prehistoric by comparison... Don PrescottArticle: 67517
TommyInTheNews@numba-tu.com wrote in message news:<40515D7D.4060803@numba-tu.com>... > john jakson wrote: > ..... > > model and expensive NRE for special smp controllers. A couple of > > slower Transputers should easily be able to beat 1 faster x86 at any > > task. Even Intel is seeing the light. But Intel doesn't understand > > Occam and is stuck with x86 rock around its neck. > ..... > > sorry to sound like blowing my own horn, but the possibilities of FPGA > > technology seems far more interesting than the endless x86 drivel on > > comp.arch. > > No John, more power to you. You have to love FPGAs for giving mere > mortals such as ourselves the power to play computer architects. Though > I don't share your belief in Transputers (sw is a major deal), watching > you try is very exciting and pushing a cpu design to the limit is > something probably most of us enjoy. > > I look forward to seeing your Transputer! > > Tommy > PS: Be wary of the ivory tower and consider replacing Occam with > something more like Handel-C. Occam was just an awful language IMHO. Thanks Tommy: Precisely, but lets just say the syntax and BCPL loudness (so 70s) and its lack of normal expressions, tabbing syntax made it look strange but also beautiful in a Lisp sort of way. These are all very easy to fix, but these characteristics also made it mathematically easy to manipulate with Occam mangling tools or provers. Changing the syntax to the crude and vulger C that most of us want also makes that task alot harder for the formal types. But then if you accept Occam as a wannabe HDL sort of language, Verilog has the same issues, tool writers have to deal with a big syntax and parser to get at the meaning of the source before they can mess with it. So was Occam a sort of an EDIF, simple but rude syntax more friendly to the compiler writer than the end user, yes I think it was just a glorified TP assembler. The Par,Seq,Alt and message passing idiom and general distributed hierarchical Process model though is what counts. Not a million miles from the event driven HDL model which is why you mention HandelC. Before I went into ISE I had spent the last yr working on the compiler. I said it before here, its an lcc derived compiler with all new parts to include a std improved #`preprocessor with lexer, a combined Verilog/C/Occam parser, these are done. I was just about to dive into the not so wonderful world of C type semantics (see Hanson-Fraser book) and thought I might like a change of scenery. Also I really wanted some HW done rather than on the todo list since I have to do target emmision after tree building. I was planning on an altogether different single threaded cpu more in the mini 68k tradition, luckily ISE choked on it so I started over. One point I would make is that the internal tree could be emitted as raw Occam since its just a tree, so the math guys gets to see whats behind the Par C syntax. I call it V++ a pun on C++ but C with live HW objects and following 2 other Vxx languages. If I were a fan of VHDL, I probably could have left it intact as a single language, it already does most of what is needed IIRC, but it might get the same reception as Occam (Europe might love it), and I am not a fan yet. Some people would just hack lcc back end, but the project requires adding Occam-Verilog syntax and semantics so it turns into a rewrite. Thank goodness for the book though. I almost gave up on a previous compiler. To speed things up I may take some serious liberties with both Verilog & C types to get something working asap. Like lcc, passes can be replaced. The Verilog parts I most want to add to C are the synth RTL with some behav parts. The non synth parts sort of overlap with Occam and are probably redundant. The really low level stuff like udps will kill. thanks for the support regards johnjakson_usa_comArticle: 67518
Fredrik wrote: > Hi, > I would remove the pin assigment in Quartus (since you not using the > pin it should not be in your design). Second you have the option to > set (Assignment/Settings/ -> Device tap and Device and pin option > button -> Unused pin tab) all unused pins to tri-state. I guess this > is what you want if you have a signal on a pin that is not used. I think, if you declare in the Unused pin tab =A8As inputs, tri-stated=A8= =20 (This is the exact declaration! The other options are =A8As outputs,=20 driving ground=A8 and =A8As outputs, driving an unspecified signal=A8 - I= =20 would really like to know what is this later exactly!), you end up in=20 your hardware a large number of unconnected input pins. Just in the last = thread about unconnected =A8TRST=A8 pin several people pointed out, that = input pins MUST NOT remain unconnected, as they might start to oscillate = in high frequency, possibly destroying your FPGA. Or am I mistaken? I did not find any indication in Altera Datasheets if the input pins=20 have internal weak pullup resistors in general (the TRST pin should have = one, by definition). This also means if the unused pins aren=B4t connecte= d=20 at all they must not be declared =A8As inputs, tri-stated=A8. Could somebody explain here what is the correct procedure? Thanks, Janos Ero CERN Div. EPArticle: 67519
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<c2rtqm$psc$1@news.tu-darmstadt.de>... > john jakson <johnjakson@yahoo.com> wrote: > ... > > : The technology died out because Inmos didn't have their act together > : and FPGAs weren't around to help them prototype. The 2 tchnologies > : .. > > Actually Inmos was bought by ST and when the T800 came out after the merge > it was the first chip with more bugs than transistors :-) Do you mean the T9000 was full of bugs? I only know some of the story since I left Inmos in 84 before anything good came out. Basically I recall the T9000 was literaly 1 32b bus short out of 10, each attempt to fix the microcode pushed the problem elsewhere. Having a proprietary process didn't help either. If only they had had big FPGAs back then, but the stack arch & huffy coding would have killed it. Also the sim environment was Vaxen so its not like they had billions of cpu cycles either. johnjakson_usa_comArticle: 67520
Sander Vesik <sander@haldjas.folklore.ee> wrote in message snipped > > > > >Only because of HT and 3 level of LUT logic. HT means the pipelines > > >are mostly independant but cyclic like the spokes of a wheel. Just > > >like DSP (which is what I have been doing alot of over the years since > > >my Inmos days). > > > > Actually, thats not hyperthreading/SMT, thats > > interleaved-multithreading or C-slowing. See Chapter 11 and Appendix > > B: > > > > http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf > > Any particular reason you didn't use the term 'barrel processor'? C-slow appears > to be either a very new or very obscure term. > > > Thanks Sander I had been thinking about what term to use that would be self evident to any mechanical type. I was thinking of machine guns, piston engines, merrygorounds, spoked wheels etc. I am not one to follow strict terminology and hadn't been chatting with many comp architects, but I have heard that term before and will use it henceforth. Its been around long enough to be known for what this is. It does get me off the HT explanation beat. I sure don't like C slower as it actually speeds up C if it includes the Occam primitives. I think I would use the C slower term for conventional single threaded cpus that pay penalties when all the extra fancy HW doesn't work. regards johnjakson_usa_comArticle: 67521
TheCppMaster@aol.com (John) wrote in message news:<a25b4de5.0403121953.266cfb97@posting.google.com>... > Hello, > I'm looking for a prototyping board designed for complete system > development that is fairly inexpensive. I'm looking for a board with > video, audio, USB, PS/2, serial, ethernet, SDRAM, etc. I'm also > looking for a board that will give relatively good performance. I Basically a PC - the x86. Check out the fpga board list that Philip maintains, it keeps growing and growing and growing. http://www.fpga-faq.com/FPGA_Boards.shtml I would probably say that either A Nios or X MB is fine for what you propose. Check their respective web zones to see what looks more comfortable and then compare with boards that look like a PC, there are several I am thinking. I was am maybe tempted by the XESS board that also looks like a PC -x86. Do go for a board that has the largest FPGA that the free SW will allow, thats about 1/3 of way from the bottom up in any family. Check free Webpack or Quartus 1st to see limit. Also try these SWs 1st before you buy the board, that will lock you in for sure. After you choose the tool, the board will be safe investment for a while. Most of these boards will only have a part small enough to work with free SW or even smaller (too much cost saving). In my recent humbling exp of overestimating the sp3 given the false XST synth projections that makes it look as good as a v2pro before PR (for my HDL) and then crashes at half the PR speed, I'd def get whats here now. It will be nice when it arrives but I don't see it yet. Any board that cost near 1K, doesn't make much difference if a little more to get the faster bigger part, but most of these PC-x86 boards I see seem to use Spartan2, so look for E version & get extra blockrams. There are specific boards made for the Nios & MB markets that don't look like the PC-x86 thing that are probably better for serious work on those. The really good stuff that uses the v2 or v2pros or the Stratix won't come to you looking like a PC -x86, instead it will look like a PCI64 or some other serious factor with rockets and lasers and other wonder bits. Those parts don't go to the <1K experimenting crowd. good luck johnjakson_usa_comArticle: 67522
Hi all and hi Xilinx, actually dealing with gigabit transmission using external SERDES devices from TI, I just wonder if the app note xapp607 is just paper-and-vhdl-work, or if it is based on measurements on a real design. The general advices are 'nice', however at that frequency in multigigabit transmission, I would like to know a little bit more about the clock source for the GTX_CLK. According to the datasheet from TI clock jitter is a non-trivial requirement. If Xilinx has really build such a system and made some measurements, what kind of clock sources have been used? It seems to be obvious, that no DCM is involved in the design, however it is somehow not clear enough stated, that it will not work for more than half an hour or so, before failure if the GTX_CLK is coming out of a DCM ... Any comments on this? Have a nice weekend MarkusArticle: 67523
"Don Prescott" <DMBPrescott@aol.com> wrote in message news:7fb54666.0403130005.a5c8430@posting.google.com... > > My point is that for me, the price of my time for evaluating a product > > is to provide a tool that I can do *useful* work with as part of the > > eval. This precludes 100 pins or 30 day limits. This is just my > > opinion. I am sure you will find lots of users who are willing to spend > > their time and money to eval a tool. > > > > > I've looked at many Layout products over the years. I believe I can > assess if a product has possibilities within a couple of hours - many > times far less for the horror products. For those passing the 2 hour > tests I can assess upto 90% of the capability within 8 hours. For the > other 10%, yes maybe you have to layout a decent size board and that > might take a week using a full evaluation... I would say the Pulsonix > demo and evaluation period is more than adequate to assess the > capabilities. > > Still, I guess I'm biased as I use Pulsonix. IMO it's about the best > product around and beats OrCAD, PADS and Protel hands-down. I tried > Eagle again this week and what a shock! It looks prehistoric by > comparison... If you want another shock look at this abortion: http://www.otl.co.uk/ The developer seems to have a very high opinion of it, but it doesn't even have rubber-banding on the connections! LeonArticle: 67524
hello all, i want to download my program using Xilinx Spartan 4k 4.2 on xilinx xc4010e fpga board by programming in vhdllanguage. as i am new to this field i need your help . please tell me the steps in details. thanking you.
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