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I suggest looking through the iMPACT related answers in the database on support.xilinx.com I get no such error when running the process. What exactly are you trying to do if you don't mind my asking? Mike emanuel stiebler wrote: > Just tried, and I get: > > Launching Application for process "Generate PROM, ACE, or JTAG File". > > // *** BATCH CMD : setPreference -pref UserLevel:NOVICE > // *** BATCH CMD : setMode -bs > ERROR:iMPACT:355 - Open file error, bypass > // *** BATCH CMD : setMode -bs > > Cheers > > Mike Nicklas wrote: > >> I just tried this, it should launch the iMPACT program which then >> gives you the option of selecting your target type device i.e. PROM, >> ACE, JTAG etc. >> >> it's pretty intuitive from then on. >> >> Mike >> >> Mike Nicklas wrote: >> >>> have you tried expanding the "Generate Programming file" option in >>> the processes for source pane of ISE. >>> >>> The option to generate PROM, ACE or JTAG file is there, try running >>> that? >>> >>> Mike >>> >>> emanuel stiebler wrote: >>> >>>> Hi all, >>>> >>>> Where is the strange checkmark hiding in ISE 6.1 >>>> to create the .mcs files for programming the proms ? >>>> >>>> Thanks >>>> >>> >> > -- _ Michael Nicklas FPGA Design Engineer michaeln@slayer.com.remove To email, remove 'remove'! Seven Layer Communications Ltd. URL: www.slayer.com SSPC, Station Road, tel: +44 (0) 131 331 6170 South Queensferry, EH30 9TG fax: +44 (0) 131 331 7772 -Article: 67351
Hal, I don't know if this was aimed at me, but it sounds like me! A million clocks should be enough samples so that the "law of large numbers" holds and one can use gaussian (normal) statistics to make predictions. In general, 200K samples in our experience is just about the absolute minimum number of samples to work with. So I may get 200K samples while I am fiddling around, and then go up to 1 M samples for the final numbers that I wish to record. This is based on experience in the lab, using different boxes to capture data. If you use a scope, and sample 20K samples, then you may not get even close to the "right" answer. This is typically what folks do, and they underestimate the jitter by 2 to 3 times the peak to peak value. Based on where the samples are taken, you may actually need more. If clocks are time stamped and captured in a straight sequence, all 1 M consequetively. then you may need to take more to catch a lower frequency jitter spectral element. If the 1 M samples are not in a continuous sequence, then lower frequency elements are more faithfully captured. Some people have made jitter their career. If you are interested, NIST has training classes on the subject, and there are lots of books and articles on jitter as well. Some folks have studied jitter for longer than I have been an engineer (>30 years), and they are at least humble enough to admit what they don't know. Remember, if you can measure a smaller jitter value by changing something in the setup, you probably haven't found the real jitter yet. Also if you add more measurements to the jitter and it continues to increase by more than 10 to 20%, you still do not have enough samples. Once the measurement seems to converge, you are as "there" as you will be able to get. Jitter will always increase the longer you measure it, the trick is in knowing when to stop. Some folks call this the 1E-12 BER limit (14.3 sigma), but that assumes a normal distribution, which is definitely not present in the output spectrum of the DCM (it is superimposed gaussians, one for each tap change of the input jitter spectrum, so conversion of rms to p-p doesn't work at all). Like the famous quote, after awhile, "you will know it when you see it." Austin Hal Murray wrote: >>Oh, and I alwasy make sure I have at least a million clock cycles, and >>take repeated samples of a million cycles to be sure that I have the >>peak values captured. > > > How did you decide that a million was enough? How many times do you > have to repeat that? >Article: 67352
I forgot something and I add below:
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message
news:c2n95d$ap7$1@sunnews.cern.ch...
>
> > You can take the 50 mhz clock into a 2 bit counter and take the output
> > of the MSB for 12.5 MHz. This can drive a global clock tree within the
> > device to minimize skew between all registers driven by the 12.5 MHz.
> > The only drawback is that you will have some skew between the 50 mhz
> > and 12.5 mhz domains, so you need to be careful with data transfers
> > across the domains.
> >
> > Or you could take a 25 MHz PLL output and divide by 2 with a TFF. A
> > variety of options here.
> >
> > Sincerely,
> > Greg Steinke
> > gregs@altera.com
> > Altera Corporation
>
>
> Hi all,
>
> Since I am not an expert user I have a couple of questions on the above.
>
> <This can drive a global clock tree.. > how do you configure this?
> With the Assignment Editor?
>
> If in the top-level schematic ( I use mostly schematics were some of its
> blocks are in VHDL) you ask from the Assignment Editor to set for example
> the CLK pin as a global clock then everything connected with this pin
below
> in the hierarchy will be by this global tree lines? or do I have to go one
> by one the steps below to configure with the assignment editor the clock
> input as global line?
>
> It sounds logical only the first but had to ask.
>
> Thanks for your time.
What actually happens in the cases where I get the message:
Info: Automatically promoted some destinations of signal resetA to use
Global clock in Pin P4
Info: Destination crc_check:inst|calcCRC[6]~34 may be non-global
or may not use global clock
Info: Destination crc_check:inst1|calcCRC[6]~34 may be
non-global or may not use global clock
Why the software did not promote all but some?
Just in case you need to know:
S/W: Quartus II 3.0 with SP2
fpga: EP1S30F780C7.
Christos
Article: 67353If your board is 95% FPGA and you don't have many signals interfacing to the device, the FPGA *might* be able to be an island onto itself and deliver the results you need with 2 layers. More probably you have many signals coming from other functional components. Your jitter performance will be miserable with an average 2 layer design with 100 MHz operation. The 100 MHz is a knock against you. Any signals over 20 MHz interfacing with the chip will significantly affect the "quality" of your DC levels and, hence, your edge accuracy. There are many people who do 2 layer designs, but those are for digital functionality and not concerned about jitter. I like the suggestion of the cheaper Spartan-II device (the rough Virtex equivalent) as an offset for the cost of going the way you need to go... with at least a 4 layer board. "chuk" <charlesg77@yahoo.com> wrote in message news:faa526d6.0403100430.7c06f465@posting.google.com... > A hardware question? > > I am planning to use a Virtex 300 FPGA QFP package for a current > project running with a clock of 100MHz. My question is with regard to > the PCD design. Due to budget restriction I would like to restrict my > design to a 2 layer PCB. As a result, due to space restriction I have > placed the power tracks under the FPGA on the component side and plan > to place most of the larger decoupling caps on the bottom layer where > I have my ground plane. I am concerned that placing power tracks > under the fpga may cause coupling problems as well as excessive > chopping up of the bottom layer ground plane. The implementation is > jitter critical I must add. Does anyone have experience on this > respect? Should I just bite the bullet and pay for a four layer > implementation? > Thanks > ChukArticle: 67354
Synplify has an option to make a state machine "safe" in the sense that if your state machine magically (alpha particle ...) transitions to an illegal state code, that it will get back to the reset state within a few cycles. This is much less expensive than the normal way of specifying transitions for all states illegal or otherwise. Ken McElvain Mike Treseler wrote: > Hal Murray wrote: > >> But that's only one of the screwup patterns. The other one is >> that it starts in state 0000... >> Is there any simple way out of that? (I can't see one.) > > > I don't know a *simple* one. > The *stress-less* one is > binary encoding. > > -- Mike Treseler >Article: 67355
On 9 Mar 2004 23:30:45 -0800, imad694@yahoo.com (Hunter) wrote: >Hi, > >I have written a very small design to control some LEDs in order to >check out the XC2V6000-4ff1517 FPGA on a board that I am bringing up. > >The code has only 92 signals that are to be routed. The Synthesis, >Translation and mapping steps take just 25 seconds. However, the PAR >takes about 20 minutes. I would like to know what the ISE6.1 (SP3) is >doing in all that time? > >Any suggestion to improve this will be very welcome. > >Thanks, >Hunter Have you constrained it to a very high speed? If so, relax the timing constraints (say, half the speed) and try again. If it routes much faster, it was working hard to meet timings, which could indicate some redesign needed (reduce logic levels, or increase pipeline depth, or floorplan) so it can meet timings more easily. Or reduce the clock rate, if all it is doing is lighting up LEDs... - BrianArticle: 67356
Please, someone could suggest books about embedded systems ?? tks Ricardo MenottiArticle: 67357
In article <qh1xo11nep.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: >> If you are using a Xilinx, the V2/V2Pro bitfile encryption is a VERY >> high barrier for an attacker to cross: I'd comfortably protect a $10K >> secret, and uncomfortably protect a $100K secret from a malicious, >> capable adversary. > >I'd expect the cost of extracting a valid decrypted bitstream from the >part to be even higher than that. You have to do it without losing the >backup power to the part long enough for cells to change state. This >makes a lot of the otherwise promising avenues of attack difficult if >not impossible. For instance, you're not likely to be able to decap >the part and microprobe it. (Microprobing probably wouldn't work anyhow, >as the signals you need for bistream extraction are likely below metal.) I'd be uncomfortable putting a "THis is the magic words to get you $100k" in the part, as thats enough money for a fair bit of reverse engineering. It would be a neet contest for Xilinx to do however, and they might very well keep their $100K. I'd still worry about sidechannels on the encrypted loader (esp since can load bogus files -> known cyphertext, and there is also alot of known plaintext). >It is more likely that a successful attack would result from some sort >of "social engineering", and even the fanciest protection features built >into the FPGA aren't going to protect from that. True. And never forget the joy of "RUbber Hose Cryptanalysis" as well. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67358
Embedded IDs are very easy to crack. Just decap the part, and look for the laser fuse marks! Or, if they have fuses, look for which ones are blown. The advantage of the V2 & V2 Pro sram is that if the battery goes away, the key goes away, and the IP was (is) secure. If they open the part up while operating, and try to read the sram cells, hey, more power to them, as they have just blown a lot more money and time on the IP than it was probably worth. They could have gone to the manufacturer, waited for a smoke break, and asked "anyone have the keys? I have $$$$ right here...." Never protect an expensive bike with a cheap lock, and conversely never protect a cheap bike with Fort Knox. AustinArticle: 67359
Warren, When iMPACT intializes chain, only TMS and TCK is toggled and TDO captured. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11857 However, when running IDCODE looping, TDI is actually toggled. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8902 If IDCODE looping fails, this usually indicate some kind of SI/PI issue. A couple things to check. With the FPGA configuration, did the DONE pin go high? What's the INIT pin status? When FPGA verify fails, does it always fail with the same number of mismatches? With IDCODE looping, does it always fail at the same count? Is the standard Xilinx PC3 cable and flying leads used? The Xilinx hotline can provide more debugging tips. http://support.xilinx.com/support/services/contact_info.htm Regards, Wei warren wrote: > I have been going nuts with a Spartan 2 and 18v04 during configuration > with a JTAG cable (III) and impact 6.1. > > 1. The mode pins are set for boundary scan. > 2. If I run the cable with a 5v reference: > a. Chain initialization will succeed 99% of the time. > b. EPROM programming/verify will succeed 95% of the time. > c. FPGA programming/verify will fail verify 100% of the time and > the FPGA is left with what appears to be wrong IOB configuration; > starts drawing a great deal of power. > d. If I run IDCODE looping, it will fail before my defined 1000 > loops are completed. > 3. If I run the cable with 3.3v reference (which it should be anyway), > I cannot get through the Chain initialization ever. I get > up to 10 unknown devices reported. > > I have pulled out a previously designed board and reprogrammed it > without any problems, to verify the software/drivers/cables. > > I have checked for noise on the power and JTAG lines, didn't find > anything alarming. > > If anyone has any suggestions, your input would be GREATLY > appreciated. > > > Thanks! > > (reposted to get a new thread)Article: 67360
According to XAPP751:- Each Spartan-3 I/O bank contains a special voltage bias circuit that controls the differential output voltage and the common-mode voltage for differential outputs. Memory cells loaded during FPGA configuration control the bias circuitry, and the default memory settings are included automatically in the generated FPGA programming file. Very good indeed! Does anyone know if the same thing exists in any other Xilinx family with LVDS outputs? (I guess this explains the LVDSEXT mode in VirtexII/Pro) Syms.Article: 67361
That code seems to go fine on my install of ISE 6.2.1i. The error message mentions a parser problem with line 337. Either there is a bug in the parser and the code is fine or there is a problem with the code at or near that line. Take a look at and around that line. Is there a control character or something unusual with that line? The code you popsted does not have that many lines so I can only guess which line it is really referring to and if it is a control character perhaps the cut & paste into this NG removed the problem. The other side is this could be a bug in the parser. I believe you mentioned you were using 4.1i which is a rather old version of the software now. You could try upgrading to the newer version of the software and see if that makes a difference. You could also try running the code through a simulator or another synthesis tool to see if it gives you problems. That could narrow down the problem for you. -- Brian sunil wrote: > hi, > tried so many ways. I am getting same error. individual > blocks are getting synthesized. Please if anybody have the idea help > me. > thanking you all.Article: 67362
Hi, You could build this: http://www.engr.sjsu.edu/crabill/lab6.pdf It is a 2x2 array with 2 LE's and 2 IO's. The bitstream is 196 bits. If you actually attempt to do this, I would be interested in your results / experience. I've had students implement this FPGA design in an FPGA (kind of recursive) and then do a 2-bit binary counter -- placed and routed by hand, bitstream generated by hand. It works. Good luck, Eric Tong wrote: > > hi Kelvin, > > Yup, I come from The Chinese University of Hong Kong. > I don't think my professor is fooling me. May be I should > state clearly what I have to do. > > The poject do not require us to make a real chip. We just > use magic to draw the layout and use irsim to simulate. And, > it is a group poject. > > Could you shed a light on my project? > > Regards, > TongArticle: 67363
Symon, Yes, it does, and yes they all work similarly. Austin Symon wrote: > According to XAPP751:- > Each Spartan-3 I/O bank contains a special voltage bias circuit that > controls the differential output voltage and the common-mode voltage > for differential outputs. Memory cells loaded during FPGA > configuration control the bias circuitry, and the default memory > settings are included automatically in the generated FPGA programming > file. > Very good indeed! Does anyone know if the same thing exists in any > other Xilinx family with LVDS outputs? (I guess this explains the > LVDSEXT mode in VirtexII/Pro) > Syms.Article: 67364
You can dowload a free version of ISE 4.2i that does support the XC4010E device from the Xilinx Web Site at: http://www.xilinx.com/webpack/classics/spartan_4k/index.htm The main gotcha with this version is that it does not include a syntheis tool so you must get your design to an XNF or EDIF netlist before using the tool. There are some free and pay-for synthesis/schematic tools available if you look around for them but I will leave that exercise up to you. This should be better than the 2.1i version you have found and it is how I would suggest you go forward if you want to use the XC4010E device. The XC3142 (about a 15 year old part) on the other hand is too old to be even suppoorted by the 4.2i or 2.1i versions and you would need to go back to the XACT tools (circa 1995) to use it which I do not suggest doing at this point. Hope this helps, -- Brian manmohan singh wrote: > Dear Sir, > > As suggested by you I have downloaded the webpack from the Xilinx > website but how to set the options for the device XC4010E and > FPGA3142. Forgive me for my ignorance. kindly help me. > > regards and thanks > > "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2004.03.07.15.46.31.684698@polybus.com>... > >>On Sun, 07 Mar 2004 06:38:15 -0800, manmohan singh wrote: >> >> >>>Hi All, >>>Greetings, >>> >>>I am a student. I found Xilinx 2.1i version software but I think >>>Licence is expired. Can anybody give me the information from where I >>>can get the licence (preferably free because as student I don't have >>>much funds) >>> >>>regards and thnaks >> >>You don't want to use 2.1 for anything it's an antique. Xilinx offers >>webpack which is a free version of their tools. Webpack is a subset but >>it's probably sufficient for your needs. If you want to use the full set >>of tools you should have your EE department contact the local Xilinx sales >>office, I suspect that they would be happy to provide a free or >>discounted version of their tools to you University.Article: 67365
Hi - On Wed, 10 Mar 2004 11:05:59 -0800, Eric Crabill <eric.crabill@xilinx.com> wrote: > >Hi, > >You could build this: > >http://www.engr.sjsu.edu/crabill/lab6.pdf I'd also recommend you pop up a level and look at some of the course material listed here: http://www.engr.sjsu.edu/crabill Very nice presentations, Eric. Bob Perlman Cambrian Design WorksArticle: 67366
If you already have a bitstream for the 4010E, you should be able to use Webpack 6.2i to download to that device however if you want to change the design or create a new one, that version does not support the creation of new bitstreams for that device. I just posted the follwoing response to a similar request and I suggest you do the same if you wish to use your XC4010E board: You can dowload a free version of ISE 4.2i that does support the XC4010E device from the Xilinx Web Site at: http://www.xilinx.com/webpack/classics/spartan_4k/index.htm The main gotcha with this version is that it does not include a syntheis tool so you must get your design to an XNF or EDIF netlist before using the tool. There are some free and pay-for synthesis/schematic tools available if you look around for them but I will leave that exercise up to you. -- Brian sirohi_rajiv@rediffmail.com wrote: > hello all. > i am working with xilinx ise webpack 6.2. > i want to know that how i can upload my program on "xilinx xc4010e" kit. > i am in great trouble so please help me. > thanking you. > rajivArticle: 67367
Austin Lesea wrote: <snip> > Never protect an expensive bike with a cheap lock, and conversely never > protect a cheap bike with Fort Knox. .. Unless you want to use the latter, to create the illusion of a _very_ expensive bike... :) -jgArticle: 67368
"rAinStorms" <chris_karma@xtra.co.nz> wrote in message news:LuB3c.513$rw6.23547@news.xtra.co.nz... > We have had lots of success so far ... been using it for a while. > > Got any optimisation flags ticked? did not got so far. Install, start Quartus Open Recent -> Compile -> Error Open tutorial -> Compile -> Error Create new project (1 input direct to output) -> Compile -> Error that was it, seemed that 100% non functional, as it failed no matter what. strange it did not ask for computer reboot or to get new license ? so I assumed it was all OK. whatever a software should not fail with showstopper internal bug 7 seconds after the splash screen is gone. > We do a lot of minimise area with chains stuff and logic locking (which is > tonnes better than 3) but there used to be issues with some flags in 3. > > Are you using an AMD based platform - had some issues running version 4 on > AMD we think. hm, need to check, but I think its genuine Intel with 2GB RAM antti tnx, I will give Quartus some more trial attempts.Article: 67369
Hi folks, I have Xilinx Webpack 6.2i and ModelSim Starter Edition 5.7g. I know that ModelSim has 500 lines limitation, beyond that it still works but run slower. So, can I overcome the limitation by using HDL Bencher? Does HDL Bencher has any limitation? Can it do what ModelSim does? Mainly accepting my own testbench and injecting the signal to the Unit Under Test but without any line limitation? Thanks! HendraArticle: 67370
Thanks, I appreciate the complement. I hope people find them useful. Eric Bob Perlman wrote: > > I'd also recommend you pop up a level and look > at some of the course material listed here: > > http://www.engr.sjsu.edu/crabill > > Very nice presentations, Eric. > > Bob Perlman > Cambrian Design WorksArticle: 67371
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<404ea276@news.starhub.net.sg>... > Do spartan-2 and JTAG support readback and verify? > > Kelvin > > Thanks for the input, found I had to put an RC circuit and buffer in the TCK line. http://www.ricreations.com/AppNote003.html tipped me off. Thanks to everyone!Article: 67372
Austin, Cool as chips! So, how about letting us know on CAF what those mystery bits actually do? It seems that they control both the common mode voltage and the differential voltage. But, which bits control which characteristics? Please don't make me experiment myself! You could save me a host of AC coupling caps! Of course, I don't expect guaranteed specs. However, I'm surprised that Xilinx doesn't tout this as a unique selling point, especially as there are so many differential signalling standards emerging as supply voltages continue to fall. Thanks, Symon. Austin Lesea <austin@xilinx.com> wrote in message news:<c2npfg$dkt1@cliff.xsj.xilinx.com>... > Symon, > > Yes, it does, and yes they all work similarly. > > Austin >Article: 67373
Hi, there: I have been confused why ISE6 always spend a lot of time after it has completed routing... On the routing log, it seems at Phase 7, it accomplished all routing already...but why Phase 8? Best Regards, Kelvin Phase 9.27 Phase 9.27 (Checksum:55d4a77) REAL time: 5 mins 4 secs Writing design to file switch_top.ncd. Total REAL time to Placer completion: 5 mins 7 secs Total CPU time to Placer completion: 5 mins 3 secs Phase 1: 13137 unrouted; REAL time: 5 mins 10 secs Phase 2: 12564 unrouted; REAL time: 5 mins 57 secs Phase 3: 3148 unrouted; REAL time: 6 mins 3 secs Phase 4: 3148 unrouted; (22384) REAL time: 6 mins 4 secs Phase 5: 3161 unrouted; (22208) REAL time: 6 mins 5 secs Phase 6: 3161 unrouted; (22208) REAL time: 6 mins 6 secs Phase 7: 0 unrouted; (22732) REAL time: 6 mins 27 secs Writing design to file switch_top.ncd. Phase 8: 0 unrouted; (22195) REAL time: 10 mins 24 secsArticle: 67374
A while back I mentioned I'd post an update on progress for this R3 hyperthreaded cpu project. Most of the area consuming Verilog blocks have been written and synthed for the -5 parts. fmax was typically just over 311MHz for most blocks, and 308MHz at the top level. As a comparison, the same design in sp2 was down to 95-120MHz and the v2pro was about 304MHz -7 grade. It barely fits the sp3_50 part now but only because all the LUTs and FFs are separated. A good ucf file can pack them well below but thats another project to get back to later. I am at about 800 LUTs and FFs. A quick look at the cyclone parts says 200MHz fmax for the BRams, that would be my limit right away or worse, but its not 90nm either so I will leave it for now. Because of the blow up and to further the cache design, I will use 4 BRams for cache, 2 for the 1way direct map set, and 2 fixed at low address to contain tags and low address sytem stuff. That gives me 8 useable ports where 4 or so are needed per cycle. The tags can now be read in parallel with the 4 cache addresses, this does mean tags are stored twice to allow 4way checking. As I said elsewhere, every op can include 1 or 2 optional bcc fields ss well as 1 datapath op. On avg 1 in 3-8 ops might take advantage of that yielding about 1.3 x fmax mips. bcc ops are 0 cycle whether taken or not, thanks to hyperthreading. bcc fields do push up the fetch rate that happens far ahead but 2 16b ops only use 1 unused port read. I am now verifying cpu block by block in C simulation (Verilog=>C code). The datapath with critical segmented 12b ALU adder and status flags looks good on rnd vectors. I will be verifying the branch datapath, hyperthreading engine, cache control next. I am feeding the beast with synthesized rnd ops to suit the test simulation at hand. I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the fmax has shot up to 430MHz overall and the 2 larger blocks besides blockram are in the 550MHz ballpark. The timing report is essentially same as before, no special warnings but some improvement in compile time I was looking for. As a crosscheck, I redid the other sp2, v2pro and got same results as before. Only the sp3 goes up. 430MHz x 1.3 is about 550mips. Is this for real, has Xilinx actually seen silicon that can do these speeds where 12b adds or 3 LUT/mux layers is the longest digital path? The datasheet ds99 only suggests 320MHz fmax, I thought that might be the BRam limit. Ofcourse I will gladly take it, but it leave butterflies in the stomach. Licensing I have been contemplating how to license the design, I would like to see the final design in its Transputer form open to individuals and dot edu, but $ for commercial interest. Trolltech does this with Qt, gpl for non commercial Linux and the KDE world while still doing well for $ Windows market. I am interested in other points of view on this. johnjakson_usa_com
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