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"millim" <merlin1974@gmx.at> skrev i meddelandet news:8e53c613.0403080739.aa1236b@posting.google.com... > I am trying to find an efficient and simple way to protect > prototypes from cloning. > > One idea relies on using the serial number of the FPGA device, > because in any prototyping phase only a hand full devices are > present. But is there an embedded hardware register in the FPGA device, > which contains a unique serial number? > > regards The Secure FPSLIC (AT94Sxx series) embeds the configurator into the same package as the FPGA: The configurator has two ports and a protection fuse. When this is set, you cannot see the configuration data on any pins. You have to physically open up the device package to discover its secrets. Not 100% protection, but at least a higher barrier. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 67551
Sounds like you are talking about finite word length effects.... not what the original posting was referring to. Since you brought it up I suppose it can be discussed. Well, it looks like you are saying that in general, bit symbols are uniform... depends on the processing that is going on (distributions can get transformed!). It says nothing about the complexity of the algorithm. The distribution along with the word lengths do contribute to the information throughput (in an information-theoretic sense). And as for your reference of word length complexity: I am sure that you are refering to a specific class of algorithms - perhaps one that you were working on recently. But this is generally not the case. Regardless, your arguement along with your reasoning very strongly state my case. You are making statements about a method based on its complexity. In more familiar terms here are some examples: Look up table (search): O(n) - Linear complexity with the length of the table. Stack Push/Pop: O(1) - Constant complexity. Tree Search: O(n log n) - Log-linear complexity. Bubble Sort: O(n^2) - Quadratic complexity. Insertion Sort: O(n log n) Shell Sort: O(n) These were simple examples, but I left the classic sorting algorithms for last. QUESTION: You have a 1k buffer that needs to be sorted. Which method do you use? Bubble is the most abused one and will give you the worst possible (timing) performance and once working, and if one is none the wiser, than it will appear as an operational upper bound. Too bad I have seen this one in a few designs. The bubble sort would take about a*(1k)^2 units of time, while shell sort would take b*(1k) units of time... where a and b are constants that reflect the timing of the associated sub-circuits, but are very close to each other. Anyhow, I think that the complexity issue is more interesting to those that are in industrial R&D and the associated academics. It is important if timing is of concern, expecially where speed performance is bounded by deadlines, ie. real time systems. Thanks for your patience in hearing me ramble. I will now get breakfast. Mmmmmmm..... "Herman Rubin" <hrubin@odds.stat.purdue.edu> wrote in message news:c2qf0u$2ceg@odds.stat.purdue.edu... > In article <zmU3c.38500$6y1.1282676@news20.bellglobal.com>, > Invisible One <Invisible_1@sympatico.ca> wrote: > >*sigh* - is speed the thing that everyone is concerned with? > > >Hands down, hardware is faster than software - most non-technical folks know > >this. End of story. Now if you are looking at complex algorithm > >implementations algorithm COMPLEXITY is of paramount concern. Time > >complexity is independent of platform: sw/hw. > > What is complexity? This is not a vacuous question; the > computational complexity of generating random variables > with "most" distributions from uniform random input by > the usual methods goes up rapidly with the length, but > it one is allowed to use bit methods, it is random finite, > usually with finite expectation. However, it can be so > slow as not even to be considered. This is the case even > if no roundoff is allowed, other than restricting the > number of bits output. > -- > This address is for information only. I do not claim that these views > are those of the Statistics Department or of Purdue University. > Herman Rubin, Department of Statistics, Purdue University > hrubin@stat.purdue.edu Phone: (765)494-6054 FAX: (765)494-0558Article: 67552
"Jon Beniston" <jon@beniston.com> skrev i meddelandet news:e87b9ce8.0403110225.313772a3@posting.google.com... > > I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the > > fmax has shot up to 430MHz overall and the 2 larger blocks besides > > blockram are in the 550MHz ballpark. > > If true, then Wow! Your FPGA based CPU is faster than 0.13 ASIC CPUs. > > The timing report is essentially > > same as before, no special warnings but some improvement in compile > > time I was looking for. If you have the restriction that two adjacents (timewise) instructions can never be in the same thread then the hyperthreading CPU inherently has less logic in the critical path than the ordinary RISC and should thus run at a higher clock frequency. The main problem with hyperthreading is in cache trashing. When you are executing out of 0 waitstate embedded SRAM, then this is no longer a problem, so a hypertreading CPU should be excellent as a processor for emulating peripherals. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 67553
TheCppMaster@aol.com (John) wrote in message > So the Spartan2E's will give enough performance to make the system > usable on a basic level? > Cpus need as much BRam as possible, check the pdfs to compare sizes, the E part is hardly more expensive than the other, I was looking at the Digikey for parts and ISTR the 400 was $26, I could be mistaken. Any of the parts you can get to work with free SW can hold far more than a simple cpu, but by the time the parts fill up I wonder how much the system freq will fall for most people doing just push button layout. > > The really good stuff that uses the v2 or v2pros or the Stratix won't > > come to you looking like a PC -x86, instead it will look like a PCI64 > > or some other serious factor with rockets and lasers and other wonder > > bits. Those parts don't go to the <1K experimenting crowd. > > Although I ruled this out due to expensive development software, check > out this link: http://www.mjl.com/product/mjlstratix.asp > It has a pretty standard motherboard layout for a stratix for only > $795. > Now that looks interesting. The only thing wrong with these PC boards is the VGA max bw, usually 100MHz or so for vga resolution, it would be cool if I could get 1600.1200 out of one.v From the doc file I see it drives the VGA from FPGA but doesn't indicate what thebest resolution might be. Color resolution might be limited with ext R2R network, thats a bit out of my scope HF analog level. regards johnjakson_usa_comArticle: 67554
rickman <spamgoeshere4@yahoo.com> wrote in message news:<405381EA.A883759F@yahoo.com>... > John wrote: > > > > > the bottleneck. Remember, you can put a lot of logic on these chips, > > > but you won't ever get much cache in comparison to the 512 MB and 1 GB > > > they are making today in CPUs. > > > > I'd like a CPU with 1GB of cache but that doesn't seem possible with > > today's technology. I only have 1GB of total memory in my system (plus > > 1MB of cache on each of my Opterons). What kind of cache could be > > expected to fit into an FPGA today? > Actually, 1Gb cache is not entirely silly, just extreme. I seem to recall in the past that one of the key diff between most PC and Crays was that they would bulk up on SRAM the same way PCs do on DRAM, only the cost is huge as well as power. A cpu such as mine effectively cycles each process slower than 20ns since that is 4 fast barrel cycles. The RLDRAM cycles each bank at 20ns too and getting faster it seems. With 8 banks its actually faster than my 4 processes could need. The BRam cache is really there to manage that bw better and to allow 4way porting into that speed so it doesn't have to be large itself. I am only planning 1 device thats 256Mb or 32Mbyte, but its not entirely silly to put 32 or 16 of the 512K RLDRAMs down but at $25 or so for each a little steep. Better to put more cpus around and or use plain SDRAM at the main level. Indeed it may make sense to model the cpu with DDRAM and no RLDRAM, since its only about 3-4x slower, and if it fits in an sp2 FPGA the boards are already there with SDRAM and sometimes SRAM too. As for spartan3, the big improvement over the spartan2 whatever the speed is, is the memory, about 2-4x as much. The 4k Brams are nice for lots of small jobs, but quickly get used up for even a small cache. But the 16-18K rams get used up quickly since only a few. I wonder if we will ever see 3 levels, big, medium and tiny. The distributed ram consumes too many LUTs for rams like 64 by 16 which I need lots of, but using a BRam is a huge waste on that. That does limit portability, not sure if I can get into a sp2 board. regards johnjakson_usa_comArticle: 67555
George wrote: > I've just completes a design change to an Altera ACEX1K100 device. > It's running a NIOS processor and I added more serial ports. Not a > big deal. > > While waiting for the new prototype boards I upgraded from Quartus II > 2.2 to Quartus II 4.0. > > When I connect the new boards using Altera ByteBlasterMV (PC parallel > to JTAG) and attempt to download this new configuration the > programming window just zips through (less than 1 sec). It says it's > done but new configuration has NOT been loaded. > > If I revert to Quartus II Ver. 2.2 BOTH old and new boards can be > loaded with either old or new configuration. > If I upgrade to Quartus II 4.0 NEITHER old or new boards can't be > loaded with any configuration. > > Anyone seen this?? > > Any suggestions?? > > Thanks > George I have same kind broplem wiht 1k chip, BBMV and Quartus II 4.0, earlier version of Quartus configuration has work correctly. Only way how I get configuration file to 1k chip is now use MaxPlusII software for configuration. I think that you can use JAMPlayer too for configuration or wait patch to Quartus. t.kariArticle: 67556
TheCppMaster@aol.com (John) wrote in message Ask Anti, he has alot to say about both but not always kind words. I guess most people seem to feel whichever one they chose is ok, they both got problems but what do you expect for $0. I don't have time to learn the A side of things just yet but the choice used to be easier. See the FPGA faqs on choosing vendors, but its dated. If one vendor had features you really needed, that the other didn't, that helps too. > > Also, as the posts have suggested, I should probably pick a vendor > based on design software rather than device capability as they (Altera > and Xilinx) both seem to be offering good products at comparable > prices. I've been doing some reading and comparing the free "Web" > editions of the design suites but I was wondering if anyone here would > like to share the reason for their choice. > > Thanks! regards johnjakson_usa_comArticle: 67557
Hi Group,
I need your help, suggestions and comments on product procurement.
I am interested in a board having Xilinx V2pro with
A/D Module (for sensor, not audio)
D/A modules (not audio but for analog sensors)
USB
Firewire
Ethernet
RS232
SysACE controller
Wireless modules (Bluetooth preferred)
Either integrated or as an Add on to the base board with V2pro. My
project is building robots with plug and play sensor capability, and
dynamic partial and full reconfigurability.
I am also interested in products from Altera with the same
capabilities.
I would like to know the distributors who have/can help me built one
of these.
Thank you for your time.
Regards
Ramnathan
Article: 67558Marc Randolph <mrand@my-deja.com> writes: > Adarsh Kumar Jain wrote: > > if you are sure about the parity with which you comma is coming than you can > > choose which one to enable... else you can allow both.. > > i am using ROCKET IOs as receivers only and I am not sure about the parity > > with which my commas will come, so i keep them both enabled... > > and they identify the words boundaries correctly and align data correctly... > > they can be deasserted later once you verify that the data aligned signal > > has gone high.... > > Howdy Adarsh, > > IF you are using it for alignment, why would you later disable it? Are > you manually inserting alignment characters to get sync'ed up, then > later on sending raw data that might have have bit patterns that look > like sync characters? Because you don't want a bit-error to possibly re-align your bitstream, I guess. Homann -- Magnus Homann, M.Sc. CS & EArticle: 67559
Leon Heller wrote: > > "Chaos Master" <wizard_of_yendorIHATESPAM@hotmail.com> wrote in message > news:c30b4j$22gb0t$3@ID-88878.news.uni-berlin.de... > > Leon Heller posted in sci.electronics.cad , in article > > <4052d7a8$0$10149$cc9e4d1f@news.dial.pipex.com>, at Sat, 13 Mar 2004 > 09:43:04 - > > 0000: > > > > > > > If you want another shock look at this abortion: > > > > > > http://www.otl.co.uk/ > > > > > > The developer seems to have a very high opinion of it, but it doesn't > even > > > have rubber-banding on the connections! > > > > And it does not run on Windows 98 (yeah, I know Kevin will flame me after > this). > > > > For other shock i'd look at VUTRAX, that has a GUI which I would call a > CUI > > (Confusing User Interface), IMHO. Their help system is a pain on the a**. > > A friend of mine has used the original DOS version of Vutrax for about 25 > years. It's probably because he comes from Yorkshire. 8-) > > I find it very strange that several PCB packages don't conform to the usual > intuitive way of selecting objects - just put the pointer on them and click > the mouse button. That's the way most other applications work these days. Yes, that can be very awkward to learn and get used to. It comes from being around before GUIs. But I found Eagle was not hard to use once you got used to it. Some of the features were actually highly productive. But it is a PITA every time I go back to it from other, normal apps. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67560
John wrote: > > > Not off the top of my head. I think these sockets are PGA, so there > > should be adapters available from ET and Ironwood, but they will be > > pricy, like a few hundred dollars. You might start out with something > > simpler and cheaper like socket A or 370. Fewer pins means fewer > > dollars. That is true for both the adapters and the FPGAs. > > The more research I'm doing the less likely this idea seems. I > searched Ironwood's online catalog and I couldn't find anything for > either of those sockets. Also, is it practical to plug an FPGA > directly into the motherboard by converting the package to a common > socket or would it be better to put it on a PCB complete with extra > hardware such as: I know they make adapters for PGAs. You may not find one that says "socket 370", look for the right number and spacing of pins. > *SRAM for some sort of L2 cache > *JTAG port or some other programming interface > *Flash memory for bitstream storage > *CPLD for device management (loading config from flash) At that point you might as well design your own board in total. > Also, I'm not that familiar with the operation of a standard PC > motherboard. It seems that there would need to be a bit of board > reconfiguration in order to get the board to boot a chip based on > another architecture. I don't know about reconfiguration. Your card will do everything it needs to boot the FPGA and from then on it should be in control of the MB. > As for the idea of putting it on a PCI card, although it would allow > for integration into a PC motherboard, how much of the board would it > actually be able to control? Could the board even be properly booted > without a CPU in the main socket? No, I said a "passive" backplane. That accepts a PCI card with the CPU on board. This would be a lot like the unit you describe above. The only advantage is that it would allow you to plug in any PCI card for IO that you would like. > If you have any suggestions, feel free to let me know. > > Also, as the posts have suggested, I should probably pick a vendor > based on design software rather than device capability as they (Altera > and Xilinx) both seem to be offering good products at comparable > prices. I've been doing some reading and comparing the free "Web" > editions of the design suites but I was wondering if anyone here would > like to share the reason for their choice. The one big difference I found is that Altera does not offer an HDL simulator with their web package. They give you a gate simulator which will not read an HDL testbench. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67561
Hi Rick, You can directly instantiate any legal logic cell from within verilog code by instantiating "WYSIWYG" logic cells. This lets you do any amount of technology mapping you like, and mix it with HDL. The Verilog syntax that is used for instantiating a logic cell is described in QUIP (Quartus University Interface Program), in the document "stratix_wysuser_doc.pdf". You can instantiate logic cells from inside VHDL code by writing a verilog file with the logic cells you want, then instantiating that entity in your VHDL code. The tutorials provide some examples of how to create these logic cells, and how to read the netlist if you choose to dump out the netlist of logic cells Quartus makes. You can download QUIP from https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp, and can see what QUIP is about from http://www.altera.com/education/univ/quip/quip-overview.html. Regards, Vaughn Altera > "Nicholas C. Weaver" wrote: > > > > Using lots of Altera features and cleverness to combine things, > > including the LUT cascade chain. > > I like the cascade chain concept. It can make wide muxes much easier. > But I have never been able to get the tools to use it for combining more > than two LUTs when using HDL. Any suggestions on how to do this? I > will be optimizing a design after it is fully debugged and this is one > of the first things I want to address. > > -- > > Rick "rickman" CollinsArticle: 67562
Hi Leszek, Look at the logic cell listed in the error message, and see if its clock and/or asyncronous clear were promoted to be global signals (look at the Quartus info messages and see if there is a message saying these became global). From the no-fit message, I believe you should find that neither was promoted to global. Since you have auto-global promotion on, it probably means you're running out of global networks. You can force one or both of these signals (say the clock) to be promoted to global by setting "Global signal = on" in the assignment editor for the appropriate signal. That should resolve the no-fit, although it does mean some other aclr or clock will be kicked off the global networks. Also, make sure you don't have so many "global signal = on" assignments on other signals that you are causing yourself to run out of global networks. Regards, Vaughn Altera leszekd@itam.zabrze.pl (Leszek) wrote in message news:<9cc55753.0403120152.2c4ee77e@posting.google.com>... > Jesse, > > Have you re-generated your SOPC Builder system (Nios and all > > peripherals) for the Apex family? > > I think so... > I avoid this problem in the past (I connected in other way my NIOS > with logic in Apex), but now I have this problem again :-(. I don't > know, what I have to do :-(. I added fifo megafunction and when I try > control it by NIOS, the same errors appear. > Pleaaaase help me :-) > LeszekArticle: 67563
> What actually happens in the cases where I get the message: > Info: Automatically promoted some destinations of signal resetA to use > Global clock in Pin P4 > Info: Destination crc_check:inst|calcCRC[6]~34 may be non-global > or may not use global clock > Info: Destination crc_check:inst1|calcCRC[6]~34 may be > non-global or may not use global clock > Why the software did not promote all but some? > > Just in case you need to know: > S/W: Quartus II 3.0 with SP2 > fpga: EP1S30F780C7. > > Christos Hi Christos, Quartus will automatically promote clock & asynchronous reset signals to use global networks, if you haven't set any global signal = <value> attribute on them. In the case where you have a signal (e.g. resetA above) that is used both as an asynchronous clear on some registers, and as a regular logic signal to some other parts of the design (e.g. an input to a LUT or some such), Quartus will automatically promote only the parts of the net that are being used as an asynchronous clear to use the global network. The parts of the net that are used as regular logic inputs may or may not use the global network -- the fitter decides based on what looks best for circuit timing and routability. This is done because users normally want low skew on the clock & asynchronous clear parts of a net, but they want fast performance on the logic parts. Sometimes it the fastest performance is achieved by not using the global resources for the logic part of the net, and that's all this message is telling you. Regards, Vaughn AlteraArticle: 67564
Vaughn Betz wrote: > You can directly instantiate any legal logic cell from within verilog > code by instantiating "WYSIWYG" logic cells. This lets you do any > amount of technology mapping you like, and mix it with HDL. > > The Verilog syntax that is used for instantiating a logic cell is > described in QUIP (Quartus University Interface Program), in the > document "stratix_wysuser_doc.pdf". You can instantiate logic cells > from inside VHDL code by writing a verilog file with the logic cells > you want, then instantiating that entity in your VHDL code. Thanks, that's useful and gets access to _everything_ but it's also a rather radical. Is there a less direct way to achieve parts of this, eg. will Quartus use the cascade chain for conjunctions when it could? Thanks, TommyArticle: 67565
In article <Kx_4c.73$QY2.8885@news20.bellglobal.com>,
Invisible One <Invisible_1@sympatico.ca> wrote:
>Sounds like you are talking about finite word length effects.... not what
>the original posting was referring to. Since you brought it up I suppose it
>can be discussed.
>Well, it looks like you are saying that in general, bit symbols are
>uniform... depends on the processing that is going on (distributions can get
>transformed!).
No, I am not saying that. The algorithms to produce
non-uniform random variables start out assuming that one
has uniform bits in the first place. The classical
algorithms use arithmetic operations on numbers.
For example, to generate exponential random variables,
one can take the negative logarithm of a uniform one.
There are other faster methods, but they involve such
things as rounded tables, and use up random bits at a
rate O(n), where n is the length, and computations on
numbers of length n.
Let me give a simple and not too efficient algorithm
for which it is not difficult to show that the
expected number of bits used is finite. I have
substantially better ones around. This one is taken
from a modification of von Neumann's.
In this, n is an integer, k is a 0-1 switch, and the other
quantities are as indicated. It is assumed that there is a
random bit stream available, from which bits can be taken
as needed. Once bits are used, they are no longer available.
start: n = 0;
oloop: J = distance to the first 1 in bit stream;
b = bit;
x = J-1 bits, followed by b;
if(b=0) go to fin;
z = x with b replaced by 0;
L = length(z);
k = 0;
iloop: J = distance to first 1 in bit stream;
if(J <= L) {b = J-th bit of x;
if(b=0) goto endi;
else {z = first J bits of z with bit J made 0:
k = 1-k; go to iloop}}
if(L < J) {b = bit; if b = 1 goto endi;
else {z = z followed by J-L-1 bits followed by b:
k = 1-k; go to iloop}}
endi: if(k = 1) goto fin;
n = n+1;
goto oloop;
fin: the output is the integer n, followed by x, followed by
as many bits as needed to fill out the output
It is not difficult to show that the expected number of
bits used in this procedure is finite, so the computational
complexity is "random finite", and the number of bits "wasted"
has a finite expectation. From the practical standpoint, I
do not believe that this particular algorithm, or any of the
better ones, is worthwhile with present word lengths, but for
some other situations, it can be better if the bit operations
are fast. One problem with this, or other procedures with
random numbers, is that the number of bits or numbers used in
an operation are themselves random, which adds to bookkeeping.
--
This address is for information only. I do not claim that these views
are those of the Statistics Department or of Purdue University.
Herman Rubin, Department of Statistics, Purdue University
hrubin@stat.purdue.edu Phone: (765)494-6054 FAX: (765)494-0558
Article: 67566Note: I was posting through Google Groups but not all of the messages were coming through and it was taking a long time so I dialed up and am now using something more substantial (but this is me the OP). >>*SRAM for some sort of L2 cache >>*JTAG port or some other programming interface >>*Flash memory for bitstream storage >>*CPLD for device management (loading config from flash) > > At that point you might as well design your own board in total. My point exactly :-) > No, I said a "passive" backplane. That accepts a PCI card with the CPU > on board. This would be a lot like the unit you describe above. The > only advantage is that it would allow you to plug in any PCI card for IO > that you would like. Sorry, I missed that on the initial reading. The more I think of it, this seems to be the ideal solution. Why get locked into a board with limited expansion capabilities when you can get something based on an industry standard architecture that allows for the integration of cheap, off the shelf components for I/O. Can anyone reccomend a vendor for good quality, relatively inexpensive PCI backplanes? Thanks again!Article: 67567
ramntn@yahoo.com (ram) wrote in message Check the list http://www.fpga-faq.com/FPGA_Boards.shtml unlikely that such a detailed spec already exists done to the tee but quite a few of those features exist on some of the family boards for X & A. We were just talking of mlj on another sim thread. Some vendors like Nallatech do things with a master PCI board with smaller plugin daughter boards for other functions you might have to do your self or ask for. There are very few interchangeable stds across the industry so far for such cards. google virtex pro + your most important features will help you find companies to look at quickly. regards johnjakson_usa_comArticle: 67568
Austin Lesea <austin@xilinx.com> wrote in message news:<c2nn1t$eq92@cliff.xsj.xilinx.com>... > Embedded IDs are very easy to crack. > > Just decap the part, and look for the laser fuse marks! > > Or, if they have fuses, look for which ones are blown. > > The advantage of the V2 & V2 Pro sram is that if the battery goes away, > the key goes away, and the IP was (is) secure. > > If they open the part up while operating, and try to read the sram > cells, hey, more power to them, as they have just blown a lot more money > and time on the IP than it was probably worth. They could have gone to > the manufacturer, waited for a smoke break, and asked "anyone have the > keys? I have $$$$ right here...." > > Never protect an expensive bike with a cheap lock, and conversely never > protect a cheap bike with Fort Knox. > > Austin In the black helicopter scenario the stuff of movies I have heard and slightly believe the following which does make some sense. If you are familiar with any eeprom technology or device physics your half way there. Power the device down, open up and locate the sram cells that hold the crypto code. If they can be got at with probes (layer stripping probably needed), measure the vts of both sides of the cells. If they can easily be reached, permanent presence of constant data leaves a shadow ie a vt drift on 1 side. It would be incredibly small though but increasing with time and voltage. That could be alleviated by the part taking steps to toggle the flops or to push the flop state closer to the bottom. HDs are supposed to have the same problem even when written over, the new data pushes down older data layers. Thats the problem with the real world, its analog. For enough reward, I'd look into by 1st experimenting and seing if the drift can be measured reliably with my own serial coded parts before attacking other ip, thats why the really serious stuff put charges in the package. But the other social techniques are probably easier. Btw, in the 80's James Bond story concerning Zorin semiconductors, the producers were originally interested in blowing up the Inmos Newport fab but it never happened. regards johnjakson_usa_comArticle: 67569
>In the black helicopter scenario the stuff of movies I have heard and >slightly believe the following which does make some sense. If you are >familiar with any eeprom technology or device physics your half way >there. It doesn't take black helicopters. Just modest amounts of cash. University resources: http://www.cl.cam.ac.uk/~mgk25/sc99-tamper.pdf http://www.cl.cam.ac.uk/~mgk25/sc99-tamper-slides.pdf It's very well done. I'd call it required reading for anybody interested in keeping secrets in chips. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67570
In article <1079137346.521365@haldjas.folklore.ee>, Sander Vesik <sander@haldjas.folklore.ee> wrote: >> Actually, thats not hyperthreading/SMT, thats >> interleaved-multithreading or C-slowing. See Chapter 11 and Appendix >> B: >> >> http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf > >Any particular reason you didn't use the term 'barrel processor'? C-slow appears >to be either a very new or very obscure term. C-slowing is an automatic transformation proposed origionally by leiserson many years ago. It can be AUTOMATICALLY applied to a processor core, which was the interesting part. The other term of note is "Interleaved-Mulitithreading", which is from Ghosh et al (IIRC), and it was "This is better than context-switch-on-event" model, without taking advantage of upping the clock rate with finer pipelinig. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67571
Magnus Homann wrote:
> Marc Randolph <mrand@my-deja.com> writes:
>
>
>>Adarsh Kumar Jain wrote:
>>
>>>if you are sure about the parity with which you comma is coming than you can
>>>choose which one to enable... else you can allow both..
>>>i am using ROCKET IOs as receivers only and I am not sure about the parity
>>>with which my commas will come, so i keep them both enabled...
>>>and they identify the words boundaries correctly and align data correctly...
>>>they can be deasserted later once you verify that the data aligned signal
>>>has gone high....
>>
>>Howdy Adarsh,
>>
>>IF you are using it for alignment, why would you later disable it? Are
>>you manually inserting alignment characters to get sync'ed up, then
>>later on sending raw data that might have have bit patterns that look
>>like sync characters?
>
>
> Because you don't want a bit-error to possibly re-align your
> bitstream, I guess.
Howdy Magnus,
Hmmm. Yeah, I guess that would work, and you could have some extra
algorithm which requires multiple bit-errors to before causing a
re-alignment.
Marc
Article: 67572nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<c332ec$2hgf$1@agate.berkeley.edu>... > In article <1079137346.521365@haldjas.folklore.ee>, > Sander Vesik <sander@haldjas.folklore.ee> wrote: > >> Actually, thats not hyperthreading/SMT, thats > >> interleaved-multithreading or C-slowing. See Chapter 11 and Appendix > >> B: > >> > >> http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf > > > >Any particular reason you didn't use the term 'barrel processor'? C-slow appears > >to be either a very new or very obscure term. > > C-slowing is an automatic transformation proposed origionally by > leiserson many years ago. It can be AUTOMATICALLY applied to a > processor core, which was the interesting part. > > The other term of note is "Interleaved-Mulitithreading", which is from > Ghosh et al (IIRC), and it was "This is better than > context-switch-on-event" model, without taking advantage of upping the > clock rate with finer pipelinig. Although I will use the barrel term from now on (I'd forgotten about it some time ago) I was 1st familiar with the idea in early 80s from a sig.arch paper, still in basement. I am also tempted to throw in planetary as in planetary gearbox, due to the way the inner and outer barrels work together as gears wheels mesh or lock with the inner or outer gear. This follows from the inner wheel always rotating at max speed carrying 4 processes or planets until such time as the instruction fetcher decides to change things like on branch or any other op that has an indefinite outcome. In that case the corresponding planet appears to lock with the inner & outer gears for 1 cycle (qtr rotation) forcing a process exchange from the static list of 12 others (on the outer rim) in ram ie it makes the outer gear follow for 1 cycle. This leads to 3 graphics, 1) every instruction pushed into the queue with Pid has a different Pid, ie the HW or the instr fetcher feels the need to keep changing process every cycle. This has the effect of dragging the outer wheel with the inner wheel always. It shares time more fairly but it also loses many opportunities for succesive ops in one process to take advantage of their previous result 4cycles before to reduce no of memory accesses to cache. Another way is to see the inner gear as a window over the outer gear, now this is just a 16 way barrel with 4 parts in HW registers sliding over the 16 bit ram. 2) every instruction pushed into the queue looks ok so the next one keeps following, ie no branches. This is the pure 4 way barrel, never shares with the outer barrel any time and can't handle a branch since the change won't get back in time. This would lead straight back to adding branch prediction and so. 3) a mix of the 2 above, pretty difficult to write by hand programs with out any branches or programs that might branch every cycle but a HDL to C cycle compiler or a HDL to C event simulator could produce such code, but thats another paper. regards johnjakson_usa_comArticle: 67573
Hi, first of all thanks to everyone who was helpfull. We are indeed running version 6.1.03i maybe that's the problem. Anyway, I managed to program to the same purpose, but in a way around, so the problem is solved. In my oppinion the proplem might have been a combination of the last two posts. Thanks a lot everybody!Article: 67574
Hi , I am facing some problems in Rocket I/O.In the deserialiser side the EOP character "FD"(K29.7) is not detected properly i.e the RXCHARISK is not being set for "FD". Any one can comment what is the problem.I am using GT_CUSTOM component for ROCKET I/O. rgds, prav "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message news:<c2s23j$eh0$1@sunnews.cern.ch>... > if you are sure about the parity with which you comma is coming than you can > choose which one to enable... else you can allow both.. > i am using ROCKET IOs as receivers only and I am not sure about the parity > with which my commas will come, so i keep them both enabled... > and they identify the words boundaries correctly and align data correctly... > they can be deasserted later once you verify that the data aligned signal > has gone high.... > "prav" <praveenkn123@yahoo.com> wrote in message > news:863df22b.0403112113.58acece8@posting.google.com... > > Hi all, > > > > I am using virtex2p rocket I/O i am using the component gt_custom. > > in this component two of the ports are namely ENMCOMMAALIGN and > ENPCOMMAALIGN. > > My doubt is what is the differnce b/w minus-comma and plus-comma and which > of > > the above ports should be enabled. > > > > > > rgds, > > prav
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