Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I am using the GPIO as interface between the ppc and fpga. Then I try to design a prototype for read/write the BRAM in FPGA from ppc. I am not sure if the ppc and FPGA can share a BRAM. Look forward to any other idea. Terrence "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.LNX.4.58-035.0403112220270.21663@unix45.andrew.cmu.edu... > Hi, > I have been creating a design extensively in hardware and I would like to > be able to have a powerPC write to block RAMs that are in my HW design. > Can someone point me in the right direction. > > What sort of bus do i need to create? > > Any pointers would be much appreciated. > > Thanks > > MattArticle: 67451
In article <adb3971c.0403111708.15fabb59@posting.google.com>, john jakson <johnjakson@yahoo.com> wrote: >Absolutely true. Without it, having to deal with all the hazards would >wreck the performance and up the design effort enormously. A previous >design was single threaded and had the forwarding logic, but had too >many other complexities to deal with in FPGA to be fast or >completable. Although careful design can get the forwarding path very short. EG, the Nios described in FPGA 2004 has a 2 LUT level for the entire ALU, including forwarding path, by clever use of features. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67452
john jakson wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message > > > > > > > Post synth. > > > > OH!!! My experience is that the synth tools do a lousy job of > > estimating total delay. You can expect your routed delays to be twice > > that or more. If you are seeing 400 MHz post synth, you will be lucky > > to get 200 MHz after routing. If you don't floorplan well, you may see > > <100 MHz. > > > > -- > > > > I will definitely floor plan, I am old hand at it from VLSI days, but > while the logic is unstable doesn't make much sense to spend time on > it. But it certainly cuts the route lengths way down and puts all > related LUTs and related FFs together, and the pics even look sorta > nice. I still have to write some auto magic ucf writer code to speed > up the edit sessions. I think you are missing my point. If you are counting ns before you have routed, you are not counting anything real. Do a place and route, then tell us what speed you get. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67453
Hi all, I am using virtex2p rocket I/O i am using the component gt_custom. in this component two of the ports are namely ENMCOMMAALIGN and ENPCOMMAALIGN. My doubt is what is the differnce b/w minus-comma and plus-comma and which of the above ports should be enabled. rgds, pravArticle: 67454
john jakson wrote: ..... > model and expensive NRE for special smp controllers. A couple of > slower Transputers should easily be able to beat 1 faster x86 at any > task. Even Intel is seeing the light. But Intel doesn't understand > Occam and is stuck with x86 rock around its neck. ..... > sorry to sound like blowing my own horn, but the possibilities of FPGA > technology seems far more interesting than the endless x86 drivel on > comp.arch. No John, more power to you. You have to love FPGAs for giving mere mortals such as ourselves the power to play computer architects. Though I don't share your belief in Transputers (sw is a major deal), watching you try is very exciting and pushing a cpu design to the limit is something probably most of us enjoy. I look forward to seeing your Transputer! Tommy PS: Be wary of the ivory tower and consider replacing Occam with something more like Handel-C. Occam was just an awful language IMHO.Article: 67455
Nicholas C. Weaver wrote: > Although careful design can get the forwarding path very short. EG, > the Nios described in FPGA 2004 has a 2 LUT level for the entire ALU, > including forwarding path, by clever use of features. Darn it Darn it Darn it :-) Is there account of this presentation in accessible electronic form anywhere? Or could you shed a little more light at how they accomplished that? Thanks, TommyArticle: 67456
> What sort of bus do i need to create? Just yesterday I got my design working ... I'm doing the same with a microblaze and the opb bus: in the EDK I take a opb_bram_if_cntrl and connect it to the opb ... the bram-ports of this component are put outside ... I wrote them manually in the .mhs file outside in my normal system there is a core-generator dual-ported blockram and thats where I connected my signals ... I merged the WEN-vector and WE together to the bram-wr/rd ... the adress-mapping got complicated ... my blockram used a (11 downto 0) description whereas the module uses (0 to 31) ... I guess I sould connect (18 to 29) from the if-cntrl to my bram-addresses - thats what I'll try after breakfast! I'm interested ... What are you trying to do with it? I'm building a On-Sreen-Display into a camera ... System: EDK3.2 with sp?, ISE 5.2sp3, virtexII 1000 bye, MichaelArticle: 67457
Hi, I would remove the pin assigment in Quartus (since you not using the pin it should not be in your design). Second you have the option to set (Assignment/Settings/ -> Device tap and Device and pin option button -> Unused pin tab) all unused pins to tri-state. I guess this is what you want if you have a signal on a pin that is not used. (Acctually the same thing is done on the Nios boards). Cheers Fredrik "Pszemol" <Pszemol@PolBox.com> wrote in message news:<c2pe9h.54c.0@poczta.onet.pl>... > Hi, > I have been working for a little time with Altera Cyclone part > and I have my project almost ready to go. I am in the process > of cleaning things up and I need to review all warnings I got > from the building process. > One of them is "Warning: Pin XXX not connected" - it is right, > I have a track with signal on PCB going into the Altera part > but later on I decided to not use it in my FPGA design... > > What is the common practice of dealing with such pins to clear > this warning and do not short this pin with signal to ground/vcc? > > I hate the practice of ignoring any "stupid" warnings because it > quiets my sensitivity for wornings which are potential errors. > When I write any piece of software I try to clean it the way > no warning is reported during the build process. I want the same > happened in Quartus software during my FPGA design synthesis. > > Thanks for any input.Article: 67458
Take a look at this document, you will see how an LE and a slice is made up of... > http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf Kelvin Tong <nospam@cuhk.edu.hk> wrote in message news:c2mmt6$1h7c$1@justice.itsc.cuhk.edu.hk... > hi Kelvin, > > Yup, I come from The Chinese University of Hong Kong. > I don't think my professor is fooling me. May be I should state clearly what > I have to do. > > The poject do not require us to make a real chip. We just use magic to draw > the layout and use irsim to simulate. And, it is a group poject. > > Could you shed a light on my project? > > > Regards, > Tong > > > "Kelvin @ SG" <kelvin8157@hotmail.com> ¼¶¼g©ó¶l¥ó·s»D > :404e7739@news.starhub.net.sg... > > it seems your professor is fooling you...i guess designing a decent FPGA > > chip will require a big team of > > engineers and top of the line Cadence & Mentor softwares...be prepared to > > pay hundreds of thousands US$ > > for the licenses alone...besides, it seems u r from a Chinese > university... > > > > > > > > Tong <nospam@cuhk.edu.hk> wrote in message > > news:c2km7a$ko9$1@justice.itsc.cuhk.edu.hk... > > > hi all, > > > > > > I am a undergraduate studying VLSI and Magic manul layout. My professor > > have > > > asked us to design an FPGA chip using Magic. > > > I am confused in how to build the switch box and look up table. Could > > anyone > > > kindly recommend some website or books that gives detail explanation on > > > these stuff. > > > > > > Thanks a lot. > > > > > > Regards, > > > Tong > > > > > > > > > > > >Article: 67459
Praveen, The ENxCOMMAALIGN ports allow you to align the incoming data to a comma character that has either negative disparity (ENMCOMMAALIGN) or positive disparity (ENPCOMMALIGN) or even both. When realignment of the data takes place due to a comma being detected (depending on ENxCOMMAALIGN), the RXREALIGN signal will indicate this. More detailed information can be found in the RocketIO User Guide under "SERDES Alignment" http://www.xilinx.com/bvdocs/userguides/ug024.pdf --Stephan prav wrote: > Hi all, > > I am using virtex2p rocket I/O i am using the component gt_custom. > in this component two of the ports are namely ENMCOMMAALIGN and ENPCOMMAALIGN. > My doubt is what is the differnce b/w minus-comma and plus-comma and which of > the above ports should be enabled. > > rgds, > pravArticle: 67460
john jakson <johnjakson@yahoo.com> wrote: ... : The technology died out because Inmos didn't have their act together : and FPGAs weren't around to help them prototype. The 2 tchnologies : .. Actually Inmos was bought by ST and when the T800 came out after the merge it was the first chip with more bugs than transistors :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 67461
in attempt to compare the logic utilization for MAX2 devices I got very interesting results. Tried to compile a 16 bit babyrisc: QII-V4 MAX1270 544LE 42% (MAX570 no fit!!) MAX7000 no fit but no fatal error Cyclone: ============================================================================ Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line: 5815 index >= 0 && index < number_of_globals (Fitter pre-processing) Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition ============================================================================ ISE 6.1 XC2S30 275 Slices 63% XC95-autoXL fitter fails with windows general protection fault XC2C-auto ============================================================================ java.lang.ClassCastException: org.apache.xalan.res.XSLTErrorResources_de at org.apache.xalan.xslt.Process.main(Unknown Source) Exception in thread "main" Considering device XC2C512-6-PQ208. ============================================================================ So A can relax, similar fatal errors are coming with the X software too! Antti Lukats P.S. MAX2 is not a PLD but more like instant-on FPGA with no dedicated RAM resources.Article: 67462
Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote in message news:<Pine.LNX.4.58-035.0403112220270.21663@unix45.andrew.cmu.edu>... > Hi, > I have been creating a design extensively in hardware and I would like to > be able to have a powerPC write to block RAMs that are in my HW design. > Can someone point me in the right direction. > > What sort of bus do i need to create? you can create a peripheral that has a "transparent" bus and connect that to the BRAM. We have done a design where a AVR RISC is used as CPU it has LMB bus and from LMB bus special wrapper to connect to BRAM and it is possible to use XPS to connect the BRAM to the system. similarly you can write your peripheral that connect to any bus (from processor side) you choose and have a transparent type of bus to connect to BRAM, the other side of BRAM can be connected to FPGA, but you would need another core that connects to that other side and exports signals to be used in ISE toplevel. alternativly you can write a peripheral core that exports some signals to ISE toplevel and then wire up the BRAM there. We are doing this in one desing, where are using OPB to AHB wrapper and exporting the AHB bus from EDK system to ISE toplevel where we have a AHB dual port RAM (just a wrapper around BRAM). The other side of the BRAM is connected to USB OTG core. Antti LukatsArticle: 67463
"Fredrik" <fredrik_he_lang@hotmail.com> wrote in message news:77a94d51.0403112344.64eb86c4@posting.google.com... > Hi, > I would remove the pin assigment in Quartus (since you not using the > pin it should not be in your design). Second you have the option to > set (Assignment/Settings/ -> Device tap and Device and pin option > button -> Unused pin tab) all unused pins to tri-state. I guess this > is what you want if you have a signal on a pin that is not used. > (Acctually the same thing is done on the Nios boards). > Cheers > Fredrik That's not always a good solution - maybe you have a pin that is not in use at the momement, but you know that it might be in later designs. Specifying it as a pin assignment early on means you only do the assignments once, instead of having to add it in at a later stage. There are also often occasions where a module (VHDL, Verilog or schematic) produces outputs that are not used in the rest of the system, or which have inputs that don't get used in the module, but you want to keep them for consistency or flexibility. Is there any more general way to disable such warnings? When doing normal schematics, I use a "no-ERC" mark (a little cross) to indicated intentionally unconnected pins - is there anything similar for fpga design (either Quartus-specific, or general to VHDL or Verilog) ? > "Pszemol" <Pszemol@PolBox.com> wrote in message news:<c2pe9h.54c.0@poczta.onet.pl>... > > Hi, > > I have been working for a little time with Altera Cyclone part > > and I have my project almost ready to go. I am in the process > > of cleaning things up and I need to review all warnings I got > > from the building process. > > One of them is "Warning: Pin XXX not connected" - it is right, > > I have a track with signal on PCB going into the Altera part > > but later on I decided to not use it in my FPGA design... > > > > What is the common practice of dealing with such pins to clear > > this warning and do not short this pin with signal to ground/vcc? > > > > I hate the practice of ignoring any "stupid" warnings because it > > quiets my sensitivity for wornings which are potential errors. > > When I write any piece of software I try to clean it the way > > no warning is reported during the build process. I want the same > > happened in Quartus software during my FPGA design synthesis. > > > > Thanks for any input.Article: 67464
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0403110735.71e1b6e8@posting.google.com>... > jon@beniston.com (Jon Beniston) wrote in message > > > The timing report is essentially > > > same as before, no special warnings but some improvement in compile > > > time I was looking for. > > > > Is that post-synthesis or post-layout? > > > > Post synth. As another poster has mentioned, expect to see a big drop off in performance after layout. I have noticed that sp3 synth results are significantly more optimistic than for other archs. > Don't have Symplify or full ISE budget, but would gladly accept a free > license if anyone is listening. email at bottom. Most EDA companies will let you do a months eval for free. Very handy if you time it just right. > Not a big fan of GPL. If no $ licenses are forthcoming, I will fold > the them both into MIT/BSD and let the world rip into it. I meant offer it under dual licenses. One GPL the other $$$. If you use the LGPL there is less chance that people will be willing to pay. I'm all for open source, but there still should be a way to earn a decent living.. Cheers, JonBArticle: 67465
Jesse, > Have you re-generated your SOPC Builder system (Nios and all > peripherals) for the Apex family? I think so... I avoid this problem in the past (I connected in other way my NIOS with logic in Apex), but now I have this problem again :-(. I don't know, what I have to do :-(. I added fifo megafunction and when I try control it by NIOS, the same errors appear. Pleaaaase help me :-) LeszekArticle: 67466
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<40512826@news.starhub.net.sg>... > Hi, there: > > I am wondering whether XST handles // synopsys parallel_case? > > Plus, How do I know XST has taken in the // synthesis parallel_case? I > didn't see any such > information in the synthesis transcripts with either //synopsys or > //synthesis... Look at the logic it synthesizes. Cheers, JonBArticle: 67467
if you are sure about the parity with which you comma is coming than you can choose which one to enable... else you can allow both.. i am using ROCKET IOs as receivers only and I am not sure about the parity with which my commas will come, so i keep them both enabled... and they identify the words boundaries correctly and align data correctly... they can be deasserted later once you verify that the data aligned signal has gone high.... "prav" <praveenkn123@yahoo.com> wrote in message news:863df22b.0403112113.58acece8@posting.google.com... > Hi all, > > I am using virtex2p rocket I/O i am using the component gt_custom. > in this component two of the ports are namely ENMCOMMAALIGN and ENPCOMMAALIGN. > My doubt is what is the differnce b/w minus-comma and plus-comma and which of > the above ports should be enabled. > > > rgds, > pravArticle: 67468
Adarsh Kumar Jain wrote:
> if you are sure about the parity with which you comma is coming than you can
> choose which one to enable... else you can allow both..
> i am using ROCKET IOs as receivers only and I am not sure about the parity
> with which my commas will come, so i keep them both enabled...
> and they identify the words boundaries correctly and align data correctly...
> they can be deasserted later once you verify that the data aligned signal
> has gone high....
Howdy Adarsh,
IF you are using it for alignment, why would you later disable it? Are
you manually inserting alignment characters to get sync'ed up, then
later on sending raw data that might have have bit patterns that look
like sync characters?
Regards,
Marc
Article: 67469> I think you are missing my point. If you are counting ns before you > have routed, you are not counting anything real. Do a place and route, > then tell us what speed you get. I would agree with Rickman here Jon, have all the speed figures you've quoted when discussing this project been based on synth results? If so be ready for a big disappointment when you P+R the finished design. Floorplanning will help, but I usually reckon on real results being 60 - 70% of what the synth tool says. Nial.Article: 67470
In article <Kqd4c.8069$_3.101237@typhoon.sonic.net>, <TommyInTheNews@numba-tu.com> wrote: >Nicholas C. Weaver wrote: >> Although careful design can get the forwarding path very short. EG, >> the Nios described in FPGA 2004 has a 2 LUT level for the entire ALU, >> including forwarding path, by clever use of features. > >Darn it Darn it Darn it :-) Is there account of this presentation in >accessible electronic form anywhere? ACM subscribers can get the paper. I don't know of the slides being online somewhere. >Or could you shed a little more light at how they accomplished that? Using lots of Altera features and cleverness to combine things, including the LUT cascade chain. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67471
"Nicholas C. Weaver" wrote: > > Using lots of Altera features and cleverness to combine things, > including the LUT cascade chain. I like the cascade chain concept. It can make wide muxes much easier. But I have never been able to get the tools to use it for combining more than two LUTs when using HDL. Any suggestions on how to do this? I will be optimizing a design after it is fully debugged and this is one of the first things I want to address. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67472
In article <4051D7D1.15FFE3E7@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >"Nicholas C. Weaver" wrote: >> >> Using lots of Altera features and cleverness to combine things, >> including the LUT cascade chain. > >I like the cascade chain concept. It can make wide muxes much easier. >But I have never been able to get the tools to use it for combining more >than two LUTs when using HDL. Any suggestions on how to do this? I >will be optimizing a design after it is fully debugged and this is one >of the first things I want to address. The altera crew hand-mapped the logic, using Altera's features to specify exactly whats in a LUT. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67473
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<%1h2c.34366$ws.3433570@news02.tsnz.net>... > Stewart Smith wrote: > > > Thanks for your response and I'm sorry about my vagueness about > > certain points, what I meant by a single pin output, is that this > > single output from my frequency ramp CPLD would be the clock source > > for another CPLD which would contain the three pole switching sequence > > (this bit I've managed to do), it is this sequencing frequency that I > > have hopes of using to control the motor speed. > > > > This assignment has been previously undertaken successfully, with > > using only two of the 20v8 devices and this is what where actively > > encouraged to limiting ourselves to. > > > > I suspect the softstart to be much cruder than the type you have > > suggested (which is probably the correct method). > > > > In your reply you mention a "tapped divider, exponent pointer, or Mux > > selector" could you possibly suggest an example of how these are coded > > in cupl. > > Somewhere you have to generate the clock to determine the Step freq. > If that is external, from a SigGenerator or similar, then you need > a way to proportionally gate that. > > Look into Rate Multipliers : These have Fo = N/Base output, so > a 4 bit binary one can start at 1/16 fi, and step thru 2/16,3/16 > up to 16/16 Fi, in linear frequency steps > > Rate Multiplier info is not easy to find, so here is one ref : > http://focus.ti.com/docs/prod/folders/print/sn7497.html > > Then the 4 Bit number that feeds this Rate Multiplier, could derive from > a saturating counter (one that counts to a MAX, and then stops until > reversed. ) > The step rate of the RateNumber determines the soft-start, so you could > clock that from the Phase signals, or a divided version of the phase > signal for slower still Start-rate. ( so far, you have used only 3 bits > of the PhaseGen PLD) > > - this will give a revolution proportional slow start, which may > be too conservative at very low step rates, but it is simple, and you > can fit both the 4 bit rate Multiplier Ctr, 1 rate MergeCell, the 4 bit > saturating Ctr, Delayed Dirn BIT, and your 3 bit phase engine into 2 PLDs. > > The Delayed Dirn bit is some fine-tuning, that would only allow DIRN > to be changed ONLY at the LOWEST possible rate value. > > -jg Thank you for taking time to respond Have looked into the link you suggested and, no problem for me to use this type of device, in fact they have them in stock at uni which is handy. This definitely seems a step in the right direction. The external clock source I thought was maybe to use a waveform generator which could be fine tuned to my max Frequency requirements. When you suggest using the phase signal to clock the step rate is the Mergecell you refer to, which in turn then would be the clocking signal to the counter pld. Can this be done internally or do I need to feed back physically to three input pins. Would be interested on what you think, the Dirn bit should look like. I am still looking into the coding for the saturating up/down counter, can get it to count up and down no problem getting it stop any stage is another thing. StewartArticle: 67474
"David Brown" <david@no.westcontrol.spam.com> wrote in message news:c2s00e$jo7$1@news.netpower.no... > There are also often occasions where a module (VHDL, Verilog or schematic) > produces outputs that are not used in the rest of the system, or which have > inputs that don't get used in the module, but you want to keep them for > consistency or flexibility. Is there any more general way to disable such > warnings? Funny you have mentioned this one because I have a lot of worrying warnings messages like this one (I have exchanged the long path to the chip with X mark): "Warning: Reduced register X|rxcntlsm:u1|state~34 with stuck data_in port to stuck value GND" The module 'rxcntlsm' is a state machine for UART receiver written in VHDL. During the synthesis, Quartus unfortunately converted state names to numbers and I am confused what states are creating problems, or are they problems at all. Can you help me with this? There is some reference to states and its numbers but it is not clear which one is which (again edited messages with "X" mark): Info: Encoding result for state machine X|rxcntlsm:u1|state Info: Completed encoding using 15 state bits Info: Encoded state bit X|rxcntlsm:u1|state~34 Info: Encoded state bit X|rxcntlsm:u1|state~33 Info: Encoded state bit X|rxcntlsm:u1|state~32 Info: Encoded state bit X|rxcntlsm:u1|state~31 Info: Encoded state bit X|rxcntlsm:u1|state~30 Info: Encoded state bit X|rxcntlsm:u1|state~29 Info: Encoded state bit X|rxcntlsm:u1|state~28 Info: Encoded state bit X|rxcntlsm:u1|state~27 Info: Encoded state bit X|rxcntlsm:u1|state~26 Info: Encoded state bit X|rxcntlsm:u1|state~25 Info: Encoded state bit X|rxcntlsm:u1|state~24 Info: Encoded state bit X|rxcntlsm:u1|state~23 Info: Encoded state bit X|rxcntlsm:u1|state~22 Info: Encoded state bit X|rxcntlsm:u1|state~21 Info: Encoded state bit X|rxcntlsm:u1|state~20 Info: State X|rxcntlsm:u1|state.wait_start uses code string 000000000000000 Info: State X|rxcntlsm:u1|state.synch uses code string 000000000000011 Info: State X|rxcntlsm:u1|state.wait_data uses code string 000000000000101 Info: State X|rxcntlsm:u1|state.sample_data uses code string 000000000001001 Info: State X|rxcntlsm:u1|state.wait_parity uses code string 000000000010001 Info: State X|rxcntlsm:u1|state.sample_parity uses code string 000000000100001 Info: State X|rxcntlsm:u1|state.wait_stop1 uses code string 000000001000001 Info: State X|rxcntlsm:u1|state.sample_stop1 uses code string 000000010000001 Info: State X|rxcntlsm:u1|state.wait_stop2 uses code string 000000100000001 Info: State X|rxcntlsm:u1|state.sample_stop2 uses code string 000001000000001 Info: State X|rxcntlsm:u1|state.db1_data uses code string 000010000000001 Info: State X|rxcntlsm:u1|state.db1_parity uses code string 000100000000001 Info: State X|rxcntlsm:u1|state.db1_stop1 uses code string 001000000000001 Info: State X|rxcntlsm:u1|state.db1_stop2 uses code string 010000000000001 Info: State X|rxcntlsm:u1|state.overrun uses code string 100000000000001 How do I read the above? The warning about "reducing register state~34" repeats for state~33, state~32, state~31 and state~30 as well, which is even more worrying...
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z