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I've got 30 spartan2s sat next to me now. I went for the TQ144 package. We soldered them on ourselves here, onto two layer boards. BGA is of course a completely different issue, but if you're using 'low cost' FPGA's you'll probably find one with a more 'sensible' package (such as TQ144)!! Andy Andre wrote: > How many layers are normally needed for PCBs using low cost FPGAs ?? > > I've just been told by a supposed board layout expert that the 256 pin > BGA version of a Cyclone EP1C6 would require an 8 layer board > (apparently having the entire underside of the device covered by balls > with no free space at the centre makes signal routing a big problem). > > Is this really true ?? -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 66176
Well ! this is great. Almost exactly what I want, just that I want it to put it my own board (I'm designing my PCB still). I think I'm getting closer to be able to use the PLL core in the FPGA, which is my ideal solution. But I'll keep in mind your system. On a separate note, could someone please suggest a good and fast news server (public preferably) where to read/post to this newsgroup? I'm just using Google's web interface and it takes almost 3 hrs. for my own post to show up, and by then I notice some of you guys have already several replies to the post that I can't see yet. (I see the replies in news-reader.org but I can't post there) Thanks. David "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:<Pr_Wb.24547$Tu6.22239@newssvr25.news.prodigy.com>... > he, I may have a solution > http://www.fpga4fun.com/shop_I2CPLL.html > > Did this project just a few weeks back... > JeanArticle: 66177
Hi Pablo, Interesting idea ;) Our board is going to have an ARM and an FPGA tightly coupled as well. But we will have a lot more of course. Having gone down this road before, I would recommend that you used different devices than the two you have picked. I think you will find it is cheaper to use an ARM with internal Flash and RAM. Of course how much you need depends on your application and a SOC ARM may not have enough. But you can sell the board with/without the external Flash and RAM to make a low cost version possible. We picked the OKI ARM chips, the ML67Q5003 in particular. It has 32 kB RAM and 512 kB Flash on chip. It also has tons of IO and multiple IO devices (UARTs, SPI, I2C, ADC...). It will directly support SDRAM and provides chip selects for Flash and IO devices. The Spartan IIE FPGAs are ok devices, but as someone else pointed out, they are not very low power. They also have an issue with a power on current surge that requires 0.5 Amps of current minimum without allowing the voltage to drop. And all this is during the voltage ramp up process! Then to top it all off, these parts are not 5 volt tolerant. There are still a lot of apps that need to interface to 5 volt signals. We picked the Altera EP1K series of FPGAs. They are fairly low cost and less power hungry than the Spartan IIE devices. Their power on current is much lower and the core voltage matches the OKI ARM chip. Pablo Bleyer wrote: > > Hello group. > > We would like you to share with us your comments and opinions about a > product we are planning to launch. Your feedback will be very helpful to > determine the interest in this kind of product, and important to establish > its development path and features (including, of course, price, so by > helping us you may be helping yourself ;^) > > This is a low cost, low power little board (3"x2") we designed to use in our > own custom control & data acquisition projects, but the concept turned out > so nice and nifty that we are evaluating the possibility to commercialize it > as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI > with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power > supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a > programmable clock oscillator. Expansion headers are provided for all > important board signals (120, including power pins), with top and bottom > stack mount capability. > > Most MCU and FPGA pins are shared to provide a flexible interfacing > architecture. The FPGA can be used for logic interfacing, data processing, > video output and LCD interface, hardware UARTs and other kind of > communications, etc. > > We would like to introduce this first as a basic kit with all the necessary > tools to get one started (core module, adapter board with serial > transceivers, wiggler-like JTAG programmers, software). The board itself is > a wonderful combo-kit for learning about embedded systems with the ARM > architecture and FPGAs. Most of the software and applications will be > provided as open source and a web site with useful information (application > notes, code and FPGA cores) will be set up. An eCos profile for the board > will be made available too. > > We also have designs for a backplane and auto-configuring add-on modules > with analog and digital IOs, Ethernet interface, IrDA and RF transceivers, > CompactFlash interface, etc. Our idea is to make them available once we can > reinvest and verify enough demand for each kind of device. > > The board can be configured for 1V-3.6V input operation using an efficient > step-up regulator, targeted mainly for battery powered applications. > Another configuration allows not installing the FPGA and using a cheap LDO > regulator for cost-sensitive applications where the FPGA is not necessary > and power efficiency is not of concern. > > You can take a look at some pre-production kit items at > http://www.embedded.cl/gallery/ARMermelator > > In particular, you would help us a lot with your answers and suggestions for > the following: > - How much will you be willing to pay for a kit like this. How much for core > boards in quantities? > - Do you think the FPGA configuration (ie, FPGA present on the board) will > be useful for you? Would you choose this board over other similar products > because of its FPGA functionality? > - Concerning the kit, do you think a base board with integrated programmers, > serial transceivers and prototyping area would be more useful to you than an > adapter board and separated programmers? > - What kind of applications and solutions to your needs do you envision > using a board like this? > - Without knowing further details, your overall impression about this > product. > > Well, thank you very much in advance. Sorry for the long post and sorry if > the content of this post sounded too much like marketing instead of > technical matters -- we are not trying to offend anyone but to help us all. > > Warmest regards. > > -- > PabloBleyerKocik / > pbleyer /"Simplicity is prerequisite for reliability." > @embedded.cl / -- Edsger Wybe Dijkstra -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66178
steve41@totalise.co.uk (Steve) wrote in message news:<4d3ee211.0402130309.4e48eeec@posting.google.com>... > Austin Lesea <austin@xilinx.com> wrote in message <big snip> Anyway, I suggest we leave this thread here so we can let you Xilinx guys get on with "seriously looking at ways to improve the plight of the low-volume customer", and of course to avoid rickman doing something his therapist has told him not to... ;) Then later in the year when the best-selling Spartan 3 chips are being shipped in their millions we can all compare the high and low volume prices again.... -- SteveArticle: 66179
Remis Norvilis <Norvilis.spam@charter.net.fake> writes: > I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome. Current versions of Xilinx XST, Altera Quartus, and Synplify Pro all support mixed verilog/VHDL designs. DavidArticle: 66180
You could try http://www.stratforddigital.ca/products/sputnik/ James Momrrison Hardware Designer NDI 103 Randall Drive Waterloo, ON, Canada N2V 1C5 Telephone: +1 (519) 884-5142 Toll Free: +1 (877) 634-6340 Global: ++ (800) 634-634-00 Facsimile: +1 (519) 884-5184 Website: www.ndigital.comArticle: 66181
Guy, LOCKED is an output from the state machine which is clocked by CLKIN. That makes it synchronous. It must follow (shortly) after a rising CLKIN edge. PSDONE is from the phase shift state machine, so that output is synchronous to that clock. If PSCLK and CLKIN are from the same source, then that solves that. Austin Guy Eschemann wrote: > I would like to use the "locked" output of a DLL to make sure that my > internal logic (ie. FSMs) doesn't start-up until a stable system clock > is available. > > I'm not sure if the "locked" signal is already a synchronous one, or > if I better use a 2-stage synchronizing circuit to move it to my > system-clock domain. Anyone knows ? > > Many thanks, > Guy.Article: 66182
Steve wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<402C6ABD.2A9E6871@yahoo.com>... > > Steve wrote: > > > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<402ABE46.861C779A@yahoo.com>... > > > > > > > Hey Steve, why don't you get off the soapbox. What you are doing is not > > > > getting you anywhere and is starting to tick me off. Until you give a > > > > call to your distributor and *ask* what price you can get, I don't want > > > > to listen to your rants. > > > > > > So far in this thread I've been accused of not understanding > > > economics, pricing or capitalism; seemingly just because I've had the > > > audacity to question Xilinx's low quantity prices. Basically, if > > > they're going to patronise me then I'm not going to just sit here > > > quietly and take it. > > > > You are not making any sense. By definition X and A have an oligopoly. > > So what is your point? > > I was responding to Peter Alfke's comments about X and A not being an > oligopoly: > > "The Columbia Encyclopedia describes oligopoly as: > ...the control of supply by a few producers...or by agreements among > members of an industry to restrain price competition... > > Does that describe your impression of the relationship between X and A > ? > Wow !" > > > Your questions have no point. Your statments > > are about the obvious. > > From: > > http://www.xilinx.com/prs_rls/silicon_spart/03142s3_pricing.htm > > "The 3S50, 3S200, and 3S400 Spartan-3 devices with 50,000, 200,000, > and 400,000 system gates respectively, are available for less than > $6.50*. The 3S1000 Spartan-3 device with 1 million system gates is > also available for under $12.00*." > > The cheapest XC3S400 (400k gates) in small quantities here: > > http://www.plis.ru/price.html?ID=126 > > is $28.90, that's 4.45 times as expensive. The difference will narrow > when production is ramped up to maximum, but how much will it narrow > to? Three times the price, twice the price? I think everyone who is interested in using these parts, know the prices. That has been discussed here before. Your posts shed no new light on the matter. Also, as I and others have mentioned before, if you pay list price it is your own fault. Like when you buy a new car, anyone can get a price cut just by asking. But instead of asking, you start spewing here. > > You are not telling anyone here anything they > > don't already know. > > Oh, so you don't mind paying highly inflated prices? Fair enough. Actually, if I am only building 10 boards, no I don't mind paying more for the parts because my time and expense far over shadow the cost of the chips. As others have pointed out, this is not a factor of there being an oligopoly. This is a simple fact of volume production. But then that has been explained to you before. > > You are just acting like a spoiled brat throwing a > > tantrum because he can't have dessert. > > To be perfectly honest the only person ranting round here is yourself. > > > Are you just trolling or do you have a point? > > I've made my point and I can't be bothered to make it again. Good, you have already said it more than enough times. Why is this such an issue with you? You have never explained how this pricing affects you. Is there a board you want to sell that is priced too high because the qty 10 prices on FPGAs are too high? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66183
"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<102ok9hpug47378@news.supernews.com>... > Hi Greg, > > I was thinking more in terms of SI rather than routing difficulty. > > In that case let me share how we handled that on only two signal layers. (We > did to a split PWR plane, BTW) > > It was a challenge with all the pins and signals and we wound up using a > routing service. The company does nothing but apply a full up SPECTRA > auto-routing system as a service to others. They were so knowledgeable and > helpful and the whole transaction was done by email and phone over a few > days. The price was incredible and now we'll save much more than their fee > every batch of boards due to the fewer number of layers. Did you make it past emissions testing? At what rate do your signals change? How is signal integrety? Getting a few boards to work in the lab is not as tough as getting a design to work in production in different envirinments while meeting goverment regulations.Article: 66184
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:puWWb.23870$ws.2959636@news02.tsnz.net... > Austin Lesea wrote: ... > > How many people need GHz divide by capability? > > Frequency synthesisers would be one, and precise time/phase measurements > could be another. Precise time is a little more difficult, as you > need to capture, but this would, of course, clock on both edges :) ... For much of the time precision, latching the value of the DCM's delay line could give extreme input resolution (resolution of a single tap though the accuracy would be slightly worse than one tap). I'd love to get down to ~100ps accuracy for sampling some very low frequency signals. If I could provide multiple phase-shifted outputs based on multiple phase-sampled inputs, I'd be in FPGA heaven. It seems like throwing a SERDES at a signal that toggles well under 100MHz is overkill especially when we need the low cost parts. For now, it's a matter of sampling on several phases to get a 4x or 8x the master clock resolution. Adequate, perhaps, but not awe-inspiring.Article: 66185
He's always got the option of not using FPGAs if he feels there is a better or cheaper approach.
If he cannot find a cheaper alternative, then there should be no reason to complain, right? If he
can, then he should use that cheaper alternative, and again, there is no reason to complain.
Obviously, the price point for FPGAs is not so far off the mark since people do use them.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66186Pablo Bleyer wrote: > Hello group. > > We would like you to share with us your comments and opinions about a > product we are planning to launch. Your feedback will be very helpful to > determine the interest in this kind of product, and important to establish > its development path and features (including, of course, price, so by > helping us you may be helping yourself ;^) > > This is a low cost, low power little board (3"x2") we designed to use in our > own custom control & data acquisition projects, but the concept turned out > so nice and nifty that we are evaluating the possibility to commercialize it > as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI > with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power > supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a > programmable clock oscillator. Expansion headers are provided for all > important board signals (120, including power pins), with top and bottom > stack mount capability. > > Most MCU and FPGA pins are shared to provide a flexible interfacing > architecture. The FPGA can be used for logic interfacing, data processing, > video output and LCD interface, hardware UARTs and other kind of > communications, etc. > > We would like to introduce this first as a basic kit with all the necessary > tools to get one started (core module, adapter board with serial > transceivers, wiggler-like JTAG programmers, software). The board itself is > a wonderful combo-kit for learning about embedded systems with the ARM > architecture and FPGAs. Most of the software and applications will be > provided as open source and a web site with useful information (application > notes, code and FPGA cores) will be set up. An eCos profile for the board > will be made available too. > > We also have designs for a backplane and auto-configuring add-on modules > with analog and digital IOs, Ethernet interface, IrDA and RF transceivers, > CompactFlash interface, etc. Our idea is to make them available once we can > reinvest and verify enough demand for each kind of device. > > The board can be configured for 1V-3.6V input operation using an efficient > step-up regulator, targeted mainly for battery powered applications. > Another configuration allows not installing the FPGA and using a cheap LDO > regulator for cost-sensitive applications where the FPGA is not necessary > and power efficiency is not of concern. > > You can take a look at some pre-production kit items at > http://www.embedded.cl/gallery/ARMermelator > > In particular, you would help us a lot with your answers and suggestions for > the following: > - How much will you be willing to pay for a kit like this. How much for core > boards in quantities? > - Do you think the FPGA configuration (ie, FPGA present on the board) will > be useful for you? Would you choose this board over other similar products > because of its FPGA functionality? > - Concerning the kit, do you think a base board with integrated programmers, > serial transceivers and prototyping area would be more useful to you than an > adapter board and separated programmers? > - What kind of applications and solutions to your needs do you envision > using a board like this? > - Without knowing further details, your overall impression about this > product. > > Well, thank you very much in advance. Sorry for the long post and sorry if > the content of this post sounded too much like marketing instead of > technical matters -- we are not trying to offend anyone but to help us all. > > Warmest regards. > > > -- > PabloBleyerKocik / > pbleyer /"Simplicity is prerequisite for reliability." > @embedded.cl / -- Edsger Wybe Dijkstra > > > > For the JTAG interface, just add an Multi-ICE 20-pin header. Most designers have Wiggler-like Dongle. Or if you need a better flash programming baudrate or debugging baudrate, use the Chameleon POD with raven_all_speeds configuration. (note: Chameleon POD can operates as Raven, Wiggler, Xilinx_parallel_cable, Altera_ByteBlaster, Lattice_ispDownload, Atmel_AVR_stkxxx, configutation! ALL config for FREE, ALL in ONE Dongle) Laurent www.amontec.comArticle: 66187
Ray, I might use a clk of 280MHz on a -5 Virtex-II and drive the ANDed enable logic at 140MHz - do you think 140Mhz will be ok in general (not pushing it surely?). Thanks for your time, Ken "Ray Andraka" <ray@andraka.com> wrote in message news:402BCD59.EC6C98AA@andraka.com... > ANDing is fine here, although in a high speed design the and gate may cause you > some heartburn when trying to meet timing. The place and route (PAR) tools > don't do a very good job placing second level combinatorial stuff, particularly > gates with multiple loads like you have with a clock enable. Unless you are > really pushing the clock, it should be fine. > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 66188
There are many tricks that can be done to reduce the reliance on
multipliers. One of the big things is to run the clock, not at your sample
rate, but at the largest multiple of the sample rate you can muster. Doing
that, you can take advantage of iterative or bit serial techniques rather
than having to depend on fully parallel arithmetic running at far below its
capability. Even with the chips that have the dedicated multipliers, I use
this philosophy, and more often than not have plenty of multipliers in the
design that don't use the dedicated ones. Distributed arithmetic is just
one of the available tricks, although it is a quite powerful one.
Dave Vanden Bout wrote:
> Thomas Womack <twomack@chiark.greenend.org.uk> wrote in
> news:Hxu*DCYcq@news.chiark.greenend.org.uk:
>
> > In article <c0hjkr$dqg$05$1@news.t-online.com>,
> > Antti Lukats <antti@case2000.com> wrote:
> >>"Austin Lesea" <austin@xilinx.com> wrot
> >
> >>> http://www.xess.com/
> >>>
> >>> Has some very nice inexpensive platforms. These are used for
> >>> universities, colleges, and schools. They are inexpensive enough
> >>> that a student can buy a simple one for about the price of a
> >>> textbook.
> >
> >>you better re-check XESS offerings, as ASFAIK they have dropped
> >>__all__ low cost Xilinx boards.
> >
> > No, according to http://www.xess.com/ho04000.php3 you can still get a
> > XC2S50 or XC2S100 board for $149 or $249 respectively. Or are you
> > claiming they just keep the Web site up to mislead passing travellers?
>
> Yes, we continue to make and sell these boards and will for at least a
> few more years. Last year we halted production of some boards based on
> the older XC9500 CPLDs and XC4000XL FPGAs after the boards passed their
> five-year product lifetime.
>
> >
> > The difference between the XESS and the Parallax board is basically
> > the choice between interesting peripherals and on-board large memories
> > and multipliers; whilst DSP trickery sounds fun, I suspect it would
> > probably be more sensible to get the board with peripherals to start
> > with.
>
> You can always use distributed arithmetic to commit DSP trickery.
> Multipliers are sexy and easier to use right out of the box, but DA is
> still a handy technique to know and understand.
>
> >
> > Tom
>
> --
> || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
> || devb@xess.com PO Box 33091 ||
> || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66189leszekd@itam.zabrze.pl (Leszek) wrote in message news:<9cc55753.0402130142.6096c572@posting.google.com>... > Hi, > I have big problem to move my project (NIOS + some hardware) from > CYCLONE to APEX20K200. During fit, I have masg: > Error: Logic cell ref_16_system:inst|cpu:the_cpu|cpu_pipeline:the_cpu_pipeline|cpu_compact_alu:the_cpu_compact_alu|cpu_adder_logic_lock_region:the_cpu_adder_logic_lock_region|cpu_aluadder:the_cpu_aluadder|cpu_hidden_lcell_4CEF:carryout_reg|regout > requires 5 secondary signals of types non-global clock, non-global > clock enable, non-global clear, non-global synchronous clear, and > non-global synchronous load, but the selected device allows only 4 > signals > > Quartus HELP remarks, that I have to switch Auto Global Clock and > Signals "ON". I did it, but error still keep. What I can do? > Best regards > Leszek > leszekd@itam.zabrze.pl Leszek, Have you re-generated your SOPC Builder system (Nios and all peripherals) for the Apex family? There are several device architecture-specific optimizations that go into the generated VHDL/Verilog code depending on the device family you choose; many Stratix and Cyclone features are not supported on Apex, and merely changnig the device & pin assignments in Quartus won't address these. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 66190
Hi William, Our fastest signals on the board will probably be the 32 bit SDRAM at 100-120 MHz. Our ADC's are operating at 6 MSPS (10 bit samples). USB 2.0 is operating at 30 MHz. Nios will match SDRAM. I need to look at the signals on an analog scope, but the logic analyzer is showing very low jitter operation and the clocks (both input and PLL generated output) look very clean and stable on my digital scope. The boards are operating at 110 MHz for as many days as I care to let them, so I'm fairly confident. If you stay tuned, I'm sure I'll have a fun emissions testing story in a month or two. NTI was great help with our first board 3 years ago. I'm sure they'll be a big help again. We've shipped the products to 40+ countries since then with the biggest problem being that we once had to fax the emissions report to a diligent customs official. Believe you me, my intimate intimate life-force-draining familiarity with production realities and EMC/Safety regulations is why I'm drooling over this new board. Lower parts count and layer count is key. Anyone who understands joint probability can see why. Ken "William Wallace" <msm30@yahoo.com> wrote in message news:7e4865b7.0402130820.482bb3a6@posting.google.com... > "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<102ok9hpug47378@news.supernews.com>... > > Hi Greg, > > > > I was thinking more in terms of SI rather than routing difficulty. > > > > In that case let me share how we handled that on only two signal layers. (We > > did to a split PWR plane, BTW) > > > > It was a challenge with all the pins and signals and we wound up using a > > routing service. The company does nothing but apply a full up SPECTRA > > auto-routing system as a service to others. They were so knowledgeable and > > helpful and the whole transaction was done by email and phone over a few > > days. The price was incredible and now we'll save much more than their fee > > every batch of boards due to the fewer number of layers. > > > Did you make it past emissions testing? At what rate do your signals > change? How is signal integrety? Getting a few boards to work in the > lab is not as tough as getting a design to work in production in > different envirinments while meeting goverment regulations.Article: 66191
Hello Rick! rickman <spamgoeshere4@yahoo.com> wrote in message news:<402CEAA9.9D45F077@yahoo.com>... > Hi Pablo, > > Interesting idea ;) > > Our board is going to have an ARM and an FPGA tightly coupled as well. > But we will have a lot more of course. > > Having gone down this road before, I would recommend that you used > different devices than the two you have picked. I think you will find > it is cheaper to use an ARM with internal Flash and RAM. Of course how > much you need depends on your application and a SOC ARM may not have > enough. But you can sell the board with/without the external Flash and > RAM to make a low cost version possible. We picked up this AT91 for its availability in low volumes, sleep modes (internal PLL that boosts 32kHz to 32MHz) and temperature range. Yes, we considered and are considering other devices as well, like OKI chips (they support external SDRAM, though these are difficult to source in industrial temp) and the LPC22XXs. If this works out perhaps we can offer other family siblings with the same board format and other MCUs. Nice thing is that they are all ARMs so code reusability and compatibility is secured. > The Spartan IIE FPGAs are ok devices, but as someone else pointed out, > they are not very low power. They also have an issue with a power on > current surge that requires 0.5 Amps of current minimum without allowing > the voltage to drop. And all this is during the voltage ramp up > process! We have measured the ramp-up current of SpartanII and IIe FPGAs and it is really not an issue with this kind of boards (of course, the power supply was designed considering the FPGA requirements). We have used Xilinx FPGAs in several designs, so we are confident with the parts and we know their features and limitations. We try very hard to design our boards with reliability in mind and we do lots of tests in field and harsh environments (Chilean mining industry, do I need to say more? ;^) In standby (MCU at 32kHz --not in sleep--, FPGA clocks halted) the unit takes ~60mA @ 3.3V input. When the MCU is running at 32MHz the board typically consumes ~140mA at the same voltage. FPGA consumption varies, but for simple apps it's below 100mA working at full MCU clock. So a typical application always at full MCU clock can run for ~10 hours with two rechargeable NiMH AA batteries. If the board enters sleep mode power consumption can be reduced a lot and will improve stand-alone operation considerably. > Then to top it all off, these parts are not 5 volt tolerant. > There are still a lot of apps that need to interface to 5 volt signals. Yep, we know that there are a lot of 5V systems out there. We analyzed the situation and it really was cheaper to make the core module as simple as possible, and add a couple of 25 cent 5V tolerant transceivers to the add-on modules that use 5V parts (and where there is more space). > We picked the Altera EP1K series of FPGAs. They are fairly low cost and > less power hungry than the Spartan IIE devices. Their power on current > is much lower and the core voltage matches the OKI ARM chip. Have you measured their standby current (before configuration) and static consumption (after configuration and halted clocks)? That would be nice figures to compare. Thanks for your comments. Cheers! PabloBleyerKocik / pbleyer /"Simplicity is prerequisite for reliability." @embedded.cl / -- Edsger Wybe DijkstraArticle: 66192
hi all,
I am new to the LVDS stuff. I am going to implement a LVDS transceiver
on XC3S400. I got the XAPP622 application note (talk about using LVDS on
VirtexII and VirtexII pro) from Xilinx sites. I am wondering if the same
idea could apply to Spartan 3 (I know Spartan 3 runs slow than Virtex)? Is
there any SER-DES core avaliable now for Spartan 3 (I know there is none now
on ISE. Only VirtexII/pro has it)?
Thanks
Chris
Article: 66193prav wrote: > As u told that optoisolator dosen't support high clock frequency . > Are there any other alternatives to replace a opto isolator so that i > can work at higher frequency. Phototransistors are slower than photodiodes, and LEDs are slower than laser diodes, though maybe fast enough. You might try a separate laser diode photodiode pair. -- glenArticle: 66194
Hi all, For example, I want to connect a[1] to b[0], where both a and b are buses in the current file of block editor. How to do that? Can you show documents on how to use block editor? I've been using VHDL for years, graphical design entry of QuartusII looks wired to me. I'm trying to get familar with it. Thanks a lot. ChiArticle: 66195
"Amontec Team, Laurent Gauch" wrote: > > Pablo Bleyer wrote: > > Hello group. > > > > We would like you to share with us your comments and opinions about a > > product we are planning to launch. Your feedback will be very helpful to > > determine the interest in this kind of product, and important to establish > > its development path and features (including, of course, price, so by > > helping us you may be helping yourself ;^) > > > > This is a low cost, low power little board (3"x2") we designed to use in our > > own custom control & data acquisition projects, but the concept turned out > > so nice and nifty that we are evaluating the possibility to commercialize it > > as a line product. It currently has an AT91M42800A MCU from Atmel (ARM7TDMI > > with an external bus), up to 1MB RAM, 1MB to 8MB Flash, integrated power > > supply and a Xilinx SpartanIIe FPGA (XC2S50E or XC2S100E) with a > > programmable clock oscillator. Expansion headers are provided for all > > important board signals (120, including power pins), with top and bottom > > stack mount capability. > > > > Most MCU and FPGA pins are shared to provide a flexible interfacing > > architecture. The FPGA can be used for logic interfacing, data processing, > > video output and LCD interface, hardware UARTs and other kind of > > communications, etc. > > > > We would like to introduce this first as a basic kit with all the necessary > > tools to get one started (core module, adapter board with serial > > transceivers, wiggler-like JTAG programmers, software). The board itself is > > a wonderful combo-kit for learning about embedded systems with the ARM > > architecture and FPGAs. Most of the software and applications will be > > provided as open source and a web site with useful information (application > > notes, code and FPGA cores) will be set up. An eCos profile for the board > > will be made available too. > > > > We also have designs for a backplane and auto-configuring add-on modules > > with analog and digital IOs, Ethernet interface, IrDA and RF transceivers, > > CompactFlash interface, etc. Our idea is to make them available once we can > > reinvest and verify enough demand for each kind of device. > > > > The board can be configured for 1V-3.6V input operation using an efficient > > step-up regulator, targeted mainly for battery powered applications. > > Another configuration allows not installing the FPGA and using a cheap LDO > > regulator for cost-sensitive applications where the FPGA is not necessary > > and power efficiency is not of concern. > > > > You can take a look at some pre-production kit items at > > http://www.embedded.cl/gallery/ARMermelator > > > > In particular, you would help us a lot with your answers and suggestions for > > the following: > > - How much will you be willing to pay for a kit like this. How much for core > > boards in quantities? > > - Do you think the FPGA configuration (ie, FPGA present on the board) will > > be useful for you? Would you choose this board over other similar products > > because of its FPGA functionality? > > - Concerning the kit, do you think a base board with integrated programmers, > > serial transceivers and prototyping area would be more useful to you than an > > adapter board and separated programmers? > > - What kind of applications and solutions to your needs do you envision > > using a board like this? > > - Without knowing further details, your overall impression about this > > product. > > > > Well, thank you very much in advance. Sorry for the long post and sorry if > > the content of this post sounded too much like marketing instead of > > technical matters -- we are not trying to offend anyone but to help us all. > > > > Warmest regards. > > > > > > -- > > PabloBleyerKocik / > > pbleyer /"Simplicity is prerequisite for reliability." > > @embedded.cl / -- Edsger Wybe Dijkstra > > > > > > > > > For the JTAG interface, just add an Multi-ICE 20-pin header. Most > designers have Wiggler-like Dongle. Or if you need a better flash > programming baudrate or debugging baudrate, use the Chameleon POD with > raven_all_speeds configuration. > (note: Chameleon POD can operates as Raven, Wiggler, > Xilinx_parallel_cable, Altera_ByteBlaster, Lattice_ispDownload, > Atmel_AVR_stkxxx, configutation! ALL config for FREE, ALL in ONE Dongle) Or you could just add the Xilinx coolrunner part that they are using on the Chameleon pod and connect directly to the PC! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66196
Pablo Bleyer Kocik wrote: > > Hello Rick! > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<402CEAA9.9D45F077@yahoo.com>... > > Hi Pablo, > > > > Interesting idea ;) > > > > Our board is going to have an ARM and an FPGA tightly coupled as well. > > But we will have a lot more of course. > > > > Having gone down this road before, I would recommend that you used > > different devices than the two you have picked. I think you will find > > it is cheaper to use an ARM with internal Flash and RAM. Of course how > > much you need depends on your application and a SOC ARM may not have > > enough. But you can sell the board with/without the external Flash and > > RAM to make a low cost version possible. > > We picked up this AT91 for its availability in low volumes, sleep > modes (internal PLL that boosts 32kHz to 32MHz) and temperature range. Many of the newer ARMs are available in Industrial temps (OKI only comes in Industrial) and some work with a 32 kHz xtal (the OKI does not). > Yes, we considered and are considering other devices as well, like OKI > chips (they support external SDRAM, though these are difficult to > source in industrial temp) and the LPC22XXs. Unfortunately the LPC22xx are not out yet. Only the versions with no external bus are available. > If this works out perhaps > we can offer other family siblings with the same board format and > other MCUs. Nice thing is that they are all ARMs so code reusability > and compatibility is secured. > > > The Spartan IIE FPGAs are ok devices, but as someone else pointed out, > > they are not very low power. They also have an issue with a power on > > current surge that requires 0.5 Amps of current minimum without allowing > > the voltage to drop. And all this is during the voltage ramp up > > process! > > We have measured the ramp-up current of SpartanII and IIe FPGAs and > it is really not an issue with this kind of boards (of course, the > power supply was designed considering the FPGA requirements). We have > used Xilinx FPGAs in several designs, so we are confident with the > parts and we know their features and limitations. We try very hard to > design our boards with reliability in mind and we do lots of tests in > field and harsh environments (Chilean mining industry, do I need to > say more? ;^) > > In standby (MCU at 32kHz --not in sleep--, FPGA clocks halted) the > unit takes ~60mA @ 3.3V input. When the MCU is running at 32MHz the > board typically consumes ~140mA at the same voltage. FPGA consumption > varies, but for simple apps it's below 100mA working at full MCU > clock. So a typical application always at full MCU clock can run for > ~10 hours with two rechargeable NiMH AA batteries. If the board enters > sleep mode power consumption can be reduced a lot and will improve > stand-alone operation considerably. Wow! That is a lot more than other devices can do, but I guess if it is not an issue with your application it does not matter. The OKI part runs at 60 MHz with less than 60 mA @ 2.5v. Of course the FPGA current will depend on the app inside, but we are designing with <70 mA @ 5v target in mind. Our sleep current is around 5 mA which is almost all from the FPGA. Many of our customers run from batteries and the current is a *major* concern. > > Then to top it all off, these parts are not 5 volt tolerant. > > There are still a lot of apps that need to interface to 5 volt signals. > > Yep, we know that there are a lot of 5V systems out there. We > analyzed the situation and it really was cheaper to make the core > module as simple as possible, and add a couple of 25 cent 5V tolerant > transceivers to the add-on modules that use 5V parts (and where there > is more space). I guess if you have picked the Xilinx parts for other reasons that would be true. But the power and the 5 volt tolerance is the main reason we picked the Altera ACEX part. This just eliminates the extra parts and keep the power supply simple. We are using a couple of switched capacitor converters to keep it as efficient as possible. > > We picked the Altera EP1K series of FPGAs. They are fairly low cost and > > less power hungry than the Spartan IIE devices. Their power on current > > is much lower and the core voltage matches the OKI ARM chip. > > Have you measured their standby current (before configuration) and > static consumption (after configuration and halted clocks)? That would > be nice figures to compare. I have not measured it, but the numbers that Altera has given me are 100 mA startup surge and 5/10 mA static current (commercial/industrial temps). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66197
Marius Vollmer wrote: > Jim Granville <no.spam@designtools.co.nz> writes: > > >> Just to give you a target, to fully challenge the grey matter, :) >>this company offers 10 digits/second ($2K), and 12 digits/second >>models($3K). > > > Could you explain what "10 digits/second" means? I have no idea... > Thanks! It's a figure of merit for reciprocal counters, and you can work backards to an effective timebase, and resolution. Where it is less clear is if a reading of 99.999.999 in 1 second would be counted as the more correct 8 digits/sec, or nudged to 100.000.000 and called 9 digits/sec. Since it's a marketing term, we should assume the latter :) If a reciprocal counter can read 100KHz as 100,000.000Hz in one second, that's a 1 milli Hz LSB, and it infers a 100MHz/10ns timebase. So 8-9 digits/second is 100MHz/10ns technology then 9-10 digits/second is 1GHz/1ns and 11-12 digits is 100GHz/10ps. You can also get a reality check on those inferred timebase values, by the single shot time precision. The Agilent models above spec 500ps and 150ps, and the better TTH model I found specs 25ps. These represent the cutting edge, but with some gymnastics, a FPGA should be able to resolve to the smallest discrete time, which I think was 40ps in Spartan II - anyone know the SDT for Spartan 3? Control of edges to the same LSB should also be possible in theory, but would depend on the HW and SW support to do so. -jgArticle: 66198
Steve wrote: <snip> > I believe there are ways that Xilinx could improve their service to > smaller companies such as significantly increasing the number of > distributors to increase competition. That sounds good comming off the tongue, but could actually be counter-productive to the problem, which is high low volume prices. Much of that business hits MOQs from vendors, and also the 'can't be bothered' threshold in Distis. Adding MORE distis is less efficent, as now their chance of selling stocked devices is less, since the number of customers has not increased. Most would respond by saying - "Sure, we can get that in for you - MOQ is xxx pcs, leadtime is yy weeks" That's why a web/transaction based model would work better. You focus one stock point for the low volume orders, and rationalize it further by stocking only best spec region devices, with maybe a sprinking of 'absolute cheapest' (slowest, worst temp range). Semiconductor Companies are _already_ doing this - just not yet the big FPGA ones. -jgArticle: 66199
sounds reasonable. The PLL in an FPGA might not be as flexible, but it's certainly a more integrated solution. I don't want to give out the details of my design, but I'm using a regular PLL, so you could actually use one on your board. ICS seems to have lots of product, you could look at that too. Some PLLs just require a few IOs or jumpers to configure the frequency. As a side not, my design has an EEPROM version, so you wouldn't need an I2C interface on the FPGA. You could use a 3 pins connector on your board, and the external I2C board can be used to predefine the frequency in the EEPROM. Then the PLL will start at that frequency at next power-up, no IOs are required on the FPGA. About the newsgroup, why don't you use the news server from your ISP? my posts appear almost instantly - at least looks like it on my ISP's server, I'm not sure how the posts get distributed through other servers. Jean
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