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Messages from 67750

Article: 67750
Subject: LogicLock
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 18 Mar 2004 07:06:18 -0800
Links: << >>  << T >>  << A >>
Hi folks,

I am wondering how people are getting around this problem: I LogicLock
a certain entity X. For most compiles, this works great and timing is
met. Other times, the mapper/fitter will autogenerate a combinatorial
node, something like rtl~12695, which it does not create under the
heirarchy of X. This node then gets placed outside my LL region,
usually far enough to make the timing fail horribly, and therefore
negates any gains I made by LogicLocking the entity.

Is there any way around this? I know you can LL paths, but I sure
don't want to LL every possibly path of the entity.

-- Pete

Article: 67751
Subject: Problems with Memory Initialization Files in Modelsim
From: ALuPin@web.de (ALuPin)
Date: 18 Mar 2004 07:55:11 -0800
Links: << >>  << T >>  << A >>
Dear Sir or Madam,

I want to simulate a VHDL design. It includes a RAM structure
which I initialize with an hexadecimal Initializations-File
in the MegaWizardPlugInManager in QuartusII version4.0 .

But when simulating in Modelsim there is the following problem:
When I compile the files "CAM_test.vhd" and the testbench
"tb_CAM_test.vhd", and then start simulation I get the error message
which is shown at 

http://mitglied.lycos.de/vazquez78

What does go wrong?

I would be very thankful if you had the time to have a look at it.


Best regards
Andrés Vázquez
Guntermann & Drunck
System Development

Article: 67752
Subject: Re: pcix-core target memory write
From: Matthias =?iso-8859-1?Q?M=FCller?= <mur@iis.fhg.de>
Date: Thu, 18 Mar 2004 17:38:18 +0100
Links: << >>  << T >>  << A >>
It's my own mistake,
the bits cfg_int(408...413) refer to 64bit access and not to I/O or Memory
space ;-)
Matthias

Matthias Müller schrieb:

> Hello,
> I'm trying to simulate a target memory write transaction with the PCI-X
> core V5_72. Therefore I use the procedures delivered with the example
> files with the core (Write_dword_x). In the cfg_x.vhd file I configured
> the BAR's like following:
>
>   -- BAR0
>   cfg_int(95 downto 64) <= X"ff000000";  -- 16MB
>   cfg_int(408) <= '1' ;                 -- Memory space
>   -- BAR1
>   cfg_int(127 downto 96) <= X"ff000000";  --  16MB
>   cfg_int(409) <= '1' ;                 --  Memory space
>   -- BAR2
>   cfg_int(159 downto 128) <= X"ff000000";  --  16MB
>   cfg_int(410) <= '1' ;                 --  Memory space
>   -- BAR3
>   cfg_int(191 downto 160) <= X"ff000000";  --  16MB
>   cfg_int(411) <= '1' ;                 --  Memory space
>   -- BAR4
>   cfg_int(223 downto 192) <= X"ff000000";  --  16MB
>   cfg_int(412) <= '1' ;                 --  Memory space
>   -- BAR5
>   cfg_int(255 downto 224) <= X"ff000000";  --  16MB
>   cfg_int(413) <= '1' ;                 --  Memory space
>   -- Expansion ROM BAR
>   cfg_int(351 downto 320) <= X"00000000";
>   cfg_int(414) <= '0' ;
>   -- Split Transaction Target
>   cfg_int(415) <= '1' ;
>
> i.e. all BAR's are mapped into memory-space. But I can only write into
> the mapped BAR0-register, when I change the configuration to I/O space,
> i.e. cfg_int(408) <= '0' .
> Does anyone have an explanation for that behaviour?
> Thank you for answers,
> Matthias

--
Matthias Müller
Fraunhofer Institut Integrierte Schaltungen  IIS
-Bildsensorik-
Am Wolfsmantel 33
D-91058 Erlangen
Tel:  +49 (0)9131-776-554
Fax:   +49 (0)9131-776-598
mailto:mur@iis.fhg.de        http://www.iis.fhg.de



Article: 67753
Subject: PCI Development Board
From: "Spike" <me.hates:spam@me.net>
Date: Thu, 18 Mar 2004 17:35:36 GMT
Links: << >>  << T >>  << A >>
I wonder where I can find (and buy) a PCI Development Board with a Xilinx
Spartan FPGA to develop my own PCI card(s). The problem is that I'm a
student and only doing this for fun so I was hoping for a cheap and
easy-to-develop board...

TIA!

//SPike



Article: 67754
Subject: Virtex2P OCM is not cachable?
From: John Black <black@eed.com>
Date: Thu, 18 Mar 2004 10:45:32 -0700
Links: << >>  << T >>  << A >>
Hi,
    V2P OCM can run at same frequency as processor, so it does not need
to be cached. But I was told you actually can not cache it even if you
have some funny idea to try it. Is this true?

Thanks,


Article: 67755
Subject: Re: PCI Development Board
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 18 Mar 2004 19:15:33 GMT
Links: << >>  << T >>  << A >>
On Thu, 18 Mar 2004 17:35:36 GMT, "Spike" <me.hates:spam@me.net> wrote:
>I wonder where I can find (and buy) a PCI Development Board with a Xilinx
>Spartan FPGA to develop my own PCI card(s). The problem is that I'm a
>student and only doing this for fun so I was hoping for a cheap and
>easy-to-develop board...
>
>TIA!
>
>//SPike

You may want to start your search here:

   http://www.fpga-faq.com/FPGA_Boards.shtml



===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 67756
Subject: duration of reset
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Thu, 18 Mar 2004 21:30:15 +0200
Links: << >>  << T >>  << A >>
Here is design:

  DBG_X <= '1' when X else '0';

  REG: process (CLK, RESET)
  begin
   if RESET = '1' then
    X <= True;
   elsif Rising_Edge(Clk) then
   end if;
  end process;

Xilinx implementation tools reported that the maximal delay of design is
0.3ns. Test bench applied 40ns RESET. The expected behafiour of the design:
X goes 1 during reset and remains 1 forever. Functional simulation,
post-Sinplify simulation and timing simulation of the netlist proguced by
WebPack tools showed the expected behaviour. However, the X was stuck at 0
during timing simulation when circuit was synthezied and implemented by
WebPack. Obviously, I blamed stupid XST, as the only difference was the
synthesier used. However, prolonging RESET from showed that X goes high at
100ns after simulation start in timing diagram. The questions:
    1. Why did circuir was resetting faster when Sinplify were used instead
of XST
    2. Why it takes 100 ns for 300Mhz circuit (0.3ns delay) to reset. This
is about 333 clock cycles!!




Article: 67757
Subject: Re: Logiclock TCL flow for Quartus II
From: pguzy@altera.com (Przemek Guzy)
Date: 18 Mar 2004 11:32:54 -0800
Links: << >>  << T >>  << A >>
Hi Spyros,

Let me start by directly addressing the problems you are having:

1) Top level regions are automatically made floating.  This is the
Quartus default.  You are free to lock them down yourself.  There is
only one situation where the default is to keep the region locked: 
You need to import the routing information for the lower level modules
as well.  This can be accomplished like this:

	logiclock_import -no_pins -do_routing

2) Quartus has a feature called Virtual Pins.  Using the assignment
editor you can make Virtual_Pin assignments on any pin which you want
Quartus to treat as an internal connection.  You should however make
sure that the clock pins are NOT made virtual.  Timing analysis will
not be correct if you make your clock pins virtual.  The TCL command
to make these assignments is as follows:

	set_instance_assignment -name VIRTUAL_PIN ON -to some_pin_name

Another suggestion is to make ALL the pins virtual, and make the
clocks Not-Virtual:

	set_instance_assignment -name VIRTUAL_PIN ON -to \|
	set_instance_assignment -name VIRTUAL_PIN OFF -to my_first_clock
	set_instance_assignment -name VIRTUAL_PIN OFF -to some_other_clock

3)  The -routing option in LogicLock export should create an .RCF file
in the atom_netlists subdirectory (or whatever directory you specified
for the .ESF file to be output to).  The .ESF will contain the
placement/region information and the .RCF contains the routing
information.  When doing a LogicLock_import -do_routing, it is
important that the .RCF be placed in the same directory as the .ESF.

4) I don't know why your Quartus is not showing you any help
information.  You should be seeing the following:

tcl> logiclock_import -h
---------------------------------------------------------------------------

Usage: logiclock_import [-h | -help] [-long_help] [-no_pins]
[-no_regions] [-no_nonregion] [-no_create] [-update <region name>]
[-do_routing]

        -h | -help: Short help
        -long_help: Long help with examples and possible return values

        -no_pins: Do not import assignments on pins
        -no_regions: Do not import region information
        -no_nonregion: Do not import non-region information
        -no_create: Do not create regions as required
        -update <region name>: Update region
        -do_routing: Import routing

------------
Tcl Package:
------------

Belongs to ::quartus::logiclock package.

------------
Description:
------------

All Entity Settings File (.esf) in the current project directory, and
all files pointed to by LL_IMPORT_FILE assignments are parsed and
merged into the current top level .esf.

Both LogicLock and non-LogicLock assignments are processed.

The -update option will preserve the region origin and
its place in the LogicLock hierarchy.  All region contents, including
children, will be destroyed.

---------------------------------------------------------------------------

tcl> logiclock_export -h
---------------------------------------------------------------------------

Usage: logiclock_export [-h | -help] [-long_help] -file_name
<filename> [-focus <hpath>] [-routing]

        -h | -help: Short help
        -long_help: Long help with examples and possible return values

        -file_name <filename>: File to export to
        -focus <hpath>: HPath of compilation subtree to be exported
        -routing: Export routing as well

------------
Tcl Package:
------------

Belongs to ::quartus::logiclock package.

------------
Description:
------------

All currently active Entity Settings File (.esf) are
processed.

Any assignment which applies to a node below the -focus
will be exported into the file specified by -file_name.

---------------------------------------------------------------------------



Przemek Guzy
Altera Corp.

Article: 67758
Subject: Re: LogicLock
From: pguzy@altera.com (Przemek Guzy)
Date: 18 Mar 2004 12:00:04 -0800
Links: << >>  << T >>  << A >>
Hi Peter,

I'm not 100% clear on the circumstances of your problem:
Are you using import and export?  Or are you basically creating a
region, and then a new node is created which is NOT part of the entity
that you logiclocked, however it needs to go into the region as well?

If its the second scenario, then I have the following suggestions:

Once you are satified with your HDL and don't need to make any further
changes to it, you should generate a VQM.  This can be done in the
back annotation dialog.  Then you should create a new project, which
uses that VQM as its source.  Turn off all Advanced Fitter
optimizations.  This should minimize the possibility of a new
combinatorial node being created.


Another suggestion is:  

As you said you don't want to have to logiclock every path in your
entity because there are many of them, and this would be tedious. 
However, you can use wildcards in the source and destination
expressions for the path assignment.

source= *
dest = entityX:inst1|*

Would include every node in a path that ends inside your entityX.

 
source =entityX:inst1|*
dest = *
 
Would include every node in a path that starts inside your entityX.


source =entityX:inst1|*
dest = entityX:inst1|*

Would include every node in a path that starts and ends inside
entityX.


Hope this helps.


Przemek Guzy
Altera Corp.

Article: 67759
Subject: Re: PCI Development Board
From: "Spike" <me.hates:spam@me.net>
Date: Thu, 18 Mar 2004 20:05:24 GMT
Links: << >>  << T >>  << A >>
Hi again!

I just looked at this: http://www.xilinx.com/xcell/xl38/xcell38_13.pdf, but
I'm not sure where I can buy it and whether or not it fulfills me needs...
Has any one tried it?

//SPike



Article: 67760
Subject: JDrive Xilinx
From: "Dave Colson" <dscolson@rcn.com>
Date: Thu, 18 Mar 2004 15:17:03 -0500
Links: << >>  << T >>  << A >>
Hello,

I am trying to compile the JDrive softwarebut I am geeting errors due to
missing
function from the code.

Has anyone out there tried to compile this code?

Thanks

David Colson



Article: 67761
Subject: Re: Printing from Altera SOPC Builder
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 18 Mar 2004 13:32:29 -0800
Links: << >>  << T >>  << A >>
Hi David,

When I want to see all the components in an SOPC system and their base
addresses, I use a script that runs this:

find . -name "*.ptf" | xargs grep -E
"MODULE[^_]|((SLAVE|MASTER)[^A-Z])|[^_]Base|Is_En|MASTERED"

This makes a nice printout of every module, its base address(es),
whether it's enabled, and who is mastering it, which is pretty much
all the information the GUI will give you. You can run it from the
Nios SDK shell.

-- Pete


"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<c3c41g$al0$1@news.netpower.no>...
> Is there any way to get a printout from Altera's SOPC Builder, showing the
> components around an embedded processor?  It would be nice to have something
> better than using a screen-capture program.

Article: 67762
Subject: Xilinx ISE 6.2 and Virtex-II
From: "David Roberts" <daverobe@umich.edu>
Date: Thu, 18 Mar 2004 16:37:16 -0500
Links: << >>  << T >>  << A >>
Hi,

Can anyone suggest how to prevent ISE from synthesising one 18x18
multiplication to 3 multiplier blocks?

Thanks,

Dave.



Article: 67763
Subject: Re: Xilinx ISE 6.2 and Virtex-II
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 18 Mar 2004 14:08:53 -0800
Links: << >>  << T >>  << A >>
Dave, are you asking for 2-s complement or for signed magnitude or for
positive integer multiplication?
The hardware is designed for 18 x 18 two-s complement.
Peter Alfke

> From: "David Roberts" <daverobe@umich.edu>
> Organization: University of Michigan Electrical Engineering and Computer
> Science
> Newsgroups: comp.arch.fpga
> Date: Thu, 18 Mar 2004 16:37:16 -0500
> Subject: Xilinx ISE 6.2 and Virtex-II
> 
> Hi,
> 
> Can anyone suggest how to prevent ISE from synthesising one 18x18
> multiplication to 3 multiplier blocks?
> 
> Thanks,
> 
> Dave.
> 
> 


Article: 67764
Subject: Re: LogicLock
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 18 Mar 2004 14:18:35 -0800
Links: << >>  << T >>  << A >>
Hi Przemek,

Yes I am working with scenario two. Thank you for the pointers, I
think they will solve my problems.

-- Pete

pguzy@altera.com (Przemek Guzy) wrote in message news:<6d911b21.0403181200.7040b016@posting.google.com>...
> Hi Peter,
> 
> I'm not 100% clear on the circumstances of your problem:
> Are you using import and export?  Or are you basically creating a
> region, and then a new node is created which is NOT part of the entity
> that you logiclocked, however it needs to go into the region as well?
> 
> If its the second scenario, then I have the following suggestions:
> 
> Once you are satified with your HDL and don't need to make any further
> changes to it, you should generate a VQM.  This can be done in the
> back annotation dialog.  Then you should create a new project, which
> uses that VQM as its source.  Turn off all Advanced Fitter
> optimizations.  This should minimize the possibility of a new
> combinatorial node being created.
> 
> 
> Another suggestion is:  
> 
> As you said you don't want to have to logiclock every path in your
> entity because there are many of them, and this would be tedious. 
> However, you can use wildcards in the source and destination
> expressions for the path assignment.
> 
> source= *
> dest = entityX:inst1|*
> 
> Would include every node in a path that ends inside your entityX.
> 
>  
> source =entityX:inst1|*
> dest = *
>  
> Would include every node in a path that starts inside your entityX.
> 
> 
> source =entityX:inst1|*
> dest = entityX:inst1|*
> 
> Would include every node in a path that starts and ends inside
> entityX.
> 
> 
> Hope this helps.
> 
> 
> Przemek Guzy
> Altera Corp.

Article: 67765
Subject: Re: PCI Development Board
From: "Spike" <me.hates:spam@me.net>
Date: Thu, 18 Mar 2004 22:49:34 GMT
Links: << >>  << T >>  << A >>
I can't say I know enough about FPGA processors to choose a good one, that's
mainly why asked this question. I was hoping that you could give me some
advices...

//SPike

"Philip Freidin" <philip@fliptronics.com> skrev i meddelandet
news:l7tj50pds7c68ui3ok2o6ra4u4t6fcnbsb@4ax.com...
> On Thu, 18 Mar 2004 17:35:36 GMT, "Spike" <me.hates:spam@me.net> wrote:
> >I wonder where I can find (and buy) a PCI Development Board with a Xilinx
> >Spartan FPGA to develop my own PCI card(s). The problem is that I'm a
> >student and only doing this for fun so I was hoping for a cheap and
> >easy-to-develop board...
> >
> >TIA!
> >
> >//SPike
>
> You may want to start your search here:
>
>    http://www.fpga-faq.com/FPGA_Boards.shtml
>
>
>
> ===================
> Philip Freidin
> philip@fliptronics.com
> Host for WWW.FPGA-FAQ.COM



Article: 67766
Subject: Re: Quartus II 4.0 Web Edition Software & Documentation - Available for download
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Thu, 18 Mar 2004 23:30:28 GMT
Links: << >>  << T >>  << A >>
Hi,

> What is the timing for Max II devices? Does it have worst case timing
> or does it have timing at room temp.?

The delay model for Max II (and all other FPGA/CPLD families) reflects
worst-case conditions.  In the case of commercial speed grades, this is 85C
and Vcc - 5% (this is device specific -- check the data sheet).  You may
also do a fast-corner (or minimum timing) analysis reflecting
low-temperature, high-voltage, and fastest silicon -- this is needed when
doing hold-time analysis.

The current timing model for Max II is based on circuit simulations.  This
"preliminary timing model" will be updated periodically until we are happy
with its correlation to silicon, at which point it will be designated as
final.

Regards,

Paul Leventis
Altera Corp.



Article: 67767
Subject: Re: duration of reset
From: Sudhir.Singh@email.com (Sudhir Singh)
Date: 18 Mar 2004 16:22:46 -0800
Links: << >>  << T >>  << A >>
Hi,
Its probably due to reset on configuration (ROC). I think this is
inserted by Xilinx tools when you do a timing simulation. You can
include a ROC component in your VHDL source so that your behavioural
simulation will match your timing.
Include the following component in your architecture:
   component ROC
     generic (WIDTH : Time := 100 ns); 
     port (O : out std_logic); 
   end component; 

WIDTH determines how long the global reset is asserted.

Instantiate it as:
roc_inst: ROC 
       generic map(WIDTH => x ns)         -- x = whatever you want
       port map(O => GLOBAL_RESET);

GLOBAL_RESET is a signal declared in your architecture.

You can now use this signal as your reset and your behavioural and
timing sims should match.

Also use the following library: 
library UNISIM; 
use unisim.vcomponents.all; 

search for ROC at Xilinx website, you'll find lots of info there.

Sudhir




"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:<c3ctac$268guq$1@ID-212430.news.uni-berlin.de>...
> Here is design:
> 
>   DBG_X <= '1' when X else '0';
> 
>   REG: process (CLK, RESET)
>   begin
>    if RESET = '1' then
>     X <= True;
>    elsif Rising_Edge(Clk) then
>    end if;
>   end process;
> 
> Xilinx implementation tools reported that the maximal delay of design is
> 0.3ns. Test bench applied 40ns RESET. The expected behafiour of the design:
> X goes 1 during reset and remains 1 forever. Functional simulation,
> post-Sinplify simulation and timing simulation of the netlist proguced by
> WebPack tools showed the expected behaviour. However, the X was stuck at 0
> during timing simulation when circuit was synthezied and implemented by
> WebPack. Obviously, I blamed stupid XST, as the only difference was the
> synthesier used. However, prolonging RESET from showed that X goes high at
> 100ns after simulation start in timing diagram. The questions:
>     1. Why did circuir was resetting faster when Sinplify were used instead
> of XST
>     2. Why it takes 100 ns for 300Mhz circuit (0.3ns delay) to reset. This
> is about 333 clock cycles!!

Article: 67768
Subject: Re: Spartan III availability
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Fri, 19 Mar 2004 00:44:29 -0000
Links: << >>  << T >>  << A >>

"Brad Eckert" <nospaambrad1@tinyboot.com> wrote in message
news:7d4cc56.0403170952.6724372d@posting.google.com...
> I know this subject has been kicked around a lot here, but here we go
> again.
>
> Where can one get a small quantity of XC3S400s? I already have some on
> indefinite back order at Avnet. Maybe there is another source?


What package do you need?

I can't help, but it's worth specifying.

Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 67769
Subject: Re: Xilinx RAMB16_Sm_Sn timing diagram
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Thu, 18 Mar 2004 18:04:59 -0700
Links: << >>  << T >>  << A >>


Hal Murray wrote:
> Are the numbers in the on-line data sheets updated when the software
> gets updated with a new batch of timing parameters?  Or is that level
> of detail (generally?) lost in the noise of routing delays?
> 

Good question.  In general the data sheet numbers should correlate with 
the software numbers and the data sheets do get updated to reflect the 
current timing numbers however since they are two different mediums with 
different revisioning and different release schedules, it is possible 
for the two to get out of sync now and then.  I generally trust the 
software numbers more than the data sheet numbers (my rule of thumb) as 
the software is updated more often, and that is where timing analysis is 
ultimately done.  If you are ever unsure and want to compare timing 
numbers, just run the speedprint utility in the software:

speedprint -s <speed_grade> <device>

This will dump out all timing numbers with a designation that should be 
the same found in the data sheets.  Of course, make sure you are running 
the latest version of the software with the latest service pack if you 
want the latest timing numbers.

Yet another place to go for these timing numbers that is more dynamic 
than the general data sheets and is almost always up-to-date is the 
interactive data sheets at:

http://www.xilinx.com/applications/web_ds/index_top.htm

Those data sheets are also nice in the fact that each timing parameter 
has a graphic associated with it to visually describe the timing path. 
I find the interactive data sheets very useful and should have probably 
mentioned them before as well.

--  Brian


Article: 67770
Subject: Re: PCI Development Board
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 18 Mar 2004 20:17:12 -0500
Links: << >>  << T >>  << A >>
Spike wrote:
> 
> I can't say I know enough about FPGA processors to choose a good one, that's
> mainly why asked this question. I was hoping that you could give me some
> advices...

That will require that you explain in detail what you want to do with
it.  And be prepared for a lot of advice on what you want to do as well
as how to do it... ;)

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 67771
Subject: Re: Virtex2P OCM is not cachable?
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Thu, 18 Mar 2004 17:56:43 -0800
Links: << >>  << T >>  << A >>
John,

yes, that's correct. OCM cannot be cached. Actually, you need to turn 
off the cacheability of the memory region where you mapped OCM to 
otherwise you get undefined results.

- Peter


John Black wrote:
> Hi,
>     V2P OCM can run at same frequency as processor, so it does not need
> to be cached. But I was told you actually can not cache it even if you
> have some funny idea to try it. Is this true?
> 
> Thanks,
> 


Article: 67772
Subject: Timing Constraint for Xilinx RPM
From: Sudhir.Singh@email.com (Sudhir Singh)
Date: 18 Mar 2004 18:07:56 -0800
Links: << >>  << T >>  << A >>
Hello,
I am just getting into creating Xilinx RPMs as described in their app
note xapp422. I am creating RPM after PAR. This RPM is a 5 bit adder
with registered output. After synthesis I used the Constraints Editor
to specify timing constraints from input nets to output ffs. I used
the Group Elements by Nets (TNM_NET) to create a input group (includes
all input lines A & B buses) and Group elements by instance name to
create (TNM) to create the output ffs group. Slow/Fast Path Exceptions
(FROM TO) is used to specify the delay between this two groups.
The UCF looks like: x = 0 to 4 
  NET "A<x>" TNM_NET = "INGRP";
  NET "B<x>" TNM_NET = "INGRP";
  INST "C_x" TNM = "OPGRP";
  TIMESPEC "TS_DEL" = FROM "INGRP" TO "OPGRP" 0.7 ns;

When I run the Post map timing analyzer I get the following warning:

WARNING:Timing:2666 - Constraint ignored: TS_DEL = MAXDELAY FROM
TIMEGRP
   "INGRP" TO TIMEGRP "OPGRP" 700 pS  ; 
INFO:Timing:2752 - To get complete path coverage, use the
unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

Does anybody know why the constraint is being ignored and what does
the INFO given mean ? Any help will be really appreciated.

Thanks
Sudhir

Article: 67773
Subject: Re: PCI Development Board
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Fri, 19 Mar 2004 02:41:56 GMT
Links: << >>  << T >>  << A >>
Take a look here too
http://www.fpga4fun.com/board_dragon.html

Jean



Article: 67774
Subject: V2p, plb VS opb
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Thu, 18 Mar 2004 23:03:07 -0500 (EST)
Links: << >>  << T >>  << A >>
In the V2pro, Wut is the main difference between the plb and opb?
I know the plb is faster but if I have a limited number of IOs between my
processor and elsewhere is there good reasons to use the opb?

Thanks

Matt



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