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Hi, When I synthesised my state machine coding in Leonardo spectrum I got the warning as Warning: prev_chan not always assigned, storage may be needed. What does it indicate? how can i avoid this warnings? And another warning is Warning, tpac_size should be present in the 'always' condition Can any one give the solution for these 2 warnings? With regards Pradeep. gArticle: 65526
"Antti Lukats" <antti@case2000.com> escribió en el mensaje news:bvih81$6q8$07$1@news.t-online.com... > hm good question, I was going to say its not possible in FS mode, but well > peak bitrate is 12M so the sync serial should be able to pass it through at > full speed. Well I have to admit I havent fully checked out the precise > specs, so maybe its little more. Another thing is sustained average bit > rate, that is always way smaller than max peak bit rate. 1Mbit average bit > rate isnt so bad, but agree 8 would be better. According to the datasheet, when the port is configured as a synchronous FIFO (as the FT245) it uses the same prescaler as the UART configuration, and it is capable of delivering 3Mbaud. (I guess the clock is derived dividing the base oscillator frequency by 2). However, the FT2232C has a new bit-bang interface at port A called MPSSE (Multi-Protocol Synchronous Serial Engine), which is a JTAG/SPI lookalike + GPIOs configuration capable of *5.6Mbits*. The really nice thing about the FT2232C is that it has 2 configurable ports, with enhanced overall features. We just finished designing a programmer/debugger for one of our products (http://www.embedded.cl/gallery/ARMermelator/) that uses one channel of the FT2232 as muxed JTAG for ARM debugging and FPGA configuration, and the second channel for serial communication (eg debug monitor and Flash programming). The FT2232C also makes it easy to power the main board and programmer through the USB's 5 volts, so it is really a 3-in-1 combo. Regards. -- PabloBleyerKocik /"But what... is it good for?" pbleyer / -- 1968 Engineer at IBM's Advanced Computing @embedded.cl / Systems Division, commenting on the microchipArticle: 65527
Hi
Someone must know how to do this. Please please help.
I'm testing a new cpu. The CPU fetches PC from 0x00000000 and SP from
0x00000004 upon reset. How to I link a small crt0.s and any ELF a.out
to test the cpu?
(It's a simple program only testing IO.)
void test_fun(int* x) {
int i;for (i=0;i<0x100000;i++) x[i]=i;
}
void main(){
int* x=0x100000;
while (1) test_fun(x);
}
I only have vauge idea that the crt0.s should look like this: (I could
be wrong.)
.section .text
.long _main
.long 0x2000 // SP
And .text needs to be at 0x00000000 (or at least , the first 8 bytes
need to be PC and SP)
How do I link and assemble files?
Please please help.
(I can write a small program for generating BRAM verilog file myself.
I will simply mapped the file starting 0x00000000.)
Can I use gcc -T ? can someone give a simple example. Please help!
Thanks
Article: 65528pradeep wrote: > Hi, > > When I synthesised my state machine coding in Leonardo spectrum I got > the warning as > > Warning: prev_chan not always assigned, storage may be needed. > > What does it indicate? It will create a latch (and you probably don't want this). Make sure that for every execution path of the always block that prev_chan gets a value. > > how can i avoid this warnings? > > And another warning is > > Warning, tpac_size should be present in the 'always' condition Add tpac_size to the sensitivity list. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 65529
Can anyone recommend a suitable clocking circuitry, crystal or clock component for clocking an fpga at 100MHz. Thanks chazzArticle: 65530
Hi Robert, Antti's golden rule #1 (for MicroBlaze) its 50% of XC2S200 :) I forgot to mention that the most valuable resource is RAM space, when you dont have external RAM (only external ROM) then the internal BRAM space is almost minimal (even after playing with linker scripts). In case of XC2S200 or XC2S300 you only have 4KB read write section. Situation would be much better in Spartan3, with more onchip RAM. I wrote some small post about Selecting FPGA for MicroBlaze (xilinx.openchip.org, choose MicroBlaze forum) For you if you can use external ROM _and_ RAM or external RAM and some option for initial download of programe code into it you are much safer than using only external ROM (and BRAM for read write). Antti PS time to learn is also $$$ I could foreseen that you can easily waste more then 2 weeks setting up linker scripts. (I spent more). "Robert Davis" <rkd0930@comcast.net> wrote in message news:1_%Sb.69750$U%5.389526@attbi_s03... > Thank you Antti. You have given me a lot of useful information. We > currently use the XC2S200, but I am looking at moving to a larger part, > maybe a Spartan 3 when the becomes available. Anyway thanks again. Can any > one else share your experience with Microblaze or NIOS. > > RKD > > "Antti Lukats" <antti@case2000.com> wrote in message > news:bvgvqd$tnc$02$1@news.t-online.com... > > "Robert Davis" <rkd0930@comcast.net> wrote in message > > news:5HSSb.150064$sv6.835853@attbi_s52... > > > Hi All, > > > > > > In my work, I develop high speed counting and measuring systems. Our > > > systems typically use FPGAs for high speed digital logic and a > > > microcontroller for control and calibration. To reduce costs, power and > > > space, I have been looking at the idea of implementing the microcontroller > > > function into the FPGA using either Microblaze or Nios. Does anyoneArticle: 65531
"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhu12b9mtp.fsf@ruckus.brouhaha.com... > antti@case2000.com (Antti Lukats) writes: > > New 3rd generation USB interface chip FT2232C > > has special high speed sync serial modes that allow very fast 1Mbit+ > > downloads of FPGA configuration streams. > > If they went to the trouble of designing a new generation USB-serial > chip with a high-speed sync mode, why didn't they make it capable > of at least 8 Mbps? :-( hm good question, I was going to say its not possible in FS mode, but well peak bitrate is 12M so the sync serial should be able to pass it through at full speed. Well I have to admit I havent fully checked out the precise specs, so maybe its little more. Another thing is sustained average bit rate, that is always way smaller than max peak bit rate. 1Mbit average bit rate isnt so bad, but agree 8 would be better. I guess only non HS USB microcontroller that could configure FGPA with highest bitrate (12Mbit bit peak) is the uPSD from www.st.com it has user programamble PLD inside the usb microcontroller so if that is programmed for continous shift, ah (I an blblabullshit) - any USB micro with SPI interface would get better than 1Mbit peak config download rate. anttiArticle: 65532
On Sun, 01 Feb 2004 10:46:19 -0800, Antti Lukats wrote: > "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message > news:qhu12b9mtp.fsf@ruckus.brouhaha.com... >> antti@case2000.com (Antti Lukats) writes: >> > New 3rd generation USB interface chip FT2232C has special high speed >> > sync serial modes that allow very fast 1Mbit+ downloads of FPGA >> > configuration streams. >> >> If they went to the trouble of designing a new generation USB-serial >> chip with a high-speed sync mode, why didn't they make it capable of at >> least 8 Mbps? :-( > > hm good question, I was going to say its not possible in FS mode, but > well peak bitrate is 12M so the sync serial should be able to pass it > through at full speed. Well I have to admit I havent fully checked out > the precise specs, so maybe its little more. Another thing is sustained > average bit rate, that is always way smaller than max peak bit rate. > 1Mbit average bit rate isnt so bad, but agree 8 would be better. > > I guess only non HS USB microcontroller that could configure FGPA with > highest bitrate (12Mbit bit peak) is the uPSD from www.st.com it has > user programamble PLD inside the usb microcontroller so if that is > programmed for continous shift, ah (I an blblabullshit) - any USB micro > with SPI interface would get better than 1Mbit peak config download > rate. > > antti If you dont mind just one more <$1 CPLD chip the USB245 will allow full speed download (8 MBITS/sec or so) to a FPGA (either in parallel with a tiny state machine to shift data out of the FIFO and into the FPGA or serial with a shift register) The CPLD is also nice if you want the FPGA to be configured without needing the USB interface, as the CPLD can also function as a state machine to generate the read command (03H) to a low cost(<$2.00 for 8 mbit) serial flash chip for on card config storage... Peter WallaceArticle: 65533
Hi
we have compiled synthesis reports for smallest possible MicroBlaze based
SOC system, implementation results for all Xilinx families are available
http://wiki.openchip.org/index.php/MicroBlazeSmallestSystem
XC2V250
Number of MULT18X18s 3 out of 24 12%
Number of RAMB16s 4 out of 24 16%
Number of SLICEs 527 out of 1536 34%
XC2S100,XCV100
Number of BLOCKRAMs 4 out of 10 40%
Number of SLICEs 606 out of 1200 50%
XC2S100E
Number of BLOCKRAMs 4 out of 10 40%
Number of SLICEs 604 out of 1200 50%
XC3S200
Number of Slices 631 out of 2904 21%
Number of MULT18X18s 3 out of 12 25%
Number of RAMB16s 4 out of 12 33%
Number of SLICEMs 244 out of 960 25%
XC2VP2
Number of MULT18X18s 3 out of 12 25%
Number of RAMB16s 4 out of 12 33%
Number of SLICEs 529 out of 1408 37%
All smaller devices fail with slice overmap or RPM constraint too large for
given FPGA array.
The results given are for real minimal system with 8 bit output port only
(on FSL bus!).
my previous rule "MicroBlaze SOC == 50% of XC2S200" is still golden and
valid as adding OPB bus and some small set of peripheral adds 300 to 600
slices and the result is then 50% of XC2S200.
antti
www.openchip.org
Article: 65534Hi all, I tried to summarize the differences in a table. http://www.fpga4fun.com/table.html Sorry about the link, it wasn't easy to duplicate the table in text form for this posting. Things I'd be interesting to hear about: 1. is the info accurate? 2. did I miss important features that differentiate the 2 software? (without getting into details, these are big software...) The table is intended as a beginner's guide to FPGA's software. Thanks for any help/comments. JeanArticle: 65535
bret.wade@xilinx.com (Bret Wade) wrote in message news:<465bd4b1.0401261115.7381c509@posting.google.com>... > t.bartzick@gmx.net (Thomas Bartzick) wrote in message news:<cdd36e13.0401251931.2f3cb1c7@posting.google.com>... Hi Bret, well, thanks for your hints! I could not test them yet, because I have to deal with other problems first, but I will try your solution as soon as possible! Bye, Thomas. > > Hello Thomas, > > When considering TBUF placement issues, it's necessary to understand > the placement limitations of the TBUF sets as a whole. How large a set > can the device handle? How many total sets of a particular size can it > handle? These are limitations that come into play long before the > total number of TBUF sites available becomes a factor. > > Spartan-II devices can not handle multi-row TBUF placement within a > set (Virtex-II can) so the largest possible TBUF set is equal to the > number of columns in the device. The TBUF long lines can be segmented > in groups of four TBUFs, so the number of sites consumed by each set > should be rounded up to a factor of four, then the total number of > possible sets calculated. For example, if the set size is greater than > half the number of TBUFs on a long line, then the number of possible > sets is equal to two times the number of rows (two TBUFs per CLB), > even though TBUF site utilization may only be slightly greater than > 50%. > > If you're unsure of the size of your TBUF sets and the number of sets, > see the following Answer record for a perl script that can be used to > count them: > http://support.xilinx.com/techdocs/2872.htm > > Regarding constraining TBUF placement, it's often enough to LOC a > single TBUF from each set to a site on a particular longline. The rest > of the TBUFs in the set are then implicitly LOC'd to the same long > line. > > One possibility is to allow Map to transform some of the TBUFs to > slice logic by using the -tx switch. > > Regards, > BretArticle: 65536
Jean Nicolle wrote: > Hi all, > > I tried to summarize the differences in a table. > http://www.fpga4fun.com/table.html > > Sorry about the link, it wasn't easy to duplicate the table in text form for > this posting. > > Things I'd be interesting to hear about: > 1. is the info accurate? > 2. did I miss important features that differentiate the 2 software? (without > getting into details, these are big software...) > > The table is intended as a beginner's guide to FPGA's software. > Thanks for any help/comments. > Jean Looks a good idea. You could clarify that this is comparing FREE versions, with maybe the cost of the first step upward from that ?. Perhaps a Device Ceiling (Part num and appx resource ) ? " Free up to XXXX " Installed size (100's of MB ?), and machine minimums in MB RAM and GHz clocks.... If you can be bothered, Links to a small code snippet for VHDL, verilog, ABEL, AHDL could clarify that for beginners - something like a 4 bit U/D/LD counter ? -jgArticle: 65537
Jean Nicolle <j.nicolle@sbcglobal.net> wrote: : Hi all, : I tried to summarize the differences in a table. : http://www.fpga4fun.com/table.html : Sorry about the link, it wasn't easy to duplicate the table in text form for : this posting. : Things I'd be interesting to hear about: : 1. is the info accurate? : 2. did I miss important features that differentiate the 2 software? (without : getting into details, these are big software...) : The table is intended as a beginner's guide to FPGA's software. : Thanks for any help/comments. You can use Iverilog for Xilinx too. And Cver also for both. Cver alos knows about SDF and can be use for post layout simulation. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65538
"Antti Lukats" <antti@case2000.com> wrote in message news:<bvih81$6q8$07$1@news.t-online.com>... > hm good question, I was going to say its not possible in FS mode, but well > peak bitrate is 12M so the sync serial should be able to pass it through at > full speed. Well I have to admit I havent fully checked out the precise > specs, so maybe its little more. Another thing is sustained average bit > rate, that is always way smaller than max peak bit rate. 1Mbit average bit > rate isnt so bad, but agree 8 would be better. According to the datasheet, when the port is configured as a synchronous FIFO (as the FT245) it uses the same prescaler as the UART configuration, and it is capable of delivering 3Mbaud. (I guess the clock is derived dividing the base oscillator frequency by 2). However, the FT2232C has a new bit-bang interface at port A called MPSSE (Multi-Protocol Synchronous Serial Engine), which is a JTAG/SPI lookalike + GPIOs configuration capable of *5.6Mbits*. The really nice thing about the FT2232C is that it has 2 configurable ports, with enhanced overall features. We just finished designing a programmer/debugger for one of our products (http://www.embedded.cl/gallery/ARMermelator/) that uses one channel of the FT2232 as muxed JTAG for ARM debugging and FPGA configuration, and the second channel for serial communication (eg debug monitor and Flash programming). The FT2232C also makes it easy to power the main board and programmer through the USB's 5 volts, so it is really a 3-in-1 combo. Regards. -- PabloBleyerKocik /"But what... is it good for?" pbleyer / -- 1968 Engineer at IBM's Advanced Computing @embedded.cl / Systems Division, commenting on the microchipArticle: 65539
On 1 Feb 2004 14:46:49 -0800, pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote: >"Antti Lukats" <antti@case2000.com> wrote in message news:<bvih81$6q8$07$1@news.t-online.com>... >> hm good question, I was going to say its not possible in FS mode, but well >> peak bitrate is 12M so the sync serial should be able to pass it through at >> full speed. Well I have to admit I havent fully checked out the precise >> specs, so maybe its little more. Another thing is sustained average bit >> rate, that is always way smaller than max peak bit rate. 1Mbit average bit >> rate isnt so bad, but agree 8 would be better. > > According to the datasheet, when the port is configured as a >synchronous FIFO (as the FT245) it uses the same prescaler as the UART >configuration, and it is capable of delivering 3Mbaud. (I guess the >clock is derived dividing the base oscillator frequency by 2). >However, the FT2232C has a new bit-bang interface at port A called >MPSSE (Multi-Protocol Synchronous Serial Engine), which is a JTAG/SPI >lookalike + GPIOs configuration capable of *5.6Mbits*. > > The really nice thing about the FT2232C is that it has 2 configurable >ports, with enhanced overall features. We just finished designing a >programmer/debugger for one of our products >(http://www.embedded.cl/gallery/ARMermelator/) that uses one channel >of the FT2232 as muxed JTAG for ARM debugging and FPGA configuration, >and the second channel for serial communication (eg debug monitor and >Flash programming). The FT2232C also makes it easy to power the main >board and programmer through the USB's 5 volts, so it is really a >3-in-1 combo. > > Regards. > >-- >PabloBleyerKocik /"But what... is it good for?" > pbleyer / -- 1968 Engineer at IBM's Advanced Computing > @embedded.cl / Systems Division, commenting on the microchip ... with the ft245bm i can do transfers at a real 1 mbyte/sec from my win appl .. the 232 version is a bit slower .. KBArticle: 65540
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:SXeTb.20077$ws.2691958@news02.tsnz.net... > > Jean Nicolle wrote: > > Hi all, > > > > I tried to summarize the differences in a table. > > http://www.fpga4fun.com/table.html > > > > Sorry about the link, it wasn't easy to duplicate the table in text form for > > this posting. > > > > Things I'd be interesting to hear about: > > 1. is the info accurate? > > 2. did I miss important features that differentiate the 2 software? (without > > getting into details, these are big software...) > > > > The table is intended as a beginner's guide to FPGA's software. > > Thanks for any help/comments. > > Jean > > Looks a good idea. > > You could clarify that this is comparing FREE versions, with maybe > the cost of the first step upward from that ?. > > Perhaps a Device Ceiling (Part num and appx resource ) ? > " Free up to XXXX " > > Installed size (100's of MB ?), and machine minimums in MB RAM and GHz > clocks.... I assume this is all for the Windows PC only. If so, what version(s) of the OS are supported - I believe Altera still supports Windows 98 and ME while Xilinx requires NT or XP. If not PC only, does it run on Linix? Not everybody, especially those doing things "for fun", have the latest OS versions. I ended up with Quartus because I'm still running 98SE. > If you can be bothered, Links to a small code snippet for VHDL, verilog, > ABEL, AHDL could clarify that for beginners - something like a 4 bit > U/D/LD counter ? > > -jg > > >Article: 65541
> You could clarify that this is comparing FREE versions, with maybe > the cost of the first step upward from that ?. Actually the table is intended for both. > Perhaps a Device Ceiling (Part num and appx resource ) ? > " Free up to XXXX " Looks like the limit is 200KGates for Altera and 400KGates for Xilinx. > Installed size (100's of MB ?), and machine minimums in MB RAM and GHz > clocks.... I'll look to see if there are big differences in the requirements. I could also include the OS'es supported > If you can be bothered, Links to a small code snippet for VHDL, verilog, > ABEL, AHDL could clarify that for beginners - something like a 4 bit > U/D/LD counter ? Sounds like a good idea.Article: 65542
Hi Anyone have "binary file" to "bram" tool (to verilog and constraints files)? ThanksArticle: 65543
> You can use Iverilog for Xilinx too. And Cver also for both. Cver alos knows > about SDF and can be use for post layout simulation. Sounds interesting. Here, right? http://www.pragmatic-c.com/commercial-cver/cver.htm It doesn't seem available for free anymore though, even for non-commercial use.Article: 65544
If all you need is a fixed frequency, crystal oscillators that run at 100MHz are standard components. "chuk" <charlesg77@yahoo.com> wrote in message news:faa526d6.0402010819.3001985b@posting.google.com... > Can anyone recommend a suitable clocking circuitry, crystal or clock > component for clocking an fpga at 100MHz. Thanks > chazzArticle: 65545
I think what you are looking for is a synchorniser. That is a pair of flip-flops where the first flip-flop gets clocked with a certain frequency f_a while the second flip-flop gets clocked with another frequency f_b. Hope this answers your query. regards, nachiket. > > > > Both the LUT and the register are usually part of a CLB's logic. > > Ok thanks for the ideas. For the simple flip-flop, It would need to be > clocked by two clock domains. Is it possible to do this in a Virtex > FPGA?? and for the LUT alternative, i will try it soon. > > JacArticle: 65546
Hi jim,
thank u,
Prev_chan should get a value during a particular state and that value
should be retained till it reaches the same state, so i coded as
prev_chan = chan_num in that state and assigned
prev_chan = prev_chan in all other states, but still i am having the
same problem. can't i code like this.
about the 2nd waring,
always @(tmp_teop)
begin
if (tmp_teop)
begin
if (count < 2'b01)
count_value1 <= tmp_count ;
else
count_value1 <= tmp_count + 17'h00001 ;
end
else
count_value1 <= 17'h00000 ;
end
here even if i include count and tmp_count in the sensitivity list it
will not have any effect unless tmp_teop becomes one, so here i could
avoid unnecessary entry.
Here should i include count and tmp_count in the sensitivity list or
not.
expecting ur guidance
pradeep.g
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<101q93ea27t0hda@corp.supernews.com>...
> pradeep wrote:
> > Hi,
> >
> > When I synthesised my state machine coding in Leonardo spectrum I got
> > the warning as
> >
> > Warning: prev_chan not always assigned, storage may be needed.
> >
> > What does it indicate?
>
> It will create a latch (and you probably don't want this).
> Make sure that for every execution path of the always block
> that prev_chan gets a value.
>
> >
> > how can i avoid this warnings?
> >
> > And another warning is
> >
> > Warning, tpac_size should be present in the 'always' condition
>
> Add tpac_size to the sensitivity list.
>
> Cheers,
> Jim
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 65547Do anyone knows the price of ISE/Quartus? Do they come with the same scheme (1 year licencing)? Once the license expires, does the software stops working, or there is just no more updates? Thanks.Article: 65548
Thanks for the help. Just to get things going, I've (grumblingly) gone for the windows approach. Tech Support at Xilinx basically said this was the only option available until ISE6.2. Lets hope that's soon. For those who want to know, the links from Uwe that might help were: http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html Can do svf playing http://www.asics.ws/tools/ljp.c.gz Writes bit streams directly, but needs a little hacking if you've got a complex JTAG chain. Andy Andrew Greensted wrote: > Hi All, > Has anyone had any success using a Parallel Cable III (PC3) under Linux > to program a Xilinx FPGA using JTAG? > > I know that Impact (from ise 6.1) does not support the cable (Which is > totally absurd). But is there some other software that I can use? > > Unfortunately I'm in a real hurry to get this sorted, so can't wait for > ISE 6.2 which is supposed to support the PC3. > > Many many thanks > Andy >Article: 65549
Hi All, I'm building a JTAG chain demultiplexer so I can control 30 identical JTAG chains from a single point. Can anyone confirm the quiescent (not doing anything) states of the JTAG pins; so I know what to hold the pin levels at when a chain is not being used. I see that TMS, TCK & TDI have internal pull-ups, so would I place a logical 1 on these when they're not in use? TDO is easy enough to sort out as it just goes high Z. Many Thanks Andy -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com
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