Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Fri, 5 Mar 2004 20:07:24 +0000 (UTC), Sander Vesik wrote: >There is a core on opencores.org that is probably suitable for a prng >(its slightly lacking for my taste as a general crypto core) Got a link? I'm not sure what I'm looking for otherwise. >+++ Out of cheese error +++ +++ Redo from start +++ -- MaxArticle: 67126
What I wrote is not completely correct, but there is a work-around: use DONEbar to force a starting value into the latch. Also: the latch is just one LUT with its output used as one of the inputs. No need for 2 LUTs... We might also agree that the start-up after power-up is not so important. All external RAMs (but not the BlockRAMs) come up with unknown content. Anyhow, the SRL16 solution is the most elegant, and therefore the preferred solution. Peter Alfke > From: Ray Andraka <ray@andraka.com> > Organization: Andraka Consulting Group, Inc > Newsgroups: comp.arch.fpga > Date: Fri, 05 Mar 2004 12:49:28 -0500 > Subject: Re: Global reset question? > > I'm not sure what that has to do with my statement, but you are correct, for > VirtexII > the SRL16 has a cascade out that is permanently connected to the last > 'register' in > the SRL16, which in effect is the same as forcing '1111' on the LUT inputs and > looking at the normal output. The cascade output was a new feature for > virtexII. > > What Peter was saying is that you can create a latch out of cross-coupled LUTs > that > will not be affected by global reset (which is true), however he also seemed > to > indicate that you could have that latch come up in a known state on > reconfiguration. > My statement simply says that for a LUT, the configuration sets the > combinatorial > function of the LUT, but does not determine its output value (the output is > determined by the values of the inputs and the ccombinatorial function > assigned to > the LUT). Therefore, the latch created from cross coupled LUTs cannot be > directly > assigned an initial value by configuration. To get it to a known state, one > of the > set/reset inputs must be asserted, which requires something external to the > latch and > explicitly designed in the user logic to accomplish. The SRL16 is different > than a > LUT in that it has internal storage accessible to the user circuit. The SRL16 > can be > viewed as a LUT whose program can be altered by shifting new bits into it. If > held > with the WE='0', it behaves exactly as a LUT, with the output being the value > of the > program bit selected by the inputs. > > PO Laprise wrote: > >> According to the Virtex-II datasheet, if your SRL16 is configured as >> a simple 16-bit shift register, you have direct access to the >> "shift-out" bit of the register, so it would seem you don't need to >> worry about the LUT inputs. I believe this essentially bypasses the LUT >> address mux, although I could be wrong. > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 67127
Hi, Symon. Literally, you are right. Under some circumstances the CLKIN is allowed to stop for a very short time. But the ramifications are so strange (the output keeps going for a while, and then does not start immediately when CLKIN comes back) that I preferred to ignore this limited capability. "Free-running" covers 99.9% of the applications. Peter Alfke > From: symon_brewer@hotmail.com (Symon) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 5 Mar 2004 09:24:33 -0800 > Subject: Re: CASCADING DCM > > Hi Peter, > CLKIN doesn't need to be free running when the DCM is locked, unless > you're using CLKFX or CLKFX180. Here's a quote from the user guide. > <quote> > Input Clock Changes > Changing the period of the input clock beyond the maximum input period > jitter specification requires a manual reset of the DCM. Failure to > reset the DCM produces an unreliable lock signal and output clock. > While the DCM is in the locking process, no input clock edge can be > missing. Once locked, it is possible to temporarily stop the input > clock with little impact to the de-skew circuit, as long as CLKFX or > CLKFX180 is not used. > </quote> > Complicated things, those DCMs! > Cheers, Syms. > > Peter Alfke <peter@xilinx.com> wrote in message > news:<4044CEE5.15179D88@xilinx.com>... >> Basic functionality: >> In its simplest use, the DCM eliminates the clock delay between the >> incoming clock signal and the low-skew global clock distribution. With >> the appropriate feedback to its CLKFB input the DCM inserts the right >> amount of delay so that CLKIN and CLKO signals occur simultaneously >> (within a very small fraction of a nanosecond). Physically, CLKO is >> delayed by exactly one clock period, and this obviously requires a >> free-running, constant-frequency CLKIN. >> I hope this long posting is helpful. >> Peter Alfke, Xilinx ApplicationsArticle: 67128
Stewart Smith wrote:
> Hi
> I have a query for those of you whish to help
> My Problem
> Variable frequency output via a PLD control of a Switched reluctance
> motor.
>
> (Overview)
> The system should be capable of driving a three phase Switched
> Reluctance motor open-loop (no current or position feedback), no-load,
> at a minimum speed of 10 r.p.m.
> The system should include a soft start (frequency ramp) facility and
> the ability to operate in either direction.
> Any suitable power electronic devices may be used.
> The control electronics must be isolated from the power electronics.
> The control electronics should comprise of PLD technology.
>
> So my part is the softstart (thanks guys)
>
> I have only cupl available and a Lattice Gal20v8 device.
> my max frequency output would be 200Hz my minimum requirement is 2 Hz.
> from this I would like to try and make the input frequency to say
> around 400Hz.Then somehow cut this frequency by use of a counter type
> flip-flop array in the Gal, but would also like to take the outputs
> from the said (4 bit) counter to use as my ramp. Thus Giving a
> possible 16 frequency outputs.
> Is it possible to have the counter and then have a state machine use
> the outputs of the counter to generate a ramping frequency effect on 1
> single output pin of the GAL?
> My knowledge of cupl is to say, at best is limited, I have seen
> programs in VHDL (of which my knowledge is even less), which claim to
> be able to achieve this.
> I am a student undertaking an assignment so I am not looking for
> answers (I want to learn) only pointers on how to get there.
>
> Very best regards
> Stewart
Not sure I get the question about a single pin on the 20V8, but
generally speaking
- variable reluctace motors are like coarse stepper motors, so
will need a circular pole pattern driving - best derived from
a single PAL/GAL, using something like CUPLs State engine
Sequence statement
$DEFINE Phase1 'b'00010000
Sequence ReluctanceDrive {
PRESENT Phase2
If Hold NEXT Phase2;
IF !Hold & CW NEXT Phase3;
IF !Hold & !CW NEXT Phase1;
.. repeat here..
}
Missing states in a Sequence statement will jump to 'b'00000000, due to
the D FF's used, so you need to include exit from this state.
Soft start is an issue of 'how soft' ?
For a Wide dynamic range stepper design, we used an Exponent/mantissa
approach in a CPLD. ( you would need multiple 20V8's )
In this, octaves, or 2:1 freq prescaler ranges are done with a simple
tapped divider - a single 20V8 would cover maybe 7 octaves, with a 3 bit
'exponent pointer' or MUX selector to choose which Freq is OP.
Because 1 sudden 2:1 freq jump is likely too much, you apply this
in front of a stage that divides by 32..64, or 64..128, or 128..256 etc
( call this the mantissa PLD ) - resolution is 5 or 6 or 7 bits
Ramp DOWN in freq then occurs by increasing the divider in the Mantissa,
until you get to MAX, and then next step is add-in /2, and jump back to
MIN divide. Each Octave is then covered 32 or 64 or 128 steps etc
Not sure how you want to set the soft start, but one simple scheme
would be to have a QuadEncoder driving a Up/Dn SPEED counter, that
indexes into the 2 plds above.
All up, the full Motor Control system would have ~4 SPLDs
[ 22V10's might be better ask your tutor about 22V10's ? ]
ATF22V10CQZ is a good candidate.
- Motor Field State engine
- Octave Divider, eg 7 octaves, so has 3 index bits
- Mantissa Divider, eg 32..64, so has 5 index bits
- UpDn speed counter, with 3+5 bits output, and SIGN/DIRN, maybe with a
RESET to Zero 'panic button' :)
- optional LED Decoders to show what speed you have dialed up to.
-jg
Article: 67129Max <mtj2@btopenworld.com> wrote: > On Fri, 5 Mar 2004 20:07:24 +0000 (UTC), Sander Vesik wrote: > > >There is a core on opencores.org that is probably suitable for a prng > >(its slightly lacking for my taste as a general crypto core) > > Got a link? I'm not sure what I'm looking for otherwise. > www.opencores.org -- Sander +++ Out of cheese error +++Article: 67130
Well, had to ask. But 14 days? This should have taken about 1 hour max, assuming you tried ECP and bi-directional, and didn't know how to get into your bios, and had to search around for the book... eastwood132@yahoo.com (Ted Lechman) wrote in message news:<b89924f9.0403050538.299a91ae@posting.google.com>... > Yes, of course - I spent the entire 14 day return period doing nothing else. > > msm30@yahoo.com (William Wallace) wrote in message news:<7e4865b7.0403031802.49740a9b@posting.google.com>... > > Did you verify that you had your port settings correct in the > > laptop's BIOS? > > > > > > eastwood132@yahoo.com (Ted Lechman) wrote in message news:<b89924f9.0403021447.48ec865d@posting.google.com>... > > > I've discovered incompatability between the ModelSim dongle and > > > certain notebook computer's printer ports: They are > > > > > > 1. Toshiba Satellite S150s (I would suspect all Satellites). I've > > > experienced this personally. I had to returnthis notebook and get a > > > CompaqPresario 2500 in its place to make sure the dongle works. > > > 2. Sony notebooks ( my local distributor has had this problem). > > > > > > The rumor is that its a voltage incompatabilty issue, but I'm not > > > sure. > > > > > > Ted Lechman > > > Utica, NYArticle: 67131
I have used devices with JTAG interfaces that did not work correctly if you did not take care of TRST. This is common. It may or may not apply to your problem, but if TRST is used on an IC, you do want to take care of it. erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c27lga$jni$1@sunnews.cern.ch>... > William Wallace wrote: > > TRST is often used. > > Could you explain this a bit more detailled? > > TRST is an optional JTAG signal and in JTAG applications you can easily > get the same effect using the other signals. Or am I mistaken? > > Janos Ero > CERN Div. EPArticle: 67132
Well, if it makes economic sense to hire a consultant, let me know, the firm I work at can help. "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<oNk0c.18489$jR7.10085@newssvr29.news.prodigy.com>... > William Wallace wrote: > > > He didn't say how many frequencies he was going to use, or what kind > > of FPGA, or how many bits in the samples. > > A few frequencies. Not enough data yet. > Samples can be up to 16 bits wide x 3 (RGB image processing). > Virtex 2V1000. > > Had to put the project on the shelf for a few days. I'm very tempted to run > the whole thing at the highest possible frequency (in the context of what > needs to be done, not the highest attainable by the FPGA) and use clock > enables. It would seem to me that this is the easiest way to stay out of > trouble. I like that.Article: 67133
THE IMPORTANCE OF PROVIDING A RESET THAT LEAVES THE RESET
SYNCHRONOUSLY EVEN IF IT DRIVES THE ASYNCHRONOUS RESET:
Consider a simple one hot state machine that cycles through 3 states:
S001: 001
S010: 010
S100: 100
S001: 001
S010: 010
S011: 100
This is a simple, trivial state machine, but it will serve the purpose
of highlighting why you should leave reset synchronously.
What happens if the asynchronous reset comes at a time and has delays
such that two of the flops to see clock N as the first clock, but the
third flop to see clock N+1 as the first clock. Your state machine
might end up running like so:
S001: 001
Invalid: 011
Invalid: 110
Invalid: 101
Invalid: 011
Invalid: 110
Invalid: 101
Two flip flops are hot. This is bad.
You could get around this by treating your one hot as a binary encoded
state machine, and treating all other states other than {001, 010,
100} as dead end states that must transition to one of the valid
states, but in doing so, you loose the advantages of a one hot state
machine (specifically, the combinatorial logic required to protect
against these dead end states may make it harder to meet timing, and
may chew up more resources than you want).
A different approach would be to process your reset into the FPGA such
that the entire design is reset asynchronously, but the majority of
the design leaves reset synchronously (though under control of the
asynchronous reset input)
E.g., (and not syntax checked):
process(clk,iReset)
begin
if(iReset='1') then
ResetSR="00";
elsif(clk'event and clk = '1') then
ResetSR(0) <= '1';
ResetSR(1) <= ResetSR(0);
end if;
end process;
RESET <= ResetSR(1);
simplesm : process(clk,RESET)
begin
if(Reset = '1') then -- NOTE, this is not iReset
state <= S001;
elsif(clk'event and clk='1') then
case state is =>
when S001 =>
state <= S010;
when S010 =>
state <= S100;
when S100 =>
state <= S001;
end case
end if
end process simplesm;
Here, if the path delays on the internal signal RESET are less than
the clock period, all three registers used to implement the state
machine will see the same first clock after reset.
Any thoughts? (Probably pretty obvious to some who have actually
encountered problems due to different registers in a design seeing
different first clocks, but it wasn't so obvious to me until somebody
recently recommended this practice to me, since I never had a problem
that I traced back to this type of issue.)
But for this to work, static timing analysis tools should check path
delays on the internal RESET signal to make sure it makes it to all
the registers asynchronous resets before the clock after it was
generated.
Do static timing analysis tools do this?
Article: 67134inaganti_suni@yahoo.com (sunil) wrote in message news:<9f28d282.0403040929.1624a64f@posting.google.com>... > hi all, > i am getting this error while synthesizing on XILINX4.1e. > the individual units are synthesizing. > > FATAL_ERROR:HDLParsers:vhptype.c:270:$Id: vhptype.c,v 1.1 2001/03/22 > 18:59:29 kingsley Exp $:200 - INTERNAL ERROR... while parsing > G:/ACSUNIT/totalunit.vhd line 337. Contact your hot line. Process will > terminate. To resolve this error, please consult the Answers Database > and other online resources at http://support.xilinx.com > EXEWRAP detected a return code of '1' from program > 'F:/Xilinx/bin/nt/xst.exe' > > Done: failed with exit code: 0001. > > thank u all. It might be helpful if you posted line 337 of :/ACSUNIT/totalunit.vhd line 337, as well as all other lines that shed light on this line of code. Alternatively, you could open a case at support.xilinx.com. Or you could upgrade your project navigator to something in the 5s or 6s.Article: 67135
The initiator DMA is not too bad. Here's how I do it: One register is loaded with the memory address. The other is loaded with the size. Every clock cycle we have a nonzero size count and are not currently in a DMA transfer/request, the DMA transfer requests. The size register is decremented and the address register is incremented as the data comes/goes. If the transfer finishes early, we still have a nonzero size so it just starts up again. "Matthias Müller" <spam*mur@iis.fhg.de> wrote in message news:404736F1.8D033BA@iis.fhg.de... > Hello, > I want to perform a DMA via the Xilinx PCI-X core (64bit/133MHz) to the > system's DRAM. Therefore I want to act as a busmaster and transfer > 4K-byte blocks (maximum bytecount) in initiator-burst-transfers. The > problem is that the DMA can be aborted at any time, so I have to > calculate the appropriate new byte-address, request the bus again and so > on. This can be a rather complicated design, so my question is: is there > any way to simplify a DMA like descriped above or are there any > interface-modules for the Xilinx PCI-X core which work as DMA-controller > for the core. > Futhermore I'm looking for a simulation-model for the PCI-X-bus-side. > Thank you for help, > Matthias >Article: 67136
Greg Steinke wrote: > Another thing to check would be the TCK on the devices in the chain. > If one of the devices is getting double-clocked then this would foul > up the data passing through the JTAG chain. The tricky part is that a > double-clock on any device could cause a problem, not just on the > EPC8. Thanks for the info. Actually we use a TCK fanout circuit, a 74LVTH16244. The 23 members of the JTAG chain, all Altera chips, are ordered in 4 groups, every group gets its own TCK and TMS line. The lines are source terminated by a 22ohm serial resistor. The signals on chip pins are clean. Despite of this we often have problems with the programming. The EPC8 chips seem to draw short, but extremely high current spikes when programmed (apr. 7-8 Amps), and even higher when doing verification (10-11 Amps). There are EPC8s where we cannot do verification at all - but the chip gets programmed correctly. We cannot exactly measure this current as our PS output has 12 power strips in parallel and the Board gets current from the Backplane on many connector pins. The current values above can only be seen on the display of the PS unit front panel. Putting several hundred uF capacitor on the EPC8 power pins can help, but not always. Is this correct? Thanks, Janos Ero CERN Div. EPArticle: 67137
rickman wrote: > Why not put a TRST pullup on the board to be safe? 10K should do the > job and not get in the way. You are right. Just when making layout for a thousand-pin BGA you want to avoid any unnecessary pin to connect. :-)))Article: 67138
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<6G92c.34022$ws.3420776@news02.tsnz.net>...
> Stewart Smith wrote:
> > Hi
> > I have a query for those of you whish to help
> > My Problem
> > Variable frequency output via a PLD control of a Switched reluctance
> > motor.
> >
> > (Overview)
> > The system should be capable of driving a three phase Switched
> > Reluctance motor open-loop (no current or position feedback), no-load,
> > at a minimum speed of 10 r.p.m.
> > The system should include a soft start (frequency ramp) facility and
> > the ability to operate in either direction.
> > Any suitable power electronic devices may be used.
> > The control electronics must be isolated from the power electronics.
> > The control electronics should comprise of PLD technology.
> >
> > So my part is the softstart (thanks guys)
> >
> > I have only cupl available and a Lattice Gal20v8 device.
> > my max frequency output would be 200Hz my minimum requirement is 2 Hz.
> > from this I would like to try and make the input frequency to say
> > around 400Hz.Then somehow cut this frequency by use of a counter type
> > flip-flop array in the Gal, but would also like to take the outputs
> > from the said (4 bit) counter to use as my ramp. Thus Giving a
> > possible 16 frequency outputs.
> > Is it possible to have the counter and then have a state machine use
> > the outputs of the counter to generate a ramping frequency effect on 1
> > single output pin of the GAL?
> > My knowledge of cupl is to say, at best is limited, I have seen
> > programs in VHDL (of which my knowledge is even less), which claim to
> > be able to achieve this.
> > I am a student undertaking an assignment so I am not looking for
> > answers (I want to learn) only pointers on how to get there.
> >
> > Very best regards
> > Stewart
>
> Not sure I get the question about a single pin on the 20V8, but
> generally speaking
> - variable reluctace motors are like coarse stepper motors, so
> will need a circular pole pattern driving - best derived from
> a single PAL/GAL, using something like CUPLs State engine
> Sequence statement
>
> $DEFINE Phase1 'b'00010000
>
> Sequence ReluctanceDrive {
> PRESENT Phase2
> If Hold NEXT Phase2;
> IF !Hold & CW NEXT Phase3;
> IF !Hold & !CW NEXT Phase1;
> .. repeat here..
> }
> Missing states in a Sequence statement will jump to 'b'00000000, due to
> the D FF's used, so you need to include exit from this state.
>
> Soft start is an issue of 'how soft' ?
>
> For a Wide dynamic range stepper design, we used an Exponent/mantissa
> approach in a CPLD. ( you would need multiple 20V8's )
>
> In this, octaves, or 2:1 freq prescaler ranges are done with a simple
> tapped divider - a single 20V8 would cover maybe 7 octaves, with a 3 bit
> 'exponent pointer' or MUX selector to choose which Freq is OP.
>
> Because 1 sudden 2:1 freq jump is likely too much, you apply this
> in front of a stage that divides by 32..64, or 64..128, or 128..256 etc
> ( call this the mantissa PLD ) - resolution is 5 or 6 or 7 bits
>
> Ramp DOWN in freq then occurs by increasing the divider in the Mantissa,
> until you get to MAX, and then next step is add-in /2, and jump back to
> MIN divide. Each Octave is then covered 32 or 64 or 128 steps etc
>
> Not sure how you want to set the soft start, but one simple scheme
> would be to have a QuadEncoder driving a Up/Dn SPEED counter, that
> indexes into the 2 plds above.
>
> All up, the full Motor Control system would have ~4 SPLDs
> [ 22V10's might be better ask your tutor about 22V10's ? ]
> ATF22V10CQZ is a good candidate.
>
> - Motor Field State engine
> - Octave Divider, eg 7 octaves, so has 3 index bits
> - Mantissa Divider, eg 32..64, so has 5 index bits
> - UpDn speed counter, with 3+5 bits output, and SIGN/DIRN, maybe with a
> RESET to Zero 'panic button' :)
> - optional LED Decoders to show what speed you have dialed up to.
>
> -jg
Thanks for your response and I'm sorry about my vagueness about
certain points, what I meant by a single pin output, is that this
single output from my frequency ramp CPLD would be the clock source
for another CPLD which would contain the three pole switching sequence
(this bit I've managed to do), it is this sequencing frequency that I
have hopes of using to control the motor speed.
This assignment has been previously undertaken successfully, with
using only two of the 20v8 devices and this is what where actively
encouraged to limiting ourselves to.
I suspect the softstart to be much cruder than the type you have
suggested (which is probably the correct method).
In your reply you mention a "tapped divider, exponent pointer, or Mux
selector" could you possibly suggest an example of how these are coded
in cupl.
Below is an extract of coding for the switching (which is just a
re-worked up down counter)
/** Inputs **/
Pin 1 = clk ;
Pin 2 = FWD ;
Pin 3 = REVER ;
Pin 4 = STOP ;
pin 11 = !OE;
/** Outputs **/
Pin [16..18] = [Q2..0]; /** **/
/** Declarations and Intermediate Variables **/
field srcont = [Q2..0];
$Define S0 'b'000
$Define S1 'b'001
$Define S2 'b'010
$Define S3 'b'011
$Define S4 'b'100
$Define S5 'b'101
$Define S6 'b'110
field mode = [FWD,REVER,STOP]; /* declare mode control field
*/
up = mode:4; /* define srcont up mode */
down = mode:2; /* define srcont down mode */
clear = mode:[3,5,7]; /* define srcont clear mode */
/** Logic Equations **/
Sequenced srcont { /* running srcont */
present S0
if up next S1;
if down next S1;
if clear next S0;
present S1
if up next S5;
if down next S3;
if clear next S0;
present S5
if up next S4;
if down next S2;
if clear next S0;
present S4
if up next S6;
if down next S6;
if clear next S0;
present S6
if up next S2;
if down next S4;
if clear next S0;
present S2
if up next S3;
if down next S5;
if clear next S0;
present S3
if up next S1;
if down next S1;
if clear next S0;
Thank you
Stewart
Article: 67139Stewart Smith wrote: > Thanks for your response and I'm sorry about my vagueness about > certain points, what I meant by a single pin output, is that this > single output from my frequency ramp CPLD would be the clock source > for another CPLD which would contain the three pole switching sequence > (this bit I've managed to do), it is this sequencing frequency that I > have hopes of using to control the motor speed. > > This assignment has been previously undertaken successfully, with > using only two of the 20v8 devices and this is what where actively > encouraged to limiting ourselves to. > > I suspect the softstart to be much cruder than the type you have > suggested (which is probably the correct method). > > In your reply you mention a "tapped divider, exponent pointer, or Mux > selector" could you possibly suggest an example of how these are coded > in cupl. Somewhere you have to generate the clock to determine the Step freq. If that is external, from a SigGenerator or similar, then you need a way to proportionally gate that. Look into Rate Multipliers : These have Fo = N/Base output, so a 4 bit binary one can start at 1/16 fi, and step thru 2/16,3/16 up to 16/16 Fi, in linear frequency steps Rate Multiplier info is not easy to find, so here is one ref : http://focus.ti.com/docs/prod/folders/print/sn7497.html Then the 4 Bit number that feeds this Rate Multiplier, could derive from a saturating counter (one that counts to a MAX, and then stops until reversed. ) The step rate of the RateNumber determines the soft-start, so you could clock that from the Phase signals, or a divided version of the phase signal for slower still Start-rate. ( so far, you have used only 3 bits of the PhaseGen PLD) - this will give a revolution proportional slow start, which may be too conservative at very low step rates, but it is simple, and you can fit both the 4 bit rate Multiplier Ctr, 1 rate MergeCell, the 4 bit saturating Ctr, Delayed Dirn BIT, and your 3 bit phase engine into 2 PLDs. The Delayed Dirn bit is some fine-tuning, that would only allow DIRN to be changed ONLY at the LOWEST possible rate value. -jgArticle: 67140
On 5 Mar 2004 22:15:43 -0800, msm30@yahoo.com (William Wallace) wrote: >THE IMPORTANCE OF PROVIDING A RESET THAT LEAVES THE RESET >SYNCHRONOUSLY EVEN IF IT DRIVES THE ASYNCHRONOUS RESET: > ... >But for this to work, static timing analysis tools should check path >delays on the internal RESET signal to make sure it makes it to all >the registers asynchronous resets before the clock after it was >generated. > >Do static timing analysis tools do this? Yes; for DFF cells there is a parameter called Reset Recovery Time on the reset input which is similar to setup parameter for D input. If you release the reset synchronously to the clock input, STA tools can time the reset path too.Article: 67141
You can see wave form of simulation results of testing module now!Article: 67142
Hi, there: Can Xilinx XST synthesize encrypted verilog source codes? For example the following style... What is the software to do this encryption? Best Regards, KelvinArticle: 67143
Does Model-Sim XE support this directive also? I got a big list of compilation error... Kelvin "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:c2ced9$bvr$1@reader01.singnet.com.sg... > Hi, there: > > Can Xilinx XST synthesize encrypted verilog source codes? For example the > following style... > What is the software to do this encryption? > > Best Regards, > Kelvin > > >Article: 67144
On Sat, 6 Mar 2004 03:50:49 +0000 (UTC), Sander Vesik wrote: >www.opencores.org Yes, but which core are you referring to? -- MaxArticle: 67145
Hi Brian Thanks for your answer, directed at my problem. I should have said that at the end of all the warnings I received, was the following. Warning: No Global(GSR) net could be used in the design because there is not a unique net that sets or resets all the sequential cells. So I am assuming that the STARTUP block has been included, even though I didnt specifically stipulate that it should. I am also assuming that my synthesis tool is trying to assign a signal assigned to a pin as a stimulus for this global net. As soon as one register is not cleared by this signal the GSR net is no more. I ran a simulation to see what I would get. The simulation was done with the scenario described, i.e. one register is not cleared by the input "clear" pin and synthesis gives the warnings described. I get one BUS signal at xxx? and another at 000?. Even though I am setting my external clear signal high. This is new and not what I normally get from this simulation. I normally get things cleared when the clear signal is high. From this I assume that my efforts to clear a section of the FPGA leaving one register un cleared is not working. Now this is really confusing me. I have a pin assigned to have an external signal(with the name clear). This signal is sent to all FFs and counters in the FPGA in my verilog code. Now because I have not complied with the requirements for a GSR signal, I effectivly have no clear? Many thanks for your input. Denis __________________________ From Concept to Production http://www.centronsolutions.com Brian Philofsky <brian.philofsky@no_xilinx_spam.com> wrote in message news:<4047ACA2.4010808@no_xilinx_spam.com>... > Denis, > > There are a few solutions to this problem. First the SRL was mentioned > but since you are targeting a Spartan-XL, you do not have an SRL but you > do have LUT-RAM and it can serve this same purpose. You can use a > RAM16X1S with all address lines tied to a known value (zeroes) and the > write enable tied high. You would have more-or-less a FF not tied to > global set/reset (GSR) at all. Another possibility to fix this problem > is to use a regular FF and have the initial state specied to a one. It > sounded like the problem was this the register going to zero and the > default state can be made to a one if that solves the issue. In that > case, and time GSR is used that register would be set to a one not a > zero. Both of the above suggestions are assuming that you are using the > STARTUP block to get access to the dedicated GSR net which will set or > reset depending on the defined init state of the FF at configuration. > If you have not instantiated a STARTUP block in your code, then you will > be using local resets using standard routing and in that case anything > that you do not connect to the reset will not be reset after power up. > This will consume routing resources but the XCS05XL is a small device > and as long as timing can be met, should be OK. > > The warning message below looks to be issued by the synthesis tool and I > am not exactly sure why it is being issued. I think it is trying to > warn you that you may have made a mistake in accidentally not connecting > one register to the reset but it sounds like you want this done. My > suggestion would be to do a timing simulation and see if it works as you > want it to. If so, then that can be ignored. If it does not act > properly, then you can figure out why and maybe that can address this > warning as well. > > Hope this helps, > > -- Brian > > > Denis Gleeson wrote: > > > Hello all > > > > I guess I had better stop saying that I'm new to this FPGA stuff > > as I've being saying that for two years now. Anyway Im certainly a > > novice > > who is improving with time and the gratefully accepted input of > > this newsgroups members. > > > > At this stage I am reasonably happy with my design in Verilog > > targeting > > a xilinx xcs05xl. > > > > However, I find that there is one latch that I dont want to reset when > > I am reseting everything else in the FPGA. This is because it holds > > configuration > > information for the FPGA and the external circuitry. If I dont set > > this latch > > to zero when my global clear line is low I get about 55 warnings at my > > synthesis step. > > > > I get: > > DPM : Warning NET ACB/ACB_NOT_TRIGGER_FOUND does not set/reset > > /Int_read_trigger_address/Q_reg (FPGA -GSRMAP-13) > > > > about 55 times. > > > > Im not sure how the nets mentioned above relate to the latch that is > > not being cleared. > > > > > > What is the effect of my action. Are there lots of FFs not being reset > > by my global clear signal? > > How do I get rid of all these warnings? > > Can I decide not to clear one latch and get all others to clear > > without all the warnings? > > > > > > Thanks in advance. > > > > Denis > > ___________________ > > http://www.CentronSolutions.com > > From concept to productionArticle: 67146
Dear peter, Thank you for your reply. I have some questions: > First: > check that both boards really operate with the same input signals. Swap the > boards and check where the failure moves. The enviroment, input signals, temperature are exactly the same for both boards. > Next: > Vary ambient temperature and also (separately) Vcc, and note their impact on > the behavior. Power on these boards comes from a good DC/DC converter from DATEL. There is no power variation on the boards. > It could also be caused by hanging undriven pins that very slowly drift High... I have some undriven and UNUSED pin on the fpga (XC2S150E). No signal handled by these pins. Is it important? Should I connect these pins to ground or Vcc ? regards. M. NaderiArticle: 67147
"Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0403061113.7404aca5@posting.google.com... > Dear peter, > Thank you for your reply. I have some questions: > > First: > > check that both boards really operate with the same input signals. Swap the > > boards and check where the failure moves. > The enviroment, input signals, temperature are exactly the same for > both boards. > It sure sounds like a temperature problem. Variations in process could cause one part to fail at one temperature and the other to operate fine. I once had a customer that reported that my design would work for several minutes and then start to fail. He blew some coolant on it and it started working again. He had to end up beefing up the fan system. Xilinx parts tend to use a little more power than expected. I also had a customer with a similar symptom and the cause was insufficient decoupling capacitance, so you might check that as well. Those caps seem like they're not doing much, but they are important and you should have one for eac VCC pin. -KevinArticle: 67148
Masoud Naderi wrote: > > Dear peter, > Thank you for your reply. I have some questions: > > First: > > check that both boards really operate with the same input signals. Swap the > > boards and check where the failure moves. > The enviroment, input signals, temperature are exactly the same for > both boards. > > > Next: > > Vary ambient temperature and also (separately) Vcc, and note their impact on > > the behavior. > > Power on these boards comes from a good DC/DC converter from DATEL. > There is no power variation on the boards. > > > It could also be caused by hanging undriven pins that very slowly drift High... > > I have some undriven and UNUSED pin on the fpga (XC2S150E). No signal > handled by these pins. Is it important? Should I connect these pins to > ground or Vcc ? A floating input that is not used is an unlikely source or problems. But you can make sure by configuring your device to drive these pins to a given value, even if it is just a pullup. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67149
Hi, I am pretty new at this but would like to know if anyone can recommend a good guide to getting up and running using FPGA Editor (ISE 5.2i) Have searched Web but not much found for the basics. Thanks, Durward
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z