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Hi Phil, Good thinking ;o) Thanks a lot, I haven't tried it yet but sounds good to me. I'll try it tomorrow in the office with Precision and XST and let you know. Regards, -- I.Ulises Hernandez 'postmaster' at posting domain should work for email "Phil Hays" <Spampostmaster@comcast.net> wrote in message news:cr2me0pm20cbkok7htbv1mifhifegbt95k@4ax.com... > "I. Ulises Hernandez" <delete@e-vhdl.com> wrote: > > >Your English translates brilliantly to Spanish :O) > > Good, as my Spanish is beyond awful ;-) > > > >I have built successfully your 'diffddr' module with Leonardo and Precision, > >still a problem though... > > Please try the following code. I increased the generic width to 8, as > that is what you are targeting. I added another layer of FFs to make > sure there was no ambiguity as to where to force the FF into, and > verified the map was forcing FFs into IOBs (map report file will have > "-pr b" on the command line). I also split the clocked process into > rising and falling edge sections as I have seen problems with this in > the past. XST handles the following code correctly. > > > -- > Phil Hays > Phil-hays at posting domain should work for email > > ---------------------------- Cut Here ----------------------------- > > library ieee; > use ieee.numeric_std.all; > use ieee.std_logic_1164.all; > library unisim; > use unisim.vcomponents.all; > entity idiffddr_g is > generic > ( > data_width : integer:=8 > ); > port ( > mainclk_p : in std_logic; > mainclk_n : in std_logic; > rst : in std_logic; > diff_p : in std_logic_vector(data_width-1 downto 0); > diff_n : in std_logic_vector(data_width-1 downto 0); > diffout : out std_logic_vector(data_width-1 downto 0); > diffout_n : out std_logic_vector(data_width-1 downto 0) > ); > end entity; > > architecture rtl of idiffddr_g is > signal mainclk : std_logic; > signal clk0 : std_logic; > signal clk : std_logic; > signal clk_n : std_logic; > signal diff : std_logic_vector(data_width-1 downto 0); > signal difft : std_logic_vector(data_width-1 downto 0); > signal difft_n : std_logic_vector(data_width-1 downto 0); > begin > > i_ibufgds: IBUFGDS_LVDS_25 > port map ( > I => mainclk_p, > IB => mainclk_n, > O => mainclk > ); > > -- put in a DCM > i_dcm : DCM > port map ( > CLKIN => mainclk, > CLKFB => clk, > DSSEN => '0', > PSINCDEC => '0', > PSEN => '0', > PSCLK => '0', > RST => rst, > CLK0 => clk0, > LOCKED => open > ); > > -- and a bufg > i_bufg: bufg port map ( > i => clk0, > o => clk > ); > clk_n <= not clk; > > -- Now the test code > g_ibufds: for i in diff'range generate > diff0: IBUFDS_LVDS_25 port map ( > I => diff_p(i), > IB => diff_n(i), > O => diff(i) > ); > end generate; > > process (clk) begin > if rising_edge(clk) then > difft <= diff; > diffout <= difft; > end if; > end process; > -- Falling edge clock is in a seperate process to avoid > -- problems with some synthesis tools. > process (clk) begin > if falling_edge(clk) then > difft_n <= diff; > diffout_n <= difft_n; > end if; > end process; > end; >Article: 71051
frle@hrz.tu-chemnitz.de wrote: > Hi! > > Could anyone explain, what are route-throughs in look up tables and why > are they used? When I run the map command (xilinx) on my design, I get > in the report file (design.mrp) a section: > > Design Summary: > Number of errors: 0 > Number of warnings: 3 > Number of CLBs: 124 out of 324 38% > CLB Flip Flops: 81 > 4 input LUTs: 203 (3 used as route-throughs) > 3 input LUTs: 68 (13 used as route-throughs) > Number of bonded IOBs: 62 out of 144 43% > IOB Flops: 0 > IOB Latches: 0 > Number of clock IOB pads: 1 out of 8 12% > Number of primary CLKs: 1 out of 4 25% > Number of startup: 1 out of 1 100% > > Thanks in advance > > Frank > A route-through LUT is used any time an external signal needs to reach a slice resource that can only be reached by using a LUT. The most common case is when it's necessary to reach a FF D-pin when the direct connection BX/BY is already used for something else, such as CIN or F5/F6MUX select. Regards, BretArticle: 71052
Hi, Im calculating the memory bandwidth achievable when interfacing a Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT SRAM (128k x 36bit). In general I have found the Spartan 3 datasheet very good (I like the text/description column in the switching characteristics section of the datasheet) but in the following instance I am stuck (probably due to my lack of understanding rather than the datasheet.) To do the memory bandwidth timing calculation I need to know the following FPGA IOB timing: 1)the clock to out delay for the IOB OFF(output flipflop) and 2)setup time for the IOB IFF(input flipflop). Finding 1) from the datasheet: I found table 12 on page11 of the DC and switching characteristics section. The "pin to pin clock to output time for the IOB output path" is Tickofdcm = 2.59ns. (DCM in use) But then when I look deeper into the datasheet I also find table 17 on pg 16 called Timing for the IOB output path. Tiockp gives a clock to output time of 4.18ns. What is the difference between these two timing paramaters? What I want to know is the time from a rising edge on OFF's OTCLK to the data bit appearing at the FPGA Pin on the PCB. Finding 2) from the datasheet: Table 13 on pg 12 is called "pin to pin setup and hold times for the IOB input path". Tpsdcm = 2.72ns is the relevant parameter. But then table 14 "Setup and hold times for the IOB input path" show Tiopick = 1.32ns. Which of these two timing parameters should I use? what is the difference? Notes: The IO standard used is LVCMOS25 I am using Spartan 3 datasheet DS099, march 4, 2004. I also noticed an interesting thing in table 19, output timing adjustments for IOB, LVCMOS25 FAST. The 16mA and 24mA drivers are slower than the 12mA drivers? I expected them to be faster. Also noticed the datasheet seems to be "advance product specification" which according to the datasheet is described as "These specifications are based on simulations only...." Scary stuff. Is there a more appropriate place I should be getting my timing numbers from, e.g. download latest speed files and use timing analyzer? Is the documentation just out of date? They must have characterized the production silicon right? Regards AndrewArticle: 71053
Hi, all: In my 40MHz design, ISE failed to route a few wires in the end, with complaints on timing violations also. In fpga_editor, I could observe only a chunk of sinita/sinitb are green fly wires...When I first core_gen-erated these block RAMs, I excluded sinita/sinitb...Why so special about all these sinita/sinitbs? Best Regards, KelvinArticle: 71054
Hi, My question is very simple but i cant find any answer to it juste loocking at xilinx site or reading there data sheets. My question is : Do any one have an exemple of template for instantiating xilinx Virtex II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18. Thanks in advence.Article: 71055
Oleg wrote: > Hi, > My question is very simple but i cant find any answer to it juste > loocking at xilinx site or reading there data sheets. > My question is : > Do any one have an exemple of template for instantiating xilinx Virtex > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18. Have a look at the Libraries guide - it has all the VHDL and Verilog instantiation templates. You should have this in Xilinx\doc\usenglish\books\docs\lib\lib.pdf or it should be on the Web as well. Hopefully that's what you're looking for! PeterArticle: 71056
Hi Christoph,
Thanks a lot for bringing that to my attention. Inspite
of using a jumper for channel B and the changing the code for channel
B I still get a 0 voltage output. I think I am running into some
timing issues.
Did you use the 24 bit or 32 bit load sequence ? If
possible could you post first few lines and last few lines of the dac
controller code.
Thanks once again for your prompt post. I was about to
use another D/A
Thanks
Makesh
Christoph Brinkhaus <c.brinkhaus@t-online.de> wrote in message news:<r40fcc.ql.ln@lola.de>...
> Makesh Soundarajan <makesh_s_e@hotmail.com> wrote:
>
> Dear Makesh,
>
> > Hi
> >
> > Has anybody used the D/A converter (Linear Tech's LTC1654) ? I am
> > having few issues . I tried to initialize using both the 24 and 32 bit
> > format but the output of D/A remains at 0.
> >
> I have had some small problems with the LTC1654 as well.
> Have you also started with the DAC A output?
>
> There is a small problem with the output gain configuration of the LTC1654.
> There is one pin per DAC which should be either connected to GND or to
> the DAC output - if I remember correctly. On the board the DAC A config
> pin is hardwired to VCC and the DAC B config pin is connected to VCC by
> a resistor but can be shorted to GND by a 2-pin jumper close to the DAC.
>
> If you close the jumper at least DAC B should work. To make DAC A
> running you have to lift the corresponding pin of the LTC1654 and
> connect it to GND with a short wire. There is one capacitor connected to
> GND close to that pin. This is a suitable point to get the GND signal
> from.
>
> > Any help will be greatly appreciated
> >
> I hope it helps. I guess you have the datasheet of the LTC1654,
> please look for the gain setting for detailed infos.
> >
> > Thanks
> > Makesh
>
> I like the compact board, also because of its on board peripherals.
>
> Best regards,
>
> Christoph
Article: 71057> Yes, all CRC's produce a residual - it is a function of the following items: > > * The CRC polynomial being used (CRC-16 vs. CRC-CCITT vs. CRC-32, etc) > * The initial value (sometimes all 1's, but not always) > * Bit and byte ordering (application dependant) > * Bit inversion (application dependant: sometimes XOR with all 1's) > > > Have fun, > > Marc Hi Marc, thank you for your answer. I want to use a CRC16 with the polynomial 0XBAAD (paper "Cyclic Redendany Code Poynomial Selection for Embedded Networks" Philip Koopman). But when I simulate it (VHDL code generated by CRC TOOL) and initialize it with '1's than I do not get a residual when trying different data to calculate. So maybe there has to be used a different initial value. But how do I get to know which one to use as initial value? Kind regardsArticle: 71058
Paul and Luc, There is no contridiction, they look good the new Lattice parts, my point was that the DSP block (stratix) is similar to DSP-blocks in Lattice. My second point was that the marketing done by Altera for CycloneII they have never called the embedded multipilers for DPS-blocks since they as pointed out are not. The battle for FPGA supremacy continues ... Cheers Fredrik paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407061111.18b75a94@posting.google.com>... > I agree with Luc. The DSP blocks are just great for a low cost FPGA. > Stratix have the same or similar but you need to pay for them. > Another point that Luc mentioned is the DDR capabilities. There is a > dedicated hardware (DLL and input registers) to facilitate the DDR > interface without needing to waste LUT on it. I like that as well. > Clocking scheme looks good. Great range of freq from analog PLLs. > Normal 4 quadrants. It seems the market for the low cost FPGA is > getting hot with one good new member. .. > > paul > > Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<jflke0156m53oldb1laiu7cjuf2ljujgtf@4ax.com>... > > Fredrik, > > > > I don't want to start a discussion about the chicken and the egg and.. > > You are right about Stratix, but Lattice has implemented them in a low > > cost device, and there is the advantage. If you don't want to spend > > lot's of $$ on features you're not going to use, this ECP-DSP family > > is a very good alternative, and the performance ... well look for > > yourselve and try a benchmark. > > Luc > > ___ > > for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com > > (Fredrik) wrote: > > > > >Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>... > > >> IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice > > >> is proposing is much richer: reg, mult, pipeline reg, accu, reg. On > > >> top of it, the IO cell has more regs than any other comparable > > >> architecture. > > >Please have a look at: > > >http://www.altera.com/products/devices/stratix/features/stx-dsp.html > > >and then see where Latice got thier ideas from. But you are correct > > >for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has > > >chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP > > >block a mulitiplyer you have to say the same about Latice since there > > >are at least on the marketing slides I have seen identical. > > >YMHO > > >FredrikArticle: 71059
Phil, It works just fine with Precision. The "-pr b" option is the default one so... just adding the extra pipe of FFs made the trick. Excellent! Thanks again, very appreciated. Regards, -- I. Ulises Hernandez 'ulises' at posting domain should work for email "Phil Hays" <Spampostmaster@comcast.net> wrote in message news:cr2me0pm20cbkok7htbv1mifhifegbt95k@4ax.com... > "I. Ulises Hernandez" <delete@e-vhdl.com> wrote: > > >Your English translates brilliantly to Spanish :O) > > Good, as my Spanish is beyond awful ;-) > > > >I have built successfully your 'diffddr' module with Leonardo and Precision, > >still a problem though... > > Please try the following code. I increased the generic width to 8, as > that is what you are targeting. I added another layer of FFs to make > sure there was no ambiguity as to where to force the FF into, and > verified the map was forcing FFs into IOBs (map report file will have > "-pr b" on the command line). I also split the clocked process into > rising and falling edge sections as I have seen problems with this in > the past. XST handles the following code correctly. > > > -- > Phil Hays > Phil-hays at posting domain should work for email > > ---------------------------- Cut Here ----------------------------- > > library ieee; > use ieee.numeric_std.all; > use ieee.std_logic_1164.all; > library unisim; > use unisim.vcomponents.all; > entity idiffddr_g is > generic > ( > data_width : integer:=8 > ); > port ( > mainclk_p : in std_logic; > mainclk_n : in std_logic; > rst : in std_logic; > diff_p : in std_logic_vector(data_width-1 downto 0); > diff_n : in std_logic_vector(data_width-1 downto 0); > diffout : out std_logic_vector(data_width-1 downto 0); > diffout_n : out std_logic_vector(data_width-1 downto 0) > ); > end entity; > > architecture rtl of idiffddr_g is > signal mainclk : std_logic; > signal clk0 : std_logic; > signal clk : std_logic; > signal clk_n : std_logic; > signal diff : std_logic_vector(data_width-1 downto 0); > signal difft : std_logic_vector(data_width-1 downto 0); > signal difft_n : std_logic_vector(data_width-1 downto 0); > begin > > i_ibufgds: IBUFGDS_LVDS_25 > port map ( > I => mainclk_p, > IB => mainclk_n, > O => mainclk > ); > > -- put in a DCM > i_dcm : DCM > port map ( > CLKIN => mainclk, > CLKFB => clk, > DSSEN => '0', > PSINCDEC => '0', > PSEN => '0', > PSCLK => '0', > RST => rst, > CLK0 => clk0, > LOCKED => open > ); > > -- and a bufg > i_bufg: bufg port map ( > i => clk0, > o => clk > ); > clk_n <= not clk; > > -- Now the test code > g_ibufds: for i in diff'range generate > diff0: IBUFDS_LVDS_25 port map ( > I => diff_p(i), > IB => diff_n(i), > O => diff(i) > ); > end generate; > > process (clk) begin > if rising_edge(clk) then > difft <= diff; > diffout <= difft; > end if; > end process; > -- Falling edge clock is in a seperate process to avoid > -- problems with some synthesis tools. > process (clk) begin > if falling_edge(clk) then > difft_n <= diff; > diffout_n <= difft_n; > end if; > end process; > end; >Article: 71060
Joseph, I tried the software, and it looks good. As you mentioned, they share a similar GUI, even the EPIC editor is similar. Of course the libraries aren't complete yet, but it gives you a good feeling of the possibilities. You're right, with the introduction of the 90nm SC parts, I think they can compete with every other high-end FPGA. Luc ___ On Tue, 6 Jul 2004 21:18:17 +0000 (UTC), jhallen@TheWorld.com (Joseph H Allen) wrote: >Have any of you tried Lattice's software for their new -EC parts? How close >is it to Xilinx (they share a common heritage)? I'm trying to get a feel >for its quality and stability. > >Things should be getting interesting when their 90nm -SC parts come out (vs. >Stratix-II and Virtex-4), especially with their cool DDR I/O interface. >Perhaps Lattice will make a come-back?Article: 71061
mx <mx@mx.com> wrote > (c) If the customer is acquired (purchased) by another company, the > EDA-software is non-transferrable. Thankfully within industry, the > standard practice is for the vendor to permit the ownership transfer, as > long as the new owner continues to pay the maintenance/support contract > obligations. Synopsys didn't allow us to transfer the license, while our company was aquired, until we made clear, that this would be a good point to get rid of all Synopsys software in our company. And in fact it was an important point for the next software purchase that we prefer any other company when two tools seem technically equivalent. bye ThomasArticle: 71062
news@sulimma.de (Kolja Sulimma) wrote: > license_rant_master <none@nowhere.net> wrote in message > > /RANT ON > > > > 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement > > as their premiere Modelsim/SE. > [...] > > At a minimum, > > someone needs to challenge their ridiculous license agreement > > for products aimed at 'personal' use. > > (Disclaimer: IANAL) > Site wide licenses definitely are licenses and the two companies > involved can agree basically on any ridiculous licensee term that they > can up with, but this might not be the case for a personal edition. > > For example if you can manage to buy modelsim PE in a shop or order it > online without clicking through the license agreement than you just > made a regular purchase and there is no license agreement involved. > Even if you click through the license agreement it is very doubtfull > that it is valid. Basically a purchase is a purchase not matter what > you call it and the first sale doctrine applies, which means that the > rightholder can not control the use of an item after the first sale. Be careful. License law is a very hard field, especially if different countries are involved. If you download your software, there might be the law of two countries involved, which complicates everything. In Germany your are right that you could ignore any license agreement, when purchasing a standard programm (enter the shop and buy a CD). But you have to deal with the license agreement, when purchasing a license (or get it free) by downloading a software. These are two different things, which seem very similar. bye ThomasArticle: 71063
Hello Gabor, Your reply seems reasonable but that cannot explain why even Altera gives 18X18 multilpiers? You are right that in case of an FPGA any data width would do, but if we look at the conventional DSP designs or DSP processors we see that normally 8bits, 16bits or 32 bits are used. This would mean that many of the designs that are imeplemented in these FPGAs would also have 8/16/32 bit data widths. So does this mean that Xilinx gave it to integrate with its memory and Altera gave it because XIlinx gave it? Regards, Deboleena.Article: 71064
Hi Friends, We are making Altera FPGA and CPLD downloader ByteBlaster. It can replace Altera ByteBlaster and ByteBlaster MV directly to program/configure various Altera PLD devices, reliable and affordable with a very low price. We also sell FPGA demo board. For detail information or buy on-line, please check at http://www.minford.ca. Thanks, James Wang Minford Technology E-mail: info@minford.ca http://www.minford.caArticle: 71065
ALuPin wrote:
>>Yes, all CRC's produce a residual - it is a function of the following items:
>>
>>* The CRC polynomial being used (CRC-16 vs. CRC-CCITT vs. CRC-32, etc)
>>* The initial value (sometimes all 1's, but not always)
>>* Bit and byte ordering (application dependant)
>>* Bit inversion (application dependant: sometimes XOR with all 1's)
>>
>>
>
> thank you for your answer.
>
> I want to use a CRC16 with the polynomial 0XBAAD (paper "Cyclic
> Redendany Code
> Poynomial Selection for Embedded Networks" Philip Koopman).
>
> But when I simulate it (VHDL code generated by CRC TOOL) and
> initialize it with '1's than I do not get a residual when trying
> different data to calculate.
> So maybe there has to be used a different initial value. But how do I
> get to know which one to use as initial value?
We're pretty far off topic here, but I'll give it one last stab while
presenting some links that might be useful for the FPGA crowd... I found
a neat tool on the web:
http://rcswww.urz.tu-dresden.de/~sr21/crc.html
which lets you play with various things. You might be able to feed your
simulated data into this tool and see if things match up. Using this
tool, I was able to get the residual (MAGIC NUMBER) by clicking
"nondirect" then clicking "Convert"... The initial value field will
turn into the residual (or bit flipped residue, depending on the CRC
implementation).
IE, for CRC-32, clicking nondirect and convert results in C704DD7B and
CRC-CCITT results in 1D0F. Using the same procedure for Koopman's new
polynomial 0xBAAD results in a possible residue of 3BE9 when calculated
in the same way a CRC-CCITT (initial value of FFFF with no bit flipping
or reversing).
Various links to HDL code:
http://www-ee.eng.hawaii.edu/~msmith/XCoNET/Demonstation_code.htm
http://www.bydzw.com/cpldpage/download/crc32.txt
http://www.elecdesign.com/Articles/ArticleID/3961/3961.html
Lastly, make sure you are feeding the whole received data block into the
CRC checker (including the received CRC). If you can't use the tool
above to verify your values, you could use a C program.
Good luck,
Marc
Article: 71066Hi All, I'm trying to synthesize the folllowing VHDL file with the Xilinx WebPack tools. I'm synthesising for a XC3S200 chip. When I run XST it generates one 256 bits serial register and assigns outD and outD1 both to the same output of the shift register (I checked with the RTL schematic viewer). Changing outD1 <= fifo(28); to outD1 <= fifo(7); (or any other number below 16) generates two shift registers as expected. Did I run into a XST bug or do I something terribly wrong (I'm new to VHDL). Version used 6.1.03i (It isn't the latest version I think but happens to be on the PC I'm using at the moment) Thanx, Peter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. -- library UNISIM; -- use UNISIM.VComponents.all; entity test2 is port ( clk: in std_logic; inD: in std_logic; outD1: out std_logic; outD: out std_logic ); end test2; architecture Behavioral of test2 is signal fifo: std_logic_vector(0 to 255); begin process(clk, inD) begin if (clk'event and clk='0') then fifo <= fifo(1 to 255) & inD; end if; end process; outD1 <= fifo(28); outD <= fifo(0); end Behavioral;Article: 71067
Peter Waldeck <waldeck@NOSPAM.itee.uq.edu.au> wrote in message news:<newscache$wcog0i$g35$1@bottle.itee.uq.edu.au>... > Oleg wrote: > > > Hi, > > My question is very simple but i cant find any answer to it juste > > loocking at xilinx site or reading there data sheets. > > My question is : > > Do any one have an exemple of template for instantiating xilinx Virtex > > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18. > > Have a look at the Libraries guide - it has all > the VHDL and Verilog instantiation templates. You > should have this in > Xilinx\doc\usenglish\books\docs\lib\lib.pdf or it > should be on the Web as well. Hopefully that's > what you're looking for! > > Peter Hi, Thanks Peter, i found a very helpfull info on toolbox.xilinx.comArticle: 71068
sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0407061027.203ab84e@posting.google.com>...
> rrr@ieee.org (Rajeev) wrote in message
> > So here's my questions...
> >
> > (1) Is it a bad idea to use 'X' in a simulation ?
> >
> > (2) Is there something I'm missing that explains this behavior ?
> >
> > (3) I tried other logic functions and all possible 2-input
> > combinations with
> > 9-valued inputs. The mux is the only thing that I find puzzling. Is
> > there
> > a preferred way to write the mux ?
>
> Hi Rajeev,
>
> The Quartus simulator is not a behavioral simulator. It simulates a
> synthesized circuit which is functionally equivalent to the users
> specification. The synthesizer is free to assign an 'X' signal to
> either 1 or 0 to reduce the logic.
>
> Hope this helps.
> - Subroto
Subroto,
Thank you for taking the time to respond. I'm not sure what to
conclude
from your email however.
Let me mention a few things...
a. There is no 'X' value in the design. The synthesizer never sees an
'X'. The 'X' is a simulation input (and output) only.
b. I'm afraid I cannot see what synthesized circuit is equivalent to
my specification but gives output=0 for all 3 inputs = 'X'.
c. In v4.0 (I should look in 3.0 also) the synthesis results in a
_single_
equation that is fed to both outputs Y and Z. That equation is
A1L7 = A & (B # Sel) # !A & B & !Sel;
Y = OUTPUT(A1L7);
Z = OUTPUT(A1L7);
Yet Y and Z simulate differently ! So, what is the simulator
simulating ?
Incidentally I can't help being curious why the synthesizer prefers
this form to
A1L7 = A & Sel # B & !Sel;
Regards,
-rajeev-
Article: 71069Hi, Help me please to fixe the folowing probleme: When i open PACE window (ISE 6.1)to create area constrainte (region), in the design broser window (top most left window in PACE) there are 3 folders : I/O pins, Global Logic and Logic, this last one should containe the logic of my design(by blocks) but its empty, Why? how to fixe this? is it because the tool dont keep the heararchy of the design??? Note: this happen when i use VHDL entrance to ISE tool,but does not if i use Synplify to synthesis my design and then i entre EDIF file to ISE(her i can see and plce my blocks). This is very important for me since i need to place manualy some blocks of my design to get a better speed. Thanks for any help.Article: 71070
Hi, The spartan 3 kit from Nu Horizons doesnt come with EDK (for microblaze) as standard. You have to buy it separately. The kit works with the free ISE Webpack. You just need a parallel port cable. The kit is really good. It has A/D, D/A, config flash ,LCD and others. Hope this helps Makesh "Hank" <nospam@nospam.com> wrote in message news:<CNCGc.28775$qw1.92@nwrddc01.gnilink.net>... > Hi guys, > > I am mostly a newb at fpga design, although I did a teeny bit of work on a > Spartan II design a few years ago in verilog. > > Anyway, I would like to learn vhdl, and get a development board because I like > to supplement endless reading of textbooks with some hands-on experiments. I > will probably purchase Ashenden's book soon. > > So, I have found two starter boards which look interesting...the $99 Spartan 3 > starter kit from Xilinx, and the $164 Spartan 3 starter kit from Nu Horizons. > > Before I saw the Nu Horizons board, I was ready to get the Xilinx starter kit. > Now, I am torn between the two. I know nothing about the Microblaze core...does > the Nu Horizons board come with all the IP you need to do endless experiments > with this core, or do you need to pay the $495 edk to Xilinx to get usefull IP? > If you get everything you need with the $164 Nu Horizons board, then I am sold > on that, because I have several projects in mind that would greatly benefit from > the larger Sparten 3 part, the 64MB of sdram and the 32MB of flash. The D/A is > very nice too...I have an application for that as well. > > Opinions? > > Thanks! > > HankArticle: 71071
Hank wrote: > I am mostly a newb at fpga design, although I did a teeny bit of work on a > Spartan II design a few years ago in verilog. > Anyway, I would like to learn vhdl, and get a development board because I > like > to supplement endless reading of textbooks with some hands-on experiments. > I will probably purchase Ashenden's book soon. That's the right book. Learning vhdl has more to do with your simulator than the board. Pick the board with the interfaces you need. -- Mike TreselerArticle: 71072
For a few critical paths it's possible to guide the P&R tool without resorting to full manual floorplanning. The RLOC (relative location) constraints allow you to build up a macro of a few critical registers, LUTs, or other primitives. By specifying where elements in the critical path need to be relative to each other, the P&R tool has an easier time producing the results you need. If the number of critical routes is large, this technique might not be so desireable. "Kelvin" <student@nowhere.com> wrote in message news:40ea7188@news.starhub.net.sg... > After compiling few FPGAs, I have found this phenomenon. > When the design occupies a small fraction of the FPGA, par throws the stuff > loosely spread > all over the FPGA...like ugly zigzags... > When the design occupies 80% of the FPGA, par kompresses my design densely > into the bottom > 60% of the FPGA, leaving top 40% loosely occupied...then it tell me it > failed route...:( > Weird! > > What may I do besides manual floorplanning? > > KelvinArticle: 71073
The Xilinx software gives me the option of using or not using the IO buffers for the actual pins in which input/outputs will be connected. Does this mean that I can actually program the FPGA to not use the buffers? If so, would there be an increase in speed, since the buffer delay is no longer a problem? Thanks...Article: 71074
Sorry Rob, the only way in and out is through the buffers. The option to leave them out is for the case where you're making a block of logic which will be used within another design. This sub-block would not want I/O buffers because it's instantiated within a larger block. Cheers, Syms. "Rob Chavan" <rob.chavan@nectx.com> wrote in message news:ee876a1.-1@webx.sUN8CHnE... > The Xilinx software gives me the option of using or not using the IO buffers for the actual pins in which input/outputs will be connected. > > Does this mean that I can actually program the FPGA to not use the buffers? If so, would there be an increase in speed, since the buffer delay is no longer a problem? > > Thanks...
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