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Hy guys, I'm currently working on a 10/100 ETHERNET mac implementation in an FPGA (using vhdl). in order to simulate my state machine I need to feed a real ETHERNET packet to it (in order to see if the crc check is exeuted correctly etc.). I will realy appreciate to get a complete ETHERNET packet (all bytes from PREAMBLE to FCS) so I could insert it to my modelsim simulation. the format I'm expecting is as follows.. [55][55][55]... -> .. [FCS3][FCS2][FCS1][FCS0]Article: 71201
On 12 Jul 2004 01:43:55 -0700, moti@terasync.net (Moti Cohen) wrote: >Hy guys, I'm currently working on a 10/100 ETHERNET mac implementation >in an FPGA (using vhdl). in order to simulate my state machine I need >to feed a real ETHERNET packet to it (in order to see if the crc check >is exeuted correctly etc.). I will realy appreciate to get a complete >ETHERNET packet (all bytes from PREAMBLE to FCS) so I could insert it >to my modelsim simulation. > >the format I'm expecting is as follows.. > >[55][55][55]... -> .. [FCS3][FCS2][FCS1][FCS0] You could use a network sniffer to capture a packet from your LAN. This will not capture the preamble and is unlikely to capture the CRC. You may get lucky though. I just checked with Ethereal ( http://www.ethereal.com/ ) and it didn't capture the CRC on my hardware :( Or, you could ask on news:comp.dcom.lans.ethernet, where this question would be on-topic. Regards, Allan.Article: 71202
Phil Your allusion to "common" DCM / DLL issues has aroused my curiosity. Could you elucidate please. Martin "Phil Hays" <Spampostmaster@comcast.net> wrote in message news:imsoe05ptq3h66j0m4t0ha1dqsdrure8j3@4ax.com... > "Jerker Hammarberg (DST)" <jerkerNO@SPAMdst.se> wrote: > > > > How is the reset signal handled? If the FFs are asynchronously reset, > > > then the end of reset can happen at different times to different FFs, > > > leading to an illegal state. > > > >Hi Phil! I use no reset signal at all; instead I specify initial values > >for all signals by the declarations, which is supposed to work fine with > >XST. > > You do have an asynchronous reset, you just didn't know that you did. > When a Xilinx FPGA finishes the program download, it has all initial > values held until an internal signal is released. This release is > asynchronous to your clock. To avoid problems with this add a counter > that is reset to all zeros. Until that counter counts to 15, keep the > state machine in the initial state. > > (Note: Startup is a messy subject. This is a simplified version.) > > There is another common issue with DCMs or DLLs that you might also be > having a problem with. Are you using a DCM or a DLL? > > > > But your point is still interesting in case I would need to > > introduce an asynchronous reset some day. Does that mean one should > > avoid them if illegal states are a concern? > > Yes. Suppose the initial state is "100" and the desired next state is > "010". This would be a three state one-hot machine. > If the first bit is held until just after the first edge of the clock > and the second bit is held until just before the first edge of the > clock, then the next state will be illegal, "110". > If the first bit is held until just before the first edge of clock and > the second bit is held until just after the first edge of the clock, > then the next state will be illegal, "000". > > Does that make it clear? > > > -- > Phil Hays > Phil-hays at posting domain should work for emailArticle: 71203
AndyAtHome wrote: > Hi All, > > I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP > core is too costly for the volumes I will be building, so I'm looking > at PCI controller chips. > > From experience can anybody recommend a vendor, such as Quicklogic, > AMCC, Tundra, etc. > > Thanks, > > Andy. If Target PCI core is enough for your product, we have a complet package coming with : - ezPCI PCI Core (target only) VHDL or pre-synthesized code - linux drivers - w2k, xp, nt ,win98 drivers It is very easy to use and will allow you to skip the need of PCI interface chip ;-) Our PCI package was used by 4 companies for specific products. Works well, but it is target only for now. Please contact me to know the prices. Laurent Gauch www.amontec.comArticle: 71204
Hi, does someone know links to FPGA/CPLD related sites about VHDL design of VGA controller, hsync, vsync, composite sync in general ? I would appreciate your help. Kind regardsArticle: 71205
ALuPin wrote: > Hi, > > does someone know links to FPGA/CPLD related sites about > VHDL design of VGA controller, hsync, vsync, composite sync in general ? > > I would appreciate your help. > > Kind regards Take a look at the projects of the Queensland University http://www.itee.uq.edu.au/~peters/xsvboard/ Best regardsArticle: 71206
kommandantklink@hotmail.com (Wilhelm Klink) wrote in message news:<6011e208.0407112220.19b999a7@posting.google.com>... > I've got an FIR design that runs out of FPGA memory in an ep1s60 when > I set the data width to 24-bit (The design fits with a data width of > 16-bit). However only 13% of the total memory is used. I assume the > problem is that I have lots of smaller memories, and they cannot share > the same memory blocks (M512, M4K, M-RAM). Can anyone who has > experienced this problem share their strategies for dealing with this. After fitting there is the FITTER report (resource section --> fitter resource usage summary). Here you can see the usage of total memory bits and the usage of complete M4K memory blocks. RgdsArticle: 71207
rrr@ieee.org (Rajeev) writes: <snip> > > To be a bit more specific, 'U' is the undefined or "start-up" state. > > 'X' is what appears when you drive two clashing values onto a > > std_logic. Or when the simulator sees a D input change inside the > > setup-hold window of a FF. > > Also, Stratix MegaRAM cannot be initialized. When I inspect the > contents in the Quartus v4.0 simulator it is full of 'X'. > Ahh, I may have missed the fact you were using the Quartus simulator - that may or may not be VHDL-compliant in its usage of these symbols - my comments were aimed purely from the VHDl point of view. If the Quartus memory model is full of X in a VHDL simulation, that's because the model has 'initialised them' that way, the VHDL simulator will put U everywhere until told otherwise... > > I've never used an 'X' in simulation - created a few inadvertently > > though... > > > > If you want a "don't-care" use '-' instead. > > I had imagined '-' as something to be specified on an output that > would match any of the other 8 values. I guess I need to study the > definitions and usage of these other states. > That is the case in VHDL, sort of. Don't know about Quartus. I say sort of, because if you compare two std_logics using the "=" operator, a '-' will only match a '-', so it won;t act the way you might expect. To do that you have to use (IIRC) std_match from the numeric_std library. See here for more details: http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#dont_cares This is VHDl, though - not knowing anything else about the Quartus built-in simulator, I'd better shut up now! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 71208
Thanks - two votes for PLX, I'll check them out. Andy.Article: 71209
Hi Fred, > I'll look more closely at Pathfinder to see if it details how the switchbox > settings are determined. I'm not quite sure what you mean by this. If you're referring to how the topology of the switchbox is determined (an architectural decision), there are some other papers I can point you to. From a routing algorithm perspective, it is really quite simple. You represent the entire chip as a graph where each node represents a routing resource -- a block input, block output, or routing wire. Directed edges are placed between these nodes to represent the presence of a (programmable) connection from one resource to another. So a swich box that is not a complete cross-bar is encoded in this graph as edges. For each net, the router starts at the source block output, traverses the edges from that node, and assigns a desirability/cost to each of the nodes seen and places them in a heap. It then removes the best node from the heap and repeats from there until it hits the desired destination (a block input). This is known as an a-star or best-first traversal, and clearly all the work/intelligence lies in how you cost the nodes (including a prediction of future cost), how you guide the router to correct congestion, etc. For a multi-terminal net, the routing thus far is placed on the heap and the router expands from there. There are optimizations that can be done to reduce the amount of re-expansion of the wavefront, and other techniques for quickly routing high-fanout nets. Global routing (not worrying about precise wires and switch box settings) is done using the same algorithm, except that rather than nodes representing one wire, you represent a group of wires with a node of capacity = channel width. A well-written global + detailed router does not require a global route and performs fast enough that there really isn't any point to look at global routing (in FPGAs) anymore. > If anyone can comment on how relatively wide-spring are the various > algorithms, both in academia and industry, that would be helpful. > Papers often reference other papers, but don't actually indicate which > algorithms are used by which commercial tools, and how prevalent are > the various commercial tools. Vaughn's website says Right Track is > now part of Altera, so maybe Altera's own tools may start using ideas > from VPR. I have yet to come across information about what was the > algorithm prior to this. What about Xilinx? Is it the case that they > don't like to disclose the actual inner workings of their native > tools? How common is it to use 3rd party tools for place-and-route > rather than those from the vendor? In general, information about > which commercial tool (vendors) use which algorithms seems much rarer > than just the algorithms presented in isolation. We don't like to tell each other what we do in our tools for obvious reasons :-) VPR served as the basis for Right Track CAD's work, and Right Track provided Altera with enhanced place & route results for their FLEX10K products in MaxPlus II. What the algorithms were before or what they've become since is not a matter of public record. Regards, Paul Leventis Altera Corp.Article: 71210
There is no precise answer U can give without knowing all the aspects of your problem. For instance, your proposal to have an OR function may be dangerous if you use the result directly or indirectly as a clock to some other logic. In that case, I am pretty sure the output will glitch, which is not a problem at all if the output signal is reclocked for further use. Apart from that remark, many solutions are possible, as you stated. Just try them . Another idea is to use a two bit state machine that controls an output flip-flop. Johan Bernspång <xjohbex@xfoix.se> wrote in message news:<ccjddj$39r$1@mercur.foi.se>... > Hi all, > > What would be the optimal way, in terms of device utilization and > functionality, to exstend the length of the time a signal is asserted > from one clock cycle to four clock cycles. I.e. > [pseduo code:] > if signal a is asserted then > signal b is asserted for four clk; > > Is it possible to accomplish the function by utilizing an SRL16, or is > there a better solution? Or should I simply create four delayed versions > > of signal a, and OR them together to form signal b? > > I'm working with a Virtex-2 device. > > regardsArticle: 71211
On Mon, 12 Jul 2004 10:26:21 +0100, "DrB" <nospam@nospam.no> wrote: >> There is another common issue with DCMs or DLLs that you might also be >> having a problem with. Are you using a DCM or a DLL? >Your allusion to "common" DCM / DLL issues has aroused my curiosity. Sure. I'm not sure "common" was the correct word, but I suspected that the original poster might have run into the following issue. I've seen it in someone else's design. These problems are curable by reading the fine manual (RTFM). RTFM # 1 "Do not use the DCM output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement." You can keep the part in configuration until the DCMs are locked by a bitgen option, or you can use the synchronized locked signal to force reset to all state machines and all other critical logic. Better do one of the two. The bitgen option is probably best, unless you may be resetting the DCMs after configuration, in which case you need to do the second. I didn't think he had this issue, but I've seen it as well. In my own design. RTFM # 2 "To ensure consistent locking, if a DCM is configured with external feedback, applying a reset after configuration is strongly recommended." "Strongly recommended" isn't quite correct. "Required" would be better wording. -- Phil Hays Phil-hays at posting domain should work for emailArticle: 71212
Have you simulated your design? Is it fully synchronous? What is your external clock rate? /Mikhail "Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:cctf2s$hd7$1@sunnews.cern.ch... > Hi All, > This may be a strange question .. > I program 9 Xilinx Devices with the same bitstream file. > But some of them behave differently from the others. > Can anyone give me any suggestions on why this could be happening ? > Is the problem internal to Xilinx (if i am on the edge of timing on some > signals) > or it is outside in the signals coming to them ? > Any pointers will be really appreciated, > Thanks, > Adarsh > >Article: 71213
Andrew, DCI series termination does not draw any significant power. Only the parallel terminations are power hungry. Just because the resitances are on chip rather than off chip does not mean that there is no power dissipated: there is. Same power as if the resistors where off chip. Austin Andrew Dyer wrote: > On Fri, 09 Jul 2004 09:16:06 -0700, Austin Lesea wrote: > > >>Dan, >> >>Simulate it. >> >>I doubt seriously that picking off the signal before or after a resistor >>at the receiver will make any difference at all (after all, the receiver >>has nearly infinite input impedance, and about 7-8 pF of capacitive >>loading, so what does a 82 ohm resistor to a 7 pF cap look like? not >>much I assure you). >> >>As for setting the DCI resistance, use 82 ohm, or 33 ohm reference >>resistors to set the DCI series drive impedance to 82 or 33 ohms. >> >>I would simulate it in Hyperlynx using the various IBIS models fromt he >>different vendors to prove that it works with high and low Vcc, and with >>fast and slow process corners. >> >>A standard is a starting point. Either meet it exactly, and not worry, >>or simulate what you waht to do differently to prove it will always work >>the way you intend it to. >> >>Your choice. By the way, I even simulate a standard interface, as I do >>not trust that the standard's body could anticipate every possible use >>of their precious standard, or that every vendor really 'met' the >>standard when combined with the other vendors in the design. >> > > > Hyperlynx seemed like a good tool, but IIRC it didn't handle cables and > connectors very well. > > The best thing you can do on an ATA interface besides all the resistors > is to use the 80 conductor ultra-ATA cables. The extra return lines really > help. Obviously keep the ATA cable as short as possible. If you can only > put one device on the cable at the far end. The ATA standard termination > scheme is really ad-hoc, it was never really addressed until the standard > started to push the speed envelope. > > As for the DCI it does work, but my experience it's a real power hog. > We had a 64-bit DDR interface and turned it on for a trial, and what > used to be only a moderately warm FPGA turned into a burn-your-finger > cooker.Article: 71214
Thales, Contact the Xilinx University Program to obain a grant of some useful components and software. http://www.xilinx.com/univ/ We do not want you to teach students using obsolete and antiquated technology, we will supply you with what you need to teach them using current technologies. AustinArticle: 71215
Hi, Has anybody been trying to use gprof within the NIOS II IDE ? We have some problems regarding the profiling data that is send through the jtag interface directly to the IDE console window. We had a look to the documentation but there is little information regarding the use of the profiler with the NIOS II. It seems that, to the difference of NIOS I, the profiling data is sent as binary data, resulting in the following stdout trace : < Here the program standard output > **gmon.out data follows** < non readable binary data > nios2-terminal: exiting due to ^D on remote Does anybody knows how to solve this issue ? Thank you in advance, StevenArticle: 71216
"Amontec Team" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:40F25C3F.6030706@amontecDELETEALLCAPS.com... > > It is very easy to use and will allow you to skip the need of PCI > interface chip ;-) Personally I prefer using a separate chip because it allows me to load that FPGA through the PCI bus making field upgrades easy. I am waiting with putting PCI inside of a FPGA until modular design and partial reconfiguration will allow me to achieve the same level of flexibility. /MikhailArticle: 71217
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0407120157.6cf038c1@posting.google.com... > Hi, > > does someone know links to FPGA/CPLD related sites about > VHDL design of VGA controller, hsync, vsync, composite sync in general ? > > I would appreciate your help. > > Kind regards The xilinx spartan 3 starter kit documentation has quite a bit of info on vga signals and there is a vhdl file you can download here that has a vga character mapped controller (the microblaze package): http://www.xilinx.com/products/spartan3/s3boards.htmArticle: 71218
>Personally I prefer using a separate chip because it allows me to load that >FPGA through the PCI bus making field upgrades easy. I am waiting with >putting PCI inside of a FPGA until modular design and partial >reconfiguration will allow me to achieve the same level of flexibility. You don't need partial reconfiguration to do a field upgrade. Connect a couple of pins on the FPGA to the programming pins on the serial PROM. Use them to rewrite the bit stream, then power cycle. Not as convient for debugging. It also has the problem of leaving your board in a broken state if you drop power in the middle of the update. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71219
Hi, I did something similar to this, but the only difference is I used .ncd file and swapped the pin connections, then generated a partial bitstream( command line bitgen as described in xapp290 ). Ram vramtilak@gmail.com (Ramtilak) wrote in message news:<cabffaca.0407110021.4ab219d9@posting.google.com>... > Hi all, > > I need to dynamically reconfigure the pin connections. For example, > say, I have a port in my code which is attached to pin H3 of the > virtex-2 chip. Now, I want to reconfigure it using ICAP to attach to > pin G3. > Did anyone do anything of this sort before? I will be thankful if > someone can help me on this? > > Thanks, > RamtilakArticle: 71220
Do any placement algorithms try to make regular structures? For datapaths,
for example? This is how a human would do it, and might give excellent
results in some cases.
Although, you certainly want to architect FPGAs with enough routing
resources so that regular structures are not needed.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 71221AndyAtHome wrote: > Hi All, > > I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP > core is too costly for the volumes I will be building, so I'm looking > at PCI controller chips. > > From experience can anybody recommend a vendor, such as Quicklogic, > AMCC, Tundra, etc. > > Thanks, > > Andy. If it is just functionality you use, have a look here: http://www.fpga4fun.com/PCI.html /RobArticle: 71222
> Hello (again) from Gregg C Levine > Now where'd I go about obtaining the older XACT series of tools from? I don't > suppose the company still has them....... > Gregg C Levine drwho8 atsign att dot net You might be better off selling these parts on the gray market to someone who is still using them (I purchased some recently) and upgrading to the Spartan. The Webpack tools are free and the parts, besides being much better, are cheap. TomArticle: 71223
Let me say it loud and clear once more: The only meaningful use for FPGAs of the XC3000, 4000 and 5200 vintage is in existing equipment that for some reason cannot be redesigned. Otherwise donate these obsolete parts to the landfill, and use modern Virtex and Spartan parts instead. This applies especially to our dear educators. Just because we have got our grey hair fighting the hardware and software limitations in the olden days, that is no reason to contaminate young minds. FPGAs are an exciting way to learn, try out, and implement all sorts of logic. Just stay away from the musty stuff of the previous century ! Peter Alfke > From: soar2morrow@yahoo.com (Tom Seim) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 12 Jul 2004 09:36:48 -0700 > Subject: Re: Is the Xilinix XC3020 atill supported? > >> Hello (again) from Gregg C Levine >> Now where'd I go about obtaining the older XACT series of tools from? I don't >> suppose the company still has them....... >> Gregg C Levine drwho8 atsign att dot net > > You might be better off selling these parts on the gray market to > someone who is still using them (I purchased some recently) and > upgrading to the Spartan. The Webpack tools are free and the parts, > besides being much better, are cheap. > > TomArticle: 71224
Let's squash an urban legend: In its normal use as series terminator, DCI shows insignificant additional power dissipation ( and zero additional system power compared to external resistors). It is only when DCI is used as parallel termination that it draws a continuous current and thus dissipates significant power. Peter Alfke > > As for the DCI it does work, but my experience it's a real power hog. > We had a 64-bit DDR interface and turned it on for a trial, and what > used to be only a moderately warm FPGA turned into a burn-your-finger > cooker.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z