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> This has been discussed at great length on comp.lang.vhdl: > http://groups.google.com/groups?q=safe+state+machine+vhdl > > There's no simple answer. > Consider using the binary (minimal bits) setting > and see what you get. > > -- Mike Treseler Mike, Thanks. I will read the thread. It always seems to be a problem when I try a new tool. And your right, it is not a simple problem when the people developing the tools have not considered the problem. I would have thought the Quartus tool would have had this covered. I like using the Synplify tools for this reason. I had reposted the question to Altera last week but have yet to hear a responce. If anything comes of it I will post.Article: 72526
I all. I finally succeded (or at list I think I did!) in setting up the swift libraries to simulate my design with a PPC in it (Xilinx EDK6.2), but when I run the simulation with ModelSim XE I got this "strange" message: # ** Error: Failure to license for PE Swift Interface. # ** Error: Unable to check out PE Swift license. WHY PE edition if I have a XE edition, I did everything required (see http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14019 ) and I compiled the Xilinx libraries in ModelSim with the following command line??? compxlib -s mti_se -f virtex2p:m -l vhdl -w Does anyone out of there out to solve this issue? Thanks in advance, AndreaArticle: 72527
Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: ... : > Ok, it's the MainWin porting tool that requires the per-seat license. : > That's pretty much what keep Xilinx from having a set of free tools for : > Linux, correct? : > : Well, we don't use MainWin but, yes, that is correct. I don't understand that answer. Ise 6.2 clearly uses MainWin, or am I wrong? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 72528
The Swift interface is an option you have to pay extra for with ModelSim PE, and I assume XE. "Andrea Sabatini" <andrea@dapdesign_N_O_S_P_A_M_.com> wrote in message news:412a11a2$0$65124$e4fe514c@news.xs4all.nl... > I all. > > I finally succeded (or at list I think I did!) in setting up the swift > libraries to simulate my design with a PPC in it (Xilinx EDK6.2), but when I > run the simulation with ModelSim XE I got this "strange" message: > > # ** Error: Failure to license for PE Swift Interface. > # ** Error: Unable to check out PE Swift license. > > WHY PE edition if I have a XE edition, I did everything required (see > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14019 ) and I > compiled the Xilinx libraries in ModelSim with the following command line??? > > compxlib -s mti_se -f virtex2p:m -l vhdl -w > > Does anyone out of there out to solve this issue? > > Thanks in advance, > > Andrea > >Article: 72529
Mark -
The conversion between differential and single-ended happens
very close to the pin, so on the input side, you effectively
see a single ended signal going into the DDR flops. On the
output side, single ended data from the flops goes to the
output buffer (in the IOBs) and is converted into differential.
Here's some code I've used with XST to drive a DDR style
signal out to LVDS pins on a Virtex II-Pro:
output [13:0] dac_even_p; // dac even data port
output [13:0] dac_even_n; // dac even data port
// instantiate the DDR output cell
FDDRRSE u0ddr_q (.C0(clk_dac_n),.C1(clk_dac),
.R(1'b0), .S(1'b0),.CE(1'b1),
.D0(d_pipe[0]), .D1(dac_data[0]),
.Q(dac_even[0])
);
// instantiate the LVDS driver
OBUFDS_LVDS_25 u0obuf_even(.O (dac_even_p[0]), .OB (dac_even_n[0]),
.I (dac_even[0]));
As far as I know, you MUST instantiate DDR output flops, XST can't
infer them. It is able to infer DDR input flops.
You need to be careful that you actually assign CORRECT adjacent
pins for the LVDS signals in the .ucf file! Not all adjacent
pins can be paired up. Also, the polarities are fixed, ie,
one pin is the N, the other is the P and you can't swap them.
I hope this helps!
John P
jjohnson@cs.ucf.edu (Mark) wrote in message news:<c88fa005.0408201343.4a29a701@posting.google.com>...
> Howdy Gurus,
>
> I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS
> i/o and their DDR i/o, but haven't found a clear explanation yet of
> the two being used together.
>
> DDR by itself is pretty obvious, but the LVDS appears to work by a
> magical connection between two neighboring IOBs.
>
> For an LVDS input pair (Dp and Dn) coming in at DDR, does the
> differential-to-single-ended conversion take place before the input
> flops of the IOB?
>
> i.e., if Dp comes into IOB1 and Dn comes into IOB2, is there a
> single-ended output from some magical cell after the IOBs that I have
> to feed into two general CLB flops to get my registered Qre (rising
> edge) and Qfe (falling edge) outputs? (or specify an attribute to
> request that they be mapped into IOB flops?)
>
> Or, if the conversion to single-ended is done before the IOB flops,
> then the single-ended DDR data is easily clocked into the two IOB
> flops on opposite clock edges, right?
>
> If that is the case:
> Dp -> IPAD -> IOB1 ---\
> (diff2single) >----- Dddr -----> to IOB flops
> Dn -> IPAD -> IOB2 ---/ (single-ended)
>
> then which flops (those in IOB1 or IOB2) get the DDR data?
>
> A clear explanation would be great, code/constraint snippets would be
> lovely!
>
> Thanks,
>
> MarkJ
Article: 72530This is a multi-part message in MIME format. What is the proper VHDL code for bidirectional pins on a Xilinx chip? I used the code below but the chip runs hot. SRAM_BIDIRECTIONAL_PINS:process(SRAM_W_SIGNAL_5,SRAM_DQA_SIGNAL_5,SRAM_DQ= B_SIGNAL_5 ) begin if(SRAM_W_SIGNAL_5 =3D '1') then SRAMDQA <=3D SRAM_DQA_SIGNAL_5; SRAMDQB <=3D SRAM_DQB_SIGNAL_5; else SRAMDQA <=3D (others =3D> 'Z'); SRAMDQB <=3D (others =3D> 'Z'); end if; end process; Thanks, Brad b r a d @ a i v i s i o n . c o mArticle: 72531
On Mon, 23 Aug 2004 09:18:46 -0700, Robert Sefton wrote: > The Swift interface is an option you have to pay extra for with ModelSim PE, > and I assume XE. > > "Andrea Sabatini" <andrea@dapdesign_N_O_S_P_A_M_.com> wrote in message > news:412a11a2$0$65124$e4fe514c@news.xs4all.nl... >> I all. >> >> I finally succeded (or at list I think I did!) in setting up the swift >> libraries to simulate my design with a PPC in it (Xilinx EDK6.2), but when > I >> run the simulation with ModelSim XE I got this "strange" message: >> >> # ** Error: Failure to license for PE Swift Interface. >> # ** Error: Unable to check out PE Swift license. >> >> WHY PE edition if I have a XE edition, I did everything required (see >> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14019 ) and I >> compiled the Xilinx libraries in ModelSim with the following command > line??? >> >> compxlib -s mti_se -f virtex2p:m -l vhdl -w >> >> Does anyone out of there out to solve this issue? >> >> Thanks in advance, >> >> Andrea >> >> A SWIFT license is one of the things that differentiate PE from XE. You have to upgrade to XE if you want to use SWIFT models.Article: 72532
Uwe Bonnes wrote:
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote:
> ...
> : > Ok, it's the MainWin porting tool that requires the per-seat license.
> : > That's pretty much what keep Xilinx from having a set of free tools for
> : > Linux, correct?
> : >
> : Well, we don't use MainWin but, yes, that is correct.
>
> I don't understand that answer.
>
> Ise 6.2 clearly uses MainWin, or am I wrong?
Yes, you are wrong. Xilinx does not use MainWin
--
You've *read the email* - now *buy the book*
Article: 72533"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message news:pan.2004.08.23.17.45.14.800673@yahoo.com... > On Mon, 23 Aug 2004 09:18:46 -0700, Robert Sefton wrote: > > A SWIFT license is one of the things that differentiate PE from XE. You > have to upgrade to XE if you want to use SWIFT models. You're thinking of SE, which includes the SWIFT license. I think XE is just a Xilinx-specific version of PE, not a PE upgrade. My guess is that XE users have to pony up for the SWIFT license separately.Article: 72534
Hi, As I have asked in a previous post without any answer I ask it again : what is the relationship if any between SSO and the proper decoupling of an FPGA ? It seems there is one because the xilinx datasheet (the one I read) indicate a maximum sso provided decoupling is perfect. Best regards, JFArticle: 72535
In article <cgdape$jpd2@cliff.xsj.xilinx.com>, Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: >Uwe Bonnes wrote: >> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: >> ... >> : > Ok, it's the MainWin porting tool that requires the per-seat license. >> : > That's pretty much what keep Xilinx from having a set of free tools for >> : > Linux, correct? >> : > >> : Well, we don't use MainWin but, yes, that is correct. >> >> I don't understand that answer. >> >> Ise 6.2 clearly uses MainWin, or am I wrong? > >Yes, you are wrong. Xilinx does not use MainWin > Hmmmm.... What other choices still exist which require a per-seat license? PhilArticle: 72536
JF - From what I've read, board-level decoupling has a 2nd-order effect on controlling SSO noise. The problem really needs to be tackled inside the FPGA package, which is mostly out of your control. Use a device in a flip-chip package if you can. That said, proper board-level decoupling does help (follow Xilinx's guidelines), and there are other things you can do. For example, picking pin assignments to spread the drivers out on the package (you can control this unless the board has already been fabbed). And use the slowest drivers possible (not always an option). The board stackup and how the signals are routed are also important. As for the specific impact of decoupling and SSO noise, decoupling reduces the AC impedance (inductance dominates) between voltage and GND planes. Switching currents flow in a loop, and the lower the loop inductance the fewer SSO problems you'll have. Big topic, but there's a lot of information out there. Good luck. RJS "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message news:412a3f03$0$306$7a628cd7@news.club-internet.fr... > Hi, > > As I have asked in a previous post without any answer I ask it again : what > is the relationship if any between SSO and the proper decoupling of an FPGA > ? It seems there is one because the xilinx datasheet (the one I read) > indicate a maximum sso provided decoupling is perfect. > > Best regards, > > JF > >Article: 72537
SSO stands for "simultaneously switching outputs", previously also referred to as "ground bounce", and describes the effect of output switching on the chip-internal ground and Vcc distribution. Switching many outputs simultaneously generates fairly large current changes in the inductnce between the chip ground and the system ground plane, or between the chip Vcc and the Vcc poard plane. Good decoupling makes the board-Vcc distribution "stiffer", and thus makes SSO more deterministic, although not necessarily better. Peter Alfke > From: "Robert Sefton" <rsefton@abc.net> > Newsgroups: comp.arch.fpga > Date: Mon, 23 Aug 2004 13:08:38 -0700 > Subject: Re: SSO and decoupling relationship > > JF - > > From what I've read, board-level decoupling has a 2nd-order effect on > controlling SSO noise. The problem really needs to be tackled inside the > FPGA package, which is mostly out of your control. Use a device in a > flip-chip package if you can. That said, proper board-level decoupling does > help (follow Xilinx's guidelines), and there are other things you can do. > For example, picking pin assignments to spread the drivers out on the > package (you can control this unless the board has already been fabbed). And > use the slowest drivers possible (not always an option). The board stackup > and how the signals are routed are also important. > > As for the specific impact of decoupling and SSO noise, decoupling reduces > the AC impedance (inductance dominates) between voltage and GND planes. > Switching currents flow in a loop, and the lower the loop inductance the > fewer SSO problems you'll have. > > Big topic, but there's a lot of information out there. Good luck. > > RJS > > "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message > news:412a3f03$0$306$7a628cd7@news.club-internet.fr... >> Hi, >> >> As I have asked in a previous post without any answer I ask it again : > what >> is the relationship if any between SSO and the proper decoupling of an > FPGA >> ? It seems there is one because the xilinx datasheet (the one I read) >> indicate a maximum sso provided decoupling is perfect. >> >> Best regards, >> >> JF >> >> > >Article: 72538
I was wondering if those who implemented 100BaseT ports in V2 Pro would want to share their experiences? I would like to know how difficult it was overall, what unexpected obstacles you had to go through and what kind of performance in terms of sustained TCP packet rate has been achieved? Thanks, /MikhailArticle: 72539
Hi, In my design, I am using the FFT v2.1 IP core thats available in the IP Core generator that comes along with Xilinx ISE 6.2. I want to use the scaling option (SCALE_SCH). I dont know how to derive the scaling schedule. I am configuring the IP core to do 64 point FFT with 8-bit inputs. Any pointers or suggestions is highly appreciated. Thanks. Sincerely, AnandArticle: 72540
Hi, I'm looking for an inexpensive (up to $1000) development board with the following features: - Relatively fast DSP, e.g., Blackfin. - Mid-range Cyclone II or Spartan-3 FPGA. - At least 4 MB SDRAM. - Video in (CVBS and Y/C), digital video decoder. - Video out (CVBS and Y/C), digital video encoder. - The video decoder and encoder should be able to work simultaneously. A combination of boards, e.g., a DSP kit and a plug-in FPGA board can also work. Other DSPs and FPGAs than the ones mentioned above can also be considered. This is for doing research on video processing and video compression; I don't have more precise requirements yet. Thanks, -- GeorgiArticle: 72541
You should use tri-state buffers.
SRAMDQA <= SRAM DQA SIGNAL 5 when (SRAM W SIGNAL 5 = '1') else (others => 'Z');
x <= SRAMDQA;
and so on.
x -------------------------|
|
|\ |
SRAMDQASIGNAL5 -------| \__|_______________ SRAMDQA
| /
|/|
|
SRAMWSIGNAL5 -----------|
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10ikacu41g75466@corp.supernews.com>...
> What is the proper VHDL code for bidirectional pins on a Xilinx chip?
> I used the code below but the chip runs hot.
>
>
> SRAM BIDIRECTIONAL PINS:process(SRAM W SIGNAL 5,SRAM DQA SIGNAL 5,SRAM DQ
> B SIGNAL 5 )
> begin
> if(SRAM W SIGNAL 5 = '1') then
> SRAMDQA <= SRAM DQA SIGNAL 5;
> SRAMDQB <= SRAM DQB SIGNAL 5;
> else
> SRAMDQA <= (others => 'Z');
> SRAMDQB <= (others => 'Z');
> end if;
> end process;
>
> Thanks,
>
> Brad
>
> b r a d @ a i v i s i o n . c o m
> --
Article: 72542"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10i86csqd2e44d7@news.supernews.com>... > Also, do you just hit the normal "Start Compilation" button (>) or do you > use incremental route or something. I tried Signal Probe Compilation under > Processing->Start, but I haven't tried Incremental Fit. Hit the normal compilation button. Let the smart compile logic decide which compiler executables to call. SignalProbe is a different product and is used to route an internal node to a reserved pin. SignalProbe compilation is not applicble here. Incremental fit is an entirely different flow and is not applicable here. > > Do you have any tips for either finding renamed (?) post-fit signals or a > shure fire way to have a signal not optimized away? Inserting LCELL's > (graphical) and naming both the input and the output. I've also got some > AHDL and I haven't seen the equivalent of the Preserve or Keep directive. > If you don't mind, could you or someone post a snippet of AHDL placing a > signal into a named LCELL? See the code fragment below. -- This design will generate 2 LEs after synthesis due to the LCELL buffer. -- Without it, the compiler would choose to pack all the logic into one LE. SUBDESIGN an_lcell ( a,b,c : INPUT; z : OUTPUT; ) VARIABLE my_specially_named_LE : lcell ; -- Will become the output of an LCELL BEGIN my_specially_named_LE = a AND b; z = my_specially_named_LE AND c; END; This type of code is only required when one wants to view an internal combinational signal, and we recommend that users first look at the contents of registers before resorting to this technique. Registers should never be optimized away and their names should be easy to find without using an LCELL buffer. If a register that the user wants to look at has been optimized away then this is an indication that there may be an error in the user's design, as synthesis will never optimize away a register that is necessary for ciruit function. It is probably also worth pointing out that an LCELL buffer will not preserve a fanout-free signal. Hope this helps Subroto Datta Altera Corp.Article: 72543
On Mon, 23 Aug 2004 17:02:58 -0400, "MM" <mbmsv@yahoo.com> wrote: >I was wondering if those who implemented 100BaseT ports in V2 Pro would want >to share their experiences? I would like to know how difficult it was >overall, what unexpected obstacles you had to go through and what kind of >performance in terms of sustained TCP packet rate has been achieved? I once worked on a design that had sixteen 100BaseT ports in a pair of Virtex-E 2000. That used an external multiport MAC and PHY though, but did manage to achieve 100% of the theoretical maximum performance for IP. TCP performance depends a lot on latency. You should try to keep latency low. I assume that some of your protocol stack will be in software. Offload as many functions into hardware as you can, e.g. IP header checksum calculations, etc. Also, process buffers in place to avoid the overhead of copying them (or if you want to copy buffers, use hardware acceleration to do the work, e.g. DMA). Regards, AllanArticle: 72544
Synplify has two different "safe" modes. One is to prevent sequential optimizations on the state register. You do this with the syn_preserve attribute on the register (not the best name - I know). Most synthesis tools have some way to do this. The second is to let Synplify extract the state machine and to specify a syn_encoding attribute of "safe,onehot" or "safe,sequential" on the state register. In this case Synplify automatically builds an extra reset condition based on a pipelined detection of an illegal state. By separating the illegal state detection logic and giving ourselves more time to detect the illegal states we can make a more area efficient recovery circuit and a faster FSM. This feature is covered by a patent so you probably won't see it in other tools. - Ken McElvain lecroy wrote: >>This has been discussed at great length on comp.lang.vhdl: >>http://groups.google.com/groups?q=safe+state+machine+vhdl >> >>There's no simple answer. >>Consider using the binary (minimal bits) setting >>and see what you get. >> >> -- Mike Treseler > > > Mike, > > Thanks. I will read the thread. It always seems to be a problem when > I try a new tool. And your right, it is not a simple problem when the > people developing the tools have not considered the problem. I would > have thought the Quartus tool would have had this covered. I like > using the Synplify tools for this reason. > > I had reposted the question to Altera last week but have yet to hear a > responce. If anything comes of it I will post.Article: 72545
>TCP performance depends a lot on latency. Only if your buffers/windows are too small. Standard party line is that you need a window/buffer big enough to cover the round trip time. That includes both speed of light delays and processing times at both ends. http://lsr.internet2.edu/ http://news.com.com/2100-1032_3-5195614.html?part=rss&tag=feed&subj=news You need the window scale option to get interesting buffer sizes. RFC 1323 That's not to say that you shouldn't minimize latency. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72546
Hi Altera folks, What does mean "Four times the density at half the price (compared to previous-generation MAX devices)" ? For example, the EPM570 that has 440 "Typical Equivalent Macrocells". 440/4=110 Does it means it will priced at half the price of the 128 macrocell MAX? Why not, eight times the density at same price? Or just, one eighth the price? Just curious! Luiz CarlosArticle: 72547
Hi, I have a question concerning the write operation for a DDR SDRAM with a burst length of 1: If you have a look at http://mitglied.lycos.de/vazquez78 you can see the sequence of eight back-to-back write requests that go to two different rows in the DDR SDRAM device. In the shown instance (DDR SDRAM Controller MegaCore User Guide Altera) the burst length is one on the Controller Local Interface and two on the Memory Side. My question: Why do the addresses on the local interface "local_col_addr" "020","021","022","023","030","031","032","033" turn to the memory addresses "0040","0042","0044","0046","0060","0062","0064","0066" on the DDR SDRAM Interface ? It is said later in the User Guide that the controller runs the DQ port to the DDR devices at one half the width and twice the rate of the DATAIN port (input data at the local interface of the controller). But how are the coherence with the shown example addresses? Thank you in advance. Rgds AndréArticle: 72548
Hi, I read in a previous post the following by M. Lesea : "All design (SSO tables, DCM operation, system jitter, etc) assumes that the ground bounce stays below +/- 100 mV peak to peak for proper operation." Where is this information located in the datasheet ? Thanks, JFArticle: 72549
Hi, Does anyone know if it's possible to run the Xilinx ISE 4.2i software in Linux? I would like to develop VHDL code and then program my FPGA (I use a parallel port JTAG programmer). Being able to do this from Linux would make the project easier as I need to develop a Linux device driver at the same time. I was thinking I could use WINE. Do any websites with instructions exist? Thanks.
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