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I am trying to access the board SDRAM. I should be meeting the timing of the ram, at least according to the documentation of the sdram controller and the documentation of the ram. I have the MJL Cyclone dev kit (www.mjl.com), with 8 MB Micron SDRAM On Wed, 18 Aug 2004 16:49:05 -0400, "kattice" <kattice@hotmail.com> wrote: >Are you trying to access on board SDRAM? Do you know whether you meet your >timing for SDRAM? Most of time, that is the case unless your code is >wrong. I also have NIOS I Cyclone Dev. board, but didn't get a chance to >play with it. Which board do you have? > >KevinArticle: 72451
Hi all,
in order to comply with the timing requirements,
I did explicitly replicate an output register.
-- Code Snip Below
I2 : a_reg
generic map (
n => 20
)
port map (
clk => clk,
din => addro_i,
rst => rst,
dout => addr_a_out);
I3 : a_reg
generic map (
n => 20
)
port map (
clk => clk,
din => addro_i,
rst => rst,
dout => addr_b_out);
Register instances are sourced from the very same signal.
However synthesis tries to be 'clever' and removes one
register instance, making it impossible to have them in the
IOB section. Any advice how I can avoid this removal without
going 'to-deep' and instantiate IOB-Register Primitives as
'Black-Box-Instances'.
Thank's
Markus
Article: 72452"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0408181657.4384520b@posting.google.com... > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:<cfptk6$n4e$1@news.netpower.no>... > > I'm working with a NIOS II cpu on an Altera Stratix chip. I'm finding it > > easy enough to make simple Avalon slave devices, using the "interface to > > user logic" wizard to connect my components to the bus. But I can't find > > any way to deal with memory devices that would logically connect to tristate > > buses. I have a couple of synchronous ram devices which should be simple > > enough to use (I can access them using a test module I made outside the > > NIOS). Is there any simple way of connecting new devices to a tristate bus, > > or any application notes that show how? > > > > Thanks, > > Hi David, > > On this: The trick is in the IO signal type (Input,Output,Inout) in > the interface to user logic. If you specify your data bus as > bi-directional, your peripheral will sprout a tri-state bus, and > require an Avalon Tri-State bridge to master it. > > The next thing is "what about multiple devices on the tri-state bus" - > the interface to user logic handles this as well. The trick is to > specify which signals are "shared". Anything not "shared" will have a > unique pin in the collection of pins on the tri-state bus (this is > useful for sharing an IO for read/write/byte enables). > > The Avalon Bus Spec reference manual should discuss this a bit as > well. > I've figured it out now, and got my devices working perfectly. The process was not too hard - all I needed was to write a class.ptf file for each type of device, and get the signals and timing parameters specified correctly. All in all, I needed to write about 100 lines of text class.ptf file. However, to get that I had to read hundreds of pages of documentation in the Avalon Bus Spec and the SOPC references, as the information is pretty scattered. For the sake of others who face the same situation, could you suggest to the powers that be that they a) update these manuals to refer to the Nios II (I know not much has changed in the bus, but it'd be nice to be told that in the manual), b) put links to these manuals in the Nios II literature section as well as the Nios section, c) write a 10-page application note covering connection of external memory to tristate buses, to save lots of reading and collection of information, d) write a nice wizard, like the "interface to user logic" and "flash" wizards, making it easy to see the timing. Having figured out all the required signals and timing settings, the system worked great - I added the memory components, re-generated the design, and it worked first time. But a bit more directed information would have made the process much easier. David > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 72453
there are several ways... but it depends on your tool chain.... VHDL "supports" attributes to loc various things you might have to use a mixture of 'keep' to stop nets getting optimised away and 'iob' constraints to force the flip flop into an io block. I don't think that XST supports 'keep' constraints... but other tools do. You will need to look up the documentation to find how to use them Simon "Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:aaaee51b.0408190021.9fe7363@posting.google.com... > Hi all, > > in order to comply with the timing requirements, > I did explicitly replicate an output register. > > -- Code Snip Below > > I2 : a_reg > generic map ( > n => 20 > ) > port map ( > clk => clk, > din => addro_i, > rst => rst, > dout => addr_a_out); > > I3 : a_reg > generic map ( > n => 20 > ) > port map ( > clk => clk, > din => addro_i, > rst => rst, > dout => addr_b_out); > > Register instances are sourced from the very same signal. > However synthesis tries to be 'clever' and removes one > register instance, making it impossible to have them in the > IOB section. Any advice how I can avoid this removal without > going 'to-deep' and instantiate IOB-Register Primitives as > 'Black-Box-Instances'. > > Thank's > > MarkusArticle: 72454
Hi, "Dalton Marris" <dmarris@charter.net> wrote in message news:10i7eeieh5tg452@corp.supernews.com... > Well, I'm learning more as I go... It seems that you have to > compile the design before you can use the Node Finder. So I > added an LCELL between the multiplier and the ram, and named > it mult_out. I can then add mult_out to my .vwf file and it > appears as it should in the output vectors, with the correct > waveforms. > > Now if I can get the LCELL automagically stripped out when I > create the actual device... In my Quartus II ver. 4.0 Settings > Analysis & Synthesis > More Analysis & Synthesis Settings > Ignore LCELL Buffers set this to On (Default is off) and recompile.. If i remember correctly you will get a warning message that it synthesised them away.. > > Dalton Marris wrote: > > > I am trying to perform a functional simulation of a circuit > > which contains a multiplier (LPM_MULT) feeding into a ram > > cell (VHDL code). Using the Node Finder, I have added the > > output of the multiplier "mult:inst|result" to my .vwf file, > > but I get the following warning message when I simulate: > > > > Warning: Can't find node mult:inst|result[0] for functional > > simulation. Ignored vector source file node. > > > > I have read the question posed by Christos (10/9/2003), and > > responded to by Subroto Datta (10/9/2003). > > > > Since I am performing a functional simulation, and the Node > > Finder can find the node of interest: > > > > (1) Should the LCELL still be necessary? > > > > (2) Why can't the node be found, is it stripped out when I > > run the "Generate Functional Simulation Netlist" tool? > > > > Regards, > > Dalton Good luck, Christos ** christos zamantzas at cern dot ch **Article: 72455
Hi, somebody can tell me how can I make a counter (that count 1,6ms
and other that count microseconds) I make it:
static macro proc espera2 (time)
{
unsigned 64 i;
for (i=0; i<(time/1000000)*80000000;i++)
delay;
} // wait miliseconds
static macro proc espera (time)
{
unsigned 64 i;
for (i=0; i<(time/1000)*80000000;i++)
delay;
} // wait microseconds
but don't do it well. The clock is 80MHz.
Thats
Article: 72456Andrew Rogers wrote: > Sidney Cadot wrote: > >> Andrew Rogers wrote: >> >>> The flash PROM can now also be programmed using xc3sprog. It has >>> taken a lot of experimenting to get the PROM programming to work. >>> Xilinx has not released details of the programming algorithm for >>> these devices in its datasheets. This means that I cannot be sure >>> that the delays used are correct. Also verification is not performed. >>> >>> Negatives aside, this program has sucessfully programmed the Flash >>> PROM on the $99 Spartan3 Starter Kit. >>> >>> http://www.rogerstech.co.uk/xc3sprog/ >> >> >> >> Great work Andrew. >> >> It seems we've been doing similar things over the last couple of days. >> I like your code and the SVF route may be the better way to go in the >> long run, as pointed out by Mr. Jacobson. >> >> I'll put my activities on hold for now and put a link on my web-page >> to yours. >> >> Regards, Sidney >> > > I had considered the SVF route. The problem is that the SVF player > cannot give meaningful error messages, the SVF player is not aware of > the task in hand. SVF can only report a mismatch between what was read > on the TDO and what it was told to expect. > > http://www.asset-intertech.com/support/svf.pdf > > I have just updated my webpage, adding a link to yours. > > Regards > Andrew > I think that would be nice to support SVF too. So that when a new device appears, we can program it ;) SylvainArticle: 72457
Christos wrote:
> Hi,
>
> "Dalton Marris" <dmarris@charter.net> wrote in message
> news:10i7eeieh5tg452@corp.supernews.com...
>
>>Well, I'm learning more as I go... It seems that you have to
>>compile the design before you can use the Node Finder. So I
>>added an LCELL between the multiplier and the ram, and named
>>it mult_out. I can then add mult_out to my .vwf file and it
>>appears as it should in the output vectors, with the correct
>>waveforms.
>>
>>Now if I can get the LCELL automagically stripped out when I
>>create the actual device...
>
>
> In my Quartus II ver. 4.0
>
> Settings > Analysis & Synthesis > More Analysis & Synthesis Settings >
> Ignore LCELL Buffers
> set this to On (Default is off) and recompile..
> If i remember correctly you will get a warning message that it synthesised
> them away..
>
Very good, found it in Quartus II ver. 4.1:
Assignments > Settings > Analysis & Synthesis Settings > More Settings >
Ignore LCELL Buffers
("More Settings" is a button which opens the "More Analysis & Synthesis
Settings" form.)
Now for some more reading and testing...
Thanks!
>
>>Dalton Marris wrote:
>>
>>
>>>I am trying to perform a functional simulation of a circuit
>>>which contains a multiplier (LPM_MULT) feeding into a ram
>>>cell (VHDL code). Using the Node Finder, I have added the
>>>output of the multiplier "mult:inst|result" to my .vwf file,
>>>but I get the following warning message when I simulate:
>>>
>>>Warning: Can't find node mult:inst|result[0] for functional
>>>simulation. Ignored vector source file node.
>>>
>>>I have read the question posed by Christos (10/9/2003), and
>>>responded to by Subroto Datta (10/9/2003).
>>>
>>>Since I am performing a functional simulation, and the Node
>>>Finder can find the node of interest:
>>>
>>>(1) Should the LCELL still be necessary?
>>>
>>>(2) Why can't the node be found, is it stripped out when I
>>>run the "Generate Functional Simulation Netlist" tool?
>>>
>>>Regards,
>>>Dalton
>
>
>
> Good luck,
>
> Christos
>
> ** christos zamantzas at cern dot ch **
Article: 72458
etvive@wanadoo.es wrote:
> Hi, somebody can tell me how can I make a counter (that count 1,6ms
> and other that count microseconds) I make it:
>
> static macro proc espera2 (time)
> {
> unsigned 64 i;
>
> for (i=0; i<(time/1000000)*80000000;i++)
> delay;
>
> } // wait miliseconds
>
>
> static macro proc espera (time)
> {
> unsigned 64 i;
>
> for (i=0; i<(time/1000)*80000000;i++)
> delay;
> } // wait microseconds
>
> but don't do it well. The clock is 80MHz.
I can't figure out if this could be homework or not, but I will say that
milliseconds are normally larger than microseconds, not smaller.
Marc
Article: 72459Hello, I have developped a System on chip with the EDk tool. I'm developping a V2P with ISE in with I have to use my SOC. I have linked the EDK project in my main ISE project and I can make changes to it. Under ISE I am able to launch top level simulations in modelsim, in order to validate some PPC test routines written in C. It works fine. Synthesis of the ISE project works too. But when I launch implementation in ISE, the ngdbuild step makes : - readings of design - checks timing specification And then it starts processing bmm file, in which I get errors : ERROR:NgdBuild:704 - The BRAM instance 'socinst/bram/bram/ramb16_s1_s1_0' could not be found in the netlist. Please verify the instance name in the BMM file and the netlist. I get 64 of them, as my Bram is made of 64 ramb16_s1_s1. I've turned the problem in every way an I can't get the solution. If someone has information to solve this problem. Thank you. Stephane.Article: 72460
Hi, I don't know what Mr. Brookes method is, since it was not posted here. Perhaps he (or you) tried to email me a copy, but failed to notice the "no spam" addition to my news-posting address. However, just at the moment I have a far bigger problem that is stopping me doing any debugging at all - nios2-gdb-server is now refusing to connect to my Nios2 jtag port. I have tried all sorts of things, including rebuilding a new (fairly minimal) nios2 design on my board, with no luck. The last thing I did was take a test project I made on my original Nios Cyclone development kit and replace the Nios 1 with a Nios 2, and I still can't get any contact. This is hardware that I know without doubt is working fine - I can download designs with the jtag interface (ByteBlaster II), and can connect gdb to the Nios 1 design. But I can no longer contact a Nios 2 for debugging over the jtag interface. When I run "nios2-gdb-server --verbosity=4" and try to connect to it with nios2-elf-gdb, I get the information: # [nios2-gdb-server] g_verbosity: 4 # [nios2-gdb-server] nios2-gdb-server listening on port 2342 # [nios2-gdb-server] accepting gdb connection # [nios2-gdb-server] connecting to JTAG debug module # [nios2-gdb-server] CPU will be reset on connect # [nios2-gdb-server] JTAG cable: "" # [nios2-gdb-server] JTAG device: -1 # [nios2-gdb-server] JTAG debug module instance: -1 # [nios2-gdb-server] using MDI port: "sld" # [nios2-gdb-server] MDI error FindAndOpenNode Lock Chain: AJI_BAD_HARDWARE. -105 (nios2-gdb-server_mdi.c line 161) # [nios2-gdb-server] failed to connect Similarly, the IDE debug setup finds my ByteBlasterII on lpt1, but reports <no devices connected> for the jtag device. I had this same effect when I first used the Nios 2, with the ByteBlaster II connected to lpt2. This worked fine for the Nios, and for downloading fpga designs, but the Nios2 debugger could not see the Nios 2. Switching to lpt1 fixed that. I was not too surprised with that, since I have had little luck getting my lpt2 card to work with other jtag-type debuggers - in fact, I was very surprised when it *did* work with the Nios 1. I've now tried everything I can think of, so if anyone else has any bright ideas for me, I'd be very grateful! David "Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0408181242.3398fe9e@posting.google.com... > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:<cfv864$qi8$1@news.netpower.no>... > > I'm working with a Nios II processor on an Altera fpga. Mostly, I'm doing > > fine, but there is one feature of the Eclipse interface to gdb that I seem > > to be missing - a gdb command window. There is a "nios2-gdb-server output" > > option for the Console window, but that's for output only. I want to be > > able to type my own commands. When using other gui front-ends for gdb, > > including gvd, insight and ddd, there is no problem doing this, but I can't > > find any way to get it in Eclipse. > > > > If I can't get this working, does anyone know of information about using gdb > > directly from the command line on the Nios2, such as references for the > > nios2-gdb-server parameters? > > Hi David (and other readers), > > Please disregard the 2nd to last paragraph in my reply to your > question; I did not intend to post that, but pressed the button too > soon! Quite obviously there is a method from the IDE (Mr. Brookes > provided it). > > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 72461
Just thought I would post the remainder of the conversation. Hope it helps some of you. Also, if anyone has the orignal documents that call out the 10% matching, could you pass this on to Steve or post it. Most recent first. > Steve, > > > Was the 10% matching based on the 300 mV numbers? > > I'm not sure from where that value originated. > > Prior to the S3 being released I saw a presentation on it. The 10% caught my attention. I asked for a copy of the slides but they would not release them. Later I found this same specification called out in one of the application notes. I did a quick search, but it appears Xilinx has changed many of these documents several times over from that time and there is no mention of the matching. On the plus side, I think I may have kept my orignal copies at home. I will see if I can dig them up and pass them onto you. Ahhh, that could be. The official Xilinx word on I/O robustness, I think, was overly conservative until the actual process qualification was complete. Some of the early values were indeed extremely limiting. I'd still be interested if you come across those documents, just to make sure we purge the old data. Thanks. Hi Anonymous, Question: Do you happen to go by another name? Why the anonymity? I promise, I don't bite. :-) > From the thread: > > "Steve, From the document you will notice that the concern is with matching inputs. They are asking for an impedance match of less than 10%. My question is about the reflected energy from a driver to a poorly terminated load. So, if we look at the incident versus reflected energy and tune the stub (trace) for a worst case match is it possible the driver could be damaged or the chip lock up due to the reflected energy?" > > > > That 10% could easily be eaten up by the layout, PCB processing or simulation. So, while your simulation may be showing you one thing, to meet this 10% is going to take a "real" board and a VNA to verify. If we have a mismatch of say 12%, how does that effect the life of the part? What drove the designers to 10% limit? Sorry, I've been reading through the volumous thread. I did note that the thread has some old information. Back when the question was asked, we hadn't yet completed all our process qualification steps and the engineers asked us to keep the input voltage to 3.75V or less, with total overshoot of +/-300 mV. This has since been relaxed to +/-500 mV, with an absolute maximum voltage of 4.05V. Was the 10% matching based on the 300 mV numbers? I'm not sure from where that value originated. In the diagram that I sent, there is a small amount of time where the voltage on the input exceeds 4.05V. Above this voltage, there is the possibility of a long-term wear out mechanism called Time Dependent Dielectric Breakdown (TDDB). Voltages above 4.05V will not immediately cause the device to fail and it will not cause the chip to lock up. Essentially, you will see the output leak more and more current until it eventually fails. The time to failure depends on the magnitude of the overvoltage and the duration. Does this help at all with your original question? Is there additional information that you would like. --------------------------------- Hi Anonymous and Hal, > The last comment from Xilinx was "Going back to your original question, the answer back from the factory is at > 3.3 V signaling, it is possible to have reflections damage the part.". This was followed by several posts about the importance of simulation. Based on your initial question, I tried a few simulations using some pathological conditions and, yes, it is possible to exceed the Absolute Maximum Ratings listed in the data sheet. For example, if you use the biggest, fastest output available (LVCMOS_FAST_24mA), operate it at maximum voltage (VCCO=3.45V), run it down a long trace (100 cm), simulate it under worst-case conditions, to an high-impedance load, you can exceed 4.05V absolute maximum rating at the Spartan-3 FPGA output for about 1 ns. Add a 33 ohm source termination resistor or reduce the trace length to 15 cm and you easily fall within the recommended VCCO+/-0.5V range. Similar effects are possible using a different I/O standard. I purposely picked the biggest current drive output with the fastest switching edges and used the Fast-Strong simulation model (worst-case to generate maximum overshoot/undershoot). In every PCB simulation that I've done so far, and certainly the scope shots from actual silicon, look better than this. IBIS provides an excellent first-order approximation of the actual results. However, this simple analysis isn't modeling packaging loads, etc. Attached is a PDF showing the results. I also checked with Xilinx design engineering. Before device qualification was complete, they wanted to limit the recommended maximum voltage on the inputs to no more than 3.75V (VCCO+0.3V). This has since been relaxed to VCCO+0.5V, or 3.95V. Please let me know if this answers your question or not.Article: 72462
go to google.com and enter: BIST Xilinx and you will find over 2000 hits. Have fun! Peter Alfke > From: Austin Lesea <austin@xilinx.com> > Organization: Xilinx,Inc > Newsgroups: comp.arch.fpga > Date: Wed, 18 Aug 2004 09:38:05 -0700 > Subject: Re: Regarding BIST in FPGA > > Varun, > > Search the USPTO for our patents on BIST in PLD. > > Austin > > Varun Jindal wrote: >> Hello , >> >> I am an engineering student and am working on testability issues in >> FPGA devices. Can anybody throw light on the BIST schemes used by >> Xilinx in their devices ; i.e. how do they achieve 100% fault >> coverage;whether they use soft BIST or hard BIST. Any information will >> be appreciated. Thanks in advance. >> >> Regds. >> VarunArticle: 72463
I tried to contact Altera's upport on Safe FSMs and had to explain what can cause a FSM to get lost and about recovery. We even talked a bit about how some of the other tools like Synplicity handle this. This was Altera's responce: >Description: want to code a state machine and if it goes into an undefined >state, what does he need to code to reset the state machine >Unfotunately, it is not our duty to tell you or teach you how to code in vhdl. >However, there are guidlines and references that you may refer to from our web >site and in the Quartus II Help. To do so, you may simply do a search on our >site or use the key phrase "state machine" in the Quartus II Help. > >Regards, What is interesting is that they never mention "Safe" in the orignal question. I had spent a lot of time looking for the information on their site but turned up nothing. With Altera's support once again being a dead end, does anyone know if there is a switch for this in Quartus, like Synplify and other tools? If not, has anyone dug into what it takes to make the tools create the added logic? I wonder if using the "minimal" gate feature and define a 2^nth FSM, then encode all of the states if it would optimize out states that have no entry point or not. Maybe there is a switch for the optimizer as well? I don't want to waste a lot of time trying things to find a method that works.Article: 72464
?, Is there a question here that I could answer for someone? It is unclear what is being asked. DCI accuracy? IO SI issues with 3.3V and the 4.05 V abs max specification? What happens if the IO spends time at and beyond the 4.05V gate stress abs max limits? I can answer any, or all if anyone wants to know. The answers will also apply to VII Pro, Pro-X, S3, and V4 (as they all use 0.25u IO transistors). Austin lecroy wrote: > Just thought I would post the remainder of the conversation. Hope it > helps some of you. Also, if anyone has the orignal documents that > call out the 10% matching, could you pass this on to Steve or post it. > > > Most recent first. > > > >>Steve, >> >> >>>Was the 10% matching based on the 300 mV numbers? >>>I'm not sure from where that value originated. >> >>Prior to the S3 being released I saw a presentation on it. The 10% > > caught my attention. I asked for a copy of the slides but they would > not release them. Later I found this same specification called out in > one of the application notes. I did a quick search, but it appears > Xilinx has changed many of these documents several times over from > that > time and there is no mention of the matching. On the plus side, I > think I may have kept my orignal copies at home. I will see if I can > dig them up and pass them onto you. > > Ahhh, that could be. The official Xilinx word on I/O robustness, I > think, was overly conservative until the actual process qualification > was complete. Some of the early values were indeed extremely > limiting. > > I'd still be interested if you come across those documents, just to > make > sure we purge the old data. > > Thanks. > > > > Hi Anonymous, > > Question: Do you happen to go by another name? Why the anonymity? I > promise, I don't bite. :-) > > >>From the thread: >> >>"Steve, From the document you will notice that the concern is with > > matching inputs. They are asking for an impedance match of less than > 10%. My question is about the reflected energy from a driver to a > poorly terminated load. So, if we look at the incident versus > reflected > energy and tune the stub (trace) for a worst case match is it possible > the driver could be damaged or the chip lock up due to the reflected > energy?" > >> >> >>That 10% could easily be eaten up by the layout, PCB processing or > > simulation. So, while your simulation may be showing you one thing, > to > meet this 10% is going to take a "real" board and a VNA to verify. If > we have a mismatch of say 12%, how does that effect the life of the > part? What drove the designers to 10% limit? > > Sorry, I've been reading through the volumous thread. I did note that > the thread has some old information. Back when the question was > asked, > we hadn't yet completed all our process qualification steps and the > engineers asked us to keep the input voltage to 3.75V or less, with > total overshoot of +/-300 mV. This has since been relaxed to +/-500 > mV, > with an absolute maximum voltage of 4.05V. > > Was the 10% matching based on the 300 mV numbers? I'm not sure from > where that value originated. > > In the diagram that I sent, there is a small amount of time where the > voltage on the input exceeds 4.05V. Above this voltage, there is the > possibility of a long-term wear out mechanism called Time Dependent > Dielectric Breakdown (TDDB). Voltages above 4.05V will not > immediately > cause the device to fail and it will not cause the chip to lock up. > Essentially, you will see the output leak more and more current until > it > eventually fails. The time to failure depends on the magnitude of the > overvoltage and the duration. > > Does this help at all with your original question? Is there > additional > information that you would like. > --------------------------------- > > > Hi Anonymous and Hal, > > >>The last comment from Xilinx was "Going back to your original > > question, the answer back from the factory is at > >>3.3 V signaling, it is possible to have reflections damage the part.". > > This was followed by several posts about the importance of simulation. > > > > > Based on your initial question, I tried a few simulations using some > pathological conditions and, yes, it is possible to exceed the > Absolute > Maximum Ratings listed in the data sheet. For example, if you use the > biggest, fastest output available (LVCMOS_FAST_24mA), operate it at > maximum voltage (VCCO=3.45V), run it down a long trace (100 cm), > simulate it under worst-case conditions, to an high-impedance load, > you > can exceed 4.05V absolute maximum rating at the Spartan-3 FPGA output > for about 1 ns. Add a 33 ohm source termination resistor or reduce > the > trace length to 15 cm and you easily fall within the recommended > VCCO+/-0.5V range. Similar effects are possible using a different I/O > standard. I purposely picked the biggest current drive output with > the > fastest switching edges and used the Fast-Strong simulation model > (worst-case to generate maximum overshoot/undershoot). > > In every PCB simulation that I've done so far, and certainly the scope > shots from actual silicon, look better than this. IBIS provides an > excellent first-order approximation of the actual results. However, > this simple analysis isn't modeling packaging loads, etc. > > Attached is a PDF showing the results. > > I also checked with Xilinx design engineering. Before device > qualification was complete, they wanted to limit the recommended > maximum > voltage on the inputs to no more than 3.75V (VCCO+0.3V). This has > since > been relaxed to VCCO+0.5V, or 3.95V. > > Please let me know if this answers your question or not.Article: 72465
Phil Tomson wrote:
> In article <cg0l1u$jp22@cliff.xsj.xilinx.com>,
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote:
>
>>To clear the record, Jungo does not charge a per-seat fee and was not
>>the reason that a Linux-based WebPack was absent. The specific issue
>>was the per-seat license fee associated with Xilinx's GUI development
>>tool kit.
>>
>>You may now return to your soapbox...
>>
>
>
> Ok, it's the MainWin porting tool that requires the per-seat license.
> That's pretty much what keep Xilinx from having a set of free tools for
> Linux, correct?
>
Well, we don't use MainWin but, yes, that is correct.
> BTW: I'm a customer. Just trying to help you guys out ;-)
>
> Phil
--
You've *read the email* - now *buy the book*
Article: 72466> I've figured it out now, and got my devices working perfectly. The process > was not too hard - all I needed was to write a class.ptf file for each type > of device, and get the signals and timing parameters specified correctly. > All in all, I needed to write about 100 lines of text class.ptf file. > However, to get that I had to read hundreds of pages of documentation in the > Avalon Bus Spec and the SOPC references, as the information is pretty > scattered. For the sake of others who face the same situation, could you > suggest to the powers that be that they > > a) update these manuals to refer to the Nios II (I know not much has changed > in the bus, but it'd be nice to be told that in the manual), > > b) put links to these manuals in the Nios II literature section as well as > the Nios section, > > c) write a 10-page application note covering connection of external memory > to tristate buses, to save lots of reading and collection of information, > > d) write a nice wizard, like the "interface to user logic" and "flash" > wizards, making it easy to see the timing. > > > Having figured out all the required signals and timing settings, the system > worked great - I added the memory components, re-generated the design, and > it worked first time. But a bit more directed information would have made > the process much easier. > > David > Thanks I will pass this on to the relevant people on the engr & doc team for SOPC Builder. Work is already being done for a future release on enhancing this functionality for more complex systems, but I am surprised to hear that you had to write a PTF file for an off-chip memory interface (the wizard in its current state should handle such a thing) - you're right that better docs are in order for this. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 72467
SVF is "Serial Vector Format" and is the de facto standard that
describes that data transmitted to and received from the boundary-scan
(1149.1, JTAG) Test Access Port (TAP). It was developed by TI and
Teradyne but is now administered by Asset Intertech. More details are
available on their web site
(http://www.asset-intertech.com/support/svf.pdf). You can think of the
SVF file as assembly language for TAP transactions. It already includes
the data to shifted into the device and the necessary TAP transitions.
An alternative approach is based on IEEE Std 1532 which requires BSDL
files and programming data files (which therefore separate data from
algorithm). The free and open source code for this is called JDrive and
is available from Xilinx's web site as XAPP 500
(http://www.xilinx.com/bvdocs/appnotes/xapp500.pdf) and its associated
files.
Phil Tomson wrote:
> In article <cg0ldg$jp01@cliff.xsj.xilinx.com>,
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote:
>
>>I hate to say this but you probably could have better spent your time
>>developing a SVF file interpreter that runs on Linux that way you could
>>use the SVF files generated from iMPACT which already contain a full
>>implementation of the configuration algorithm and as updated as the
>>algorithms improve. Alternatively, you could take the JDrive [open and
>>free] source code (http://www.xilinx.com/bvdocs/appnotes/xapp500.pdf)
>>and compile it on Linux (as some already have) to also have an
>>up-to-date, all device configuration solution.
>>
>
>
> Not having been in the FPGA world for several years (but getting back in
> as a hobbyist)... What's an SVF file? Even if we had an interpreter for
> SVF files, how would that help us get the bits into the FPGA? Seems like
> we still need something like JOLT (the physical layer) to actually get the
> bits there.
>
> Phil
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You've *read the email* - now *buy the book*
Article: 72468In article <4123eb30$1_1@127.0.0.1>, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >Sidney Cadot wrote: >> Andrew Rogers wrote: >> >>> The flash PROM can now also be programmed using xc3sprog. It has taken >>> a lot of experimenting to get the PROM programming to work. Xilinx has >>> not released details of the programming algorithm for these devices in >>> its datasheets. This means that I cannot be sure that the delays used >>> are correct. Also verification is not performed. >>> >>> Negatives aside, this program has sucessfully programmed the Flash >>> PROM on the $99 Spartan3 Starter Kit. >>> >>> http://www.rogerstech.co.uk/xc3sprog/ >> >> >> Great work Andrew. >> >> It seems we've been doing similar things over the last couple of days. I >> like your code and the SVF route may be the better way to go in the long >> run, as pointed out by Mr. Jacobson. >> >> I'll put my activities on hold for now and put a link on my web-page to >> yours. >> >> Regards, Sidney >> > >I had considered the SVF route. The problem is that the SVF player >cannot give meaningful error messages, the SVF player is not aware of >the task in hand. SVF can only report a mismatch between what was read >on the TDO and what it was told to expect. > >http://www.asset-intertech.com/support/svf.pdf > >I have just updated my webpage, adding a link to yours. > Just had a look at the SVF spec you linked. I found a link to an open source project that claims to have created an SVF parser/interpreter: http://ebsp.sourceforge.net/ So looks like that part is already done for us. PhilArticle: 72469
On Wed, 18 Aug 2004 16:43:35 -0700, Neil Glenn Jacobson wrote: > The short answer that avoids almost all the specific issues you raise is > that we are moving away from a GUI toolkit that is encumbered with a > per-seat license fee. This is good news, hopefully the new GUI tool kit will be X windows friendly. The current toolkit is awful, FPGA Editor (which is the only GUI tool I ever use) is unusable over a network. Cadence and Mentor tools both work seemlessly over a network, there is hardly any performance difference between running them on a your workstation and running them on your server. The Cadence and Mentor tools are also distribution agnostic, I've had no problem running them on any platform even an Athlon64 running the 64 bit version of Mandrake 10.0. The Xilinx GUI tools won't run on Mandrake 10.0 in either the 32 bit or 64 bit incarnations. I have to keep my workstation at 9.2 so I have something that can run FPGAeditor. The basic tools, xst, map, par, etc, all work fine of course because they are CLI based and have no library dependencies. In 7.1 Xilinx should statically link every thing so that these stupid dependencies go away.Article: 72470
In message <65e317a4.0408190207.57c5db47@posting.google.com>,
etvive@wanadoo.es writes
>Hi, somebody can tell me how can I make a counter (that count 1,6ms
>and other that count microseconds) I make it:
>
>static macro proc espera2 (time)
>{
> unsigned 64 i;
>
> for (i=0; i<(time/1000000)*80000000;i++)
> delay;
>
>} // wait miliseconds
-- 8< - snip - 8< --
Try re-arranging the _integer_ division and multiplication.
e.g. for a wait of 5 us
(5 / 1000000) = 0
(5 / 1000000) * 80000000 = 0
5 * (80000000 / 1000000) = 400
Rich
Article: 72471
"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<cg2eqt$s7v$1@news.netpower.no>...
> Hi,
>
> I don't know what Mr. Brookes method is, since it was not posted here.
> Perhaps he (or you) tried to email me a copy, but failed to notice the "no
> spam" addition to my news-posting address.
>
> However, just at the moment I have a far bigger problem that is stopping me
> doing any debugging at all - nios2-gdb-server is now refusing to connect to
> my Nios2 jtag port. I have tried all sorts of things, including rebuilding
> a new (fairly minimal) nios2 design on my board, with no luck. The last
> thing I did was take a test project I made on my original Nios Cyclone
> development kit and replace the Nios 1 with a Nios 2, and I still can't get
> any contact. This is hardware that I know without doubt is working fine - I
> can download designs with the jtag interface (ByteBlaster II), and can
> connect gdb to the Nios 1 design. But I can no longer contact a Nios 2 for
> debugging over the jtag interface. When I run
> "nios2-gdb-server --verbosity=4" and try to connect to it with
> nios2-elf-gdb, I get the information:
>
> # [nios2-gdb-server] g_verbosity: 4
> # [nios2-gdb-server] nios2-gdb-server listening on port 2342
> # [nios2-gdb-server] accepting gdb connection
> # [nios2-gdb-server] connecting to JTAG debug module
> # [nios2-gdb-server] CPU will be reset on connect
> # [nios2-gdb-server] JTAG cable: ""
> # [nios2-gdb-server] JTAG device: -1
> # [nios2-gdb-server] JTAG debug module instance: -1
> # [nios2-gdb-server] using MDI port: "sld"
> # [nios2-gdb-server] MDI error FindAndOpenNode Lock Chain:
> AJI_BAD_HARDWARE. -105 (nios2-gdb-server_mdi.c line 161)
> # [nios2-gdb-server] failed to connect
>
> Similarly, the IDE debug setup finds my ByteBlasterII on lpt1, but reports
> <no devices connected> for the jtag device. I had this same effect when I
> first used the Nios 2, with the ByteBlaster II connected to lpt2. This
> worked fine for the Nios, and for downloading fpga designs, but the Nios2
> debugger could not see the Nios 2. Switching to lpt1 fixed that. I was not
> too surprised with that, since I have had little luck getting my lpt2 card
> to work with other jtag-type debuggers - in fact, I was very surprised when
> it *did* work with the Nios 1.
>
> I've now tried everything I can think of, so if anyone else has any bright
> ideas for me, I'd be very grateful!
>
> David
Hi David,
Sorry, the reference to that gentleman was only in the context of
talking to GDB directly from within the IDE as you had originally
inquired about - I posted that information during the first reply (I
just forgot to remove some of the email chain that wasn't relevant to
your question).
About your problem: Can you download/debug a hello-world type
application without doing the gdb commands manually? This would be a
good starting point. One thing I noticed from the error message dump
is that there is no JTAG cable ("") -- you might try the following:
Make a new "run" or "debug" target in the IDE (this is covered in the
Nios II SW dev tutorial in the IDE on-line help), and in the 'Run'
screen go to 'Target Connection' and manually pick the programming
cable you're using from the drop-down, and if necessary the device in
the JTAG chain (if there are multiple devices). Here you can also
'Refresh' the lists to see that things are being detected properly.
This is necessary more often than not if you have two programming
cables installed (and it sounds like you might, one in lpt1, and one
in lpt2).
FYI, the "list" of programming cables comes from Quartus (what ever
programming cables the Quartus programmer sees, the IDE will have
access to).
If the above doesn't help I'd suggest that you contact your FAE or
Altera support team for some one-on-one help on the issue.
Jesse Kempa
Altera Corp.
jkempa at altera dot com
Article: 72472Hello. I know this has been asked a zillion times before, but I want to know if it is currently possible to initialize inferred Block RAM using Verilog in XST, like it is possible to do using VHDL. Else, are there plans to include this feature anytime soon? Best regards. -- /"However, what if it does matter, and we are PabloBleyerKocik / missing something fundamental that could pbleyer2004 / change the way we see the world?" @embedded.cl / -- One Little Wrong Assumption, Darren AshbyArticle: 72473
I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems to take a lot more CPU time with a NIOS II. Has anyone else experienced this? ARRRRRGGGGGHHHHH JerArticle: 72474
On Thu, 19 Aug 2004 17:39:55 -0400, "B. Joshua Rosen" <bjrosen@polybus.com> wrote: >On Wed, 18 Aug 2004 16:43:35 -0700, Neil Glenn Jacobson wrote: > >> The short answer that avoids almost all the specific issues you raise is >> that we are moving away from a GUI toolkit that is encumbered with a >> per-seat license fee. > >This is good news, hopefully the new GUI tool kit will be X windows >friendly. The current toolkit is awful, FPGA Editor (which is the only GUI >tool I ever use) is unusable over a network. FPGA Editor is also the only GUI tool I use. I use it over a network quite successfully, using TightVNC, since my desktop machine is too small and slow to run FPGA Editor itself. What makes you say it's unusable? Regards, Allan.
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