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Frank Benoit wrote: > Thanks for your answer > > I think I tried it like that too. But I will try it again tomorrow in > office. > > I spent 2 days with that problem. And then on my other office > where I have a BaseX it worked. What a shock. > So, I think the problem is in the webpack, not in the code? > But I need it working on the place with the ISE webpack. > > Frank XST in the WebPack is the same as XST in Base-X to my knowledge. If you have the same versions including service pack, I can not think of any reason why the two would act differently in this respect. I have seen a few strange things in the past like a hidden control character in the code or left over "garbage" from a previous run in the working directory cause situations like this. You might want to take another look at the code and/or try creating a new project directory in the WebPack software to see if it changes anything for you. May help you track down the problem. -- BrianArticle: 72276
I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus. When I try to do a write (ST) to the SDRAM I see that the cpu.the_sdram_s1.sdram_s1_chipselect is asserted. However the NIOS top level cpu.zs_cs_n_to_the_sdram_sdram_chip is not. If I replace the SDRAM target address of the ST instruction with a different different target address I observe that the chip select signal for that device is asserted as well as the systembus write enable signal. But I can't get this to work for the SDRAM. Any ideas? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 72277
"Captain Bly" <Bobcrap@aol.com> wrote in message news:<nmpSc.8990$js3.1583307@news4.srv.hcvlny.cv.net>... > "Jerry" <nospam@nowhere.com> wrote in message > news:10hip30b8p0f237@corp.supernews.com... > > "Captain Bly" <Bobcrap@aol.com> wrote in message > > news:yT3Sc.53161$zc4.22664573@news4.srv.hcvlny.cv.net... > > > I got a tee shirt, I could only assume it's someone that works for > Altera > > > > > > "Jerry" <nospam@nowhere.com> wrote in message > > > news:10hg4i8oulqp5af@corp.supernews.com... > > > > Does anyone know who won the camera from Altera on that Cyclone 2 web > > > > presentation? > > > > WOW, you got the tee-shirt? I didn't even get to register to win the > camera > > after sitting through > > an hour of rehashed info then listening to questions that were answered by > > the marketerr. Yes I > > did complain to Altera about it but it hasn't done me any good. The big > > question is will this > > incident affect my decision to go Altera or Xilinx on the next design? No > it > > won't. > > So only one person on this newsgroup got a tee-shirt? I thought the first > > 300 were going to > > receive one. > > > > ARRRRRGGGGG oh wait.................... > > If you are saying ARRRRRRGGGGG a lot lately you may be designing with > > Altera. > > You know how it, if you give Altera $100K in orders then they will get you a > tee shirt "after you win a contest" > - actually who knows, maybe the other 299 tee-shirt wins don't subscribe to > this group. Hey, a few years back (perhaps do a Google Groups search!) somebody posted a complaint here saying, "Hey, Xilinx, your ad said to go to your website and sign up for something and Xilinx will send you a free t-shirt and I never got the t-shirt!" A whole bunch of us replied with a "Me, too!" Very soon after that, I got a Xilinx WebPack t-shirt in the mail. Hey, Altera: Where's my t-shirt? Andy Peters 5511 E Rosewood St Tucson, AZ 85711 --aArticle: 72278
Hi Jerry, > Does anyone know who won the camera from Altera on that Cyclone 2 web presentation? I hear that we publish the list of winners for contests in a monthly Altera Net Seminar newsletter. The winner of the camera is an engineer in Beaverton, Oregon. Altera is checking with him to see if we can publish his name and company name. > WOW, you got the tee-shirt? I didn't even get to register to win the camera > after sitting through > an hour of rehashed info then listening to questions that were answered by > the marketerr. Yes I > did complain to Altera about it but it hasn't done me any good. The big > question is will this > incident affect my decision to go Altera or Xilinx on the next design? No it > won't. I'm told by our online marketing group that the survey at the end of the net seminar was likely blocked if you have a "pop-up blocker" installed on your web browser. Regardless of whether this was the cause, I apologize if you did not get a chance to submit a survey and enter the draw. > So only one person on this newsgroup got a tee-shirt? I thought the first > 300 were going to > receive one. Of all the places we have to cut costs, giving out fewer than 300 shirts is probably low on the list! We have tens of thousands of users, only a fraction of whom frequent this group. If you really want a shirt, drop me an email -- I have a shelf at home full of various cuts, colours, slogans, fonts, quality and wear levels ;-) Regards, Paul Leventis Altera Corp.Article: 72279
I am just ticked off that I didn't have a chance to win that camera. Maybe there is more people like me that didn't have a chance to win. I already have a Stratix shirt which is nice. Its even nice than the one I have from Chip Express. I don't have one from Xilinx ...... yet. I don't have a pop up blocker since I get all kinds of loan, lonely heart and insurance offers as I surf around looking for the latest tech advances. "Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:QOUSc.12$S4D.4@news04.bloor.is.net.cable.rogers.com... > Hi Jerry, > > > Does anyone know who won the camera from Altera on that Cyclone 2 web > presentation? > > I hear that we publish the list of winners for contests in a monthly Altera > Net Seminar newsletter. The winner of the camera is an engineer in > Beaverton, Oregon. Altera is checking with him to see if we can publish his > name and company name. > > > WOW, you got the tee-shirt? I didn't even get to register to win the > camera > > after sitting through > > an hour of rehashed info then listening to questions that were answered by > > the marketerr. Yes I > > did complain to Altera about it but it hasn't done me any good. The big > > question is will this > > incident affect my decision to go Altera or Xilinx on the next design? No > it > > won't. > > I'm told by our online marketing group that the survey at the end of the net > seminar was likely blocked if you have a "pop-up blocker" installed on your > web browser. Regardless of whether this was the cause, I apologize if you > did not get a chance to submit a survey and enter the draw. > > > So only one person on this newsgroup got a tee-shirt? I thought the first > > 300 were going to > > receive one. > > Of all the places we have to cut costs, giving out fewer than 300 shirts is > probably low on the list! We have tens of thousands of users, only a > fraction of whom frequent this group. If you really want a shirt, drop me > an email -- I have a shelf at home full of various cuts, colours, slogans, > fonts, quality and wear levels ;-) > > Regards, > > Paul Leventis > Altera Corp. > >Article: 72280
Hi Alistair, alastair wrote: > I'm trying to build a system with Xilinx EDK 3.2 which will have 2 > Microblaze processors running separate code on a Virtex-II > (xc2v-1000). Firstly - if you possibly can, then upgrade to the latest version of EDK. That's general advice, not specific to your question! > In XPS, each microblaze component is attached to it's own data and > instruction LMB's which have BRAM and BRAM controller blocks attached > in turn. When I attempt to generate the bitstream, the process fails > during the map stage. I get the following error message: > Number of Block RAMs: 64 out of 40 160% > So it looks to me like the number of block RAM's is where the problem > is. In the properties for each block ram, I've set the following > properties: > C_MEMSIZE = 8192 > C_PORT_AWIDTH = 13 > > There is a total of 64k of block RAM available, so I figured that > allocating 8k to each processor should be fine. Check to see if you are using caches for the microblaze - they are implemented in BRAM. a 16K data and instruction cache will quickly chew through your BRAM. Also, if you grep through the *.srp files in the /synthesis project subdirectory, you should be able to summarise the total BRAM usage: Try this: grep "Number.*BRAM" synthesis/*.srp That will tell you exactly where you BRAM is going. > If anyone has tried something similar I'd appreciate some ideas. I've built a dual processor microblaze system before (two microblazes on the same OPB bus, shared memory etc) and it synthesised without any troubles for the XC2V1000. I can dig out the project files if you are interested. Cheers, JohnArticle: 72281
Hi Sudarshan, sudarshan banerjee wrote: > So, it seems Virtex-II configuration architecture is different > from Virtex configuration architecture. > Unfortunately I have so far not been able to locate any document > specific to Virtex-II configuration architecture I think the Virtex2 Users Guide has a chapter dedicated to the configuration architecture. It should give you all the equations and numbers about frames and so on. Grab it from the Xilinx website. Regards, JohnArticle: 72282
Please tell me what is the multicycle path and how can we use it to optimize the critical path delay using LeonardoSpectrum.. Thank you..Article: 72283
Identify will display enum types directly. Everything is done in terms of the RTL source. No guessing. - Ken Moti Cohen wrote: > Hi all, > > I'm cuurently working on a xilinx spartan 2e design, for debug I'm > using the chipscope pro LA. > the problem is as follows: I'm using the chipscope pro for looking at > the logic lines (bus) that define the "state" of the state machine in > order to determine the present state of the machine at a given time. > but the chipscope is giving me the binary (or oct, hex etc.) value of > the bus. > when I'm declaring the state machine in VHDL I'm giving each state a > name (the synt' does the enumeration automatically) so I do not know > what is the corresponding bus value for each state. > I'm pretty sure that the Xilinx synthisizer generates this kind of > data but I dont know where to find it and so is their FAE :) > > for example: > if I declare a simple state machine with the follwoing states: > > type state_type is (idle , first , second , last) > > I would like to get a reference data such as: > > idle = 00 > first = 01 > second = 10 > last = 11 > > that would be very helpfull when debugging large state machines with > chipscope. > So if anyone knows where to find it (if possible) I would realy > appreciate it. > > thanks in advance, Moti.Article: 72284
"INS122595" <walter@chasque.apc.org> wrote in message news:10hmpo4eg7tb20b@news.supernews.com... > THX > > Open the schematic with the older software to know what do and know how > work; and then redo the project into the most generic VHDL as possible; > without trying to copy a schematic into VHDL. But I have only these 2 tools above - old tool - I can generate netlist but new - ISE I cannot import it! > > ( One more reason to use VHDL standard ) > > Walter > > "buke2" <cubah@tlen.pl> a écrit dans le message de > news:cff932$pv0$1@atlantis.news.tpi.pl... > > Anybody knows how convert schemtic from Xilinx 2.1 to ISE6.2 Webpack? > > It is very strange that ISE6.2 cannot convert earlier version of schematic > > (the same company). > > > > THX > > > > > >Article: 72285
The question is result of experience in designing Xilinx chip with Xilinx Foundation 2.1i (very old tool)and ISE6.2. The first have not good enough VHDL creating tool, the socond is newest but schematic editor has many...many bugs!! Anybody has experience with other free GOOD schematic tools ? THX BukeArticle: 72286
Do you know how to reconfigurate the DFS of Spartan DCM at runtime? I would like to change the FXMULTIPLY AND FXDIVIDE in order to get different CLKFX at runtime. According to xilinx manual it's not possible. But probabely smbd has just a good idea? PS: a simple reload of the FPGA configuration is too slow...Article: 72287
patcher wrote: > Do you know how to reconfigurate the DFS of Spartan DCM at runtime? > > I would like to change the FXMULTIPLY AND FXDIVIDE in order to get > different CLKFX at runtime. According to xilinx manual it's not > possible. > > But probabely smbd has just a good idea? > > PS: a simple reload of the FPGA configuration is too slow... Does the Spartan 3 have BUFGMUXes like the Virtex-II Pro? If so, you could it it differently alltogether... Use two DCMs to create the two clocks you want to switch between, and feed them into the two inputs of a BUFGMUX... then you could just chose the desired output clock by changing the select signal.... not sure what happens to attached logic during the switch, though... cu, SeanArticle: 72288
Guys, Thanks for the advice - we're intending to update to the latest version of the tools soon :) It's been a while since I did any development with XPS (that's my excuse) and after checking the memory map for the BRAM controllers I get past the error I saw. Now I get another one when generating the bitstream: ERROR:Ncd:528 - Could not find the the corresponding NC_COMP for the BlockRAM instancename:<bram_lmb_2/bram_block_0_i/ramb16_s9_s9_0>.Cannot continue with BlockRAM updates. ERROR:Bitgen:194 - Unable to update BRAM initialization data for design system.ncd. make: *** [implementation/system.bit] Error 1 Done. John - if you have time to dig out your project with dual processors I'd appreciate being able to have a look at the setup. I'm not sure what the error means and can't seem to find any information on the error from a quick search on Google and the Xilinx website - any ideas ? Thanks again, Alastair.Article: 72289
Hi there, We have a Xilinx AFX FF1152 Virtex-II Pro board with a xc2vp20 on it. I have tried to get a simple design up usign the SDRAM, but the memory check code inserted by EDK fails (the code lives in the PLB BRAM, and EDK kindly included a memory checker for the SDRAM). On the FPGA I'm using one of the PPC cores, which is connected to some BRAM over the PLB, and to an SDRAM interface on the PLB (basically this is what the system builder wizard creates for you). EDK doesn't support out specific AFX board, so I've manually updated the pin assignment information in the UCF file to match that in the documentation. For clocking, I'm using a 100 MHz oscillator in the socket marked RAM/FPGA, which as I understand it will clock the SDRAM and provide me a clock on pin D18. This clock is then fed through a DCM and the output of CLK0 is used as the OPB bus clock and fed into the OPB-SDRAM interface core. The RAM enable jumper is set to on. When I try to test the memory it fails. If I write a bunch of data to the SDRAM and read it back I just get the last value I wrote. Any suggestions as to what I might have missed? -- Michael Dales University of Cambridge Computer Laboratory http://www.cl.cam.ac.uk/~mwd24/Article: 72290
We have large inventory of Xilinx FPGA. Many parts are obsolete. All parts are new and in original packaging. Our pricing is usually 40% lower than Franchise Distributor pricing. Please visit our website to view our offers with pricing. www.mercuryintonline.com MikeArticle: 72291
Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant to the Infiniband standard (beacon and variant CRC excluded). There are two types of CRC, the invariant and the variant type. Although the RocketIOs are able to calculate at least one type, i.e. the invariant CRC, you cannot make use of it in this particular case. The reason for this is that the invariant CRC is needed for the variant CRC type which you have to handle yourself, anyway. Has anyone ever tried or finished an Infiniband implementation inside the V2P/RocketIOs and could share his experience with me? Or is there any example implementation for the whole CRC calculation inside the FPGA fabric available? I wonder how one could ever reach the typical 2.5 Gbit/s Infiniband transmission rate when almost all functions must be handled inside the FPGA fabric? Still some other questions: Could someone please help me on the question how often the beacon signal should be repeated before synchronisation is sufficiently established? And what about the packet generation? There are several IBA packet structures. If I assume a plain point-to-point connection it surely would not be necessary to include all that global routing stuff inside the header. So what would be the adequate format to use? The "local packet" structure or maybe just "raw packets"? If someone got the slightest clue, please post a write an email! Any answer is appreciated. Best regards, Bruce Keywords: FPGA, Xilinx, Virtex 2, Virtex2, Virtex-2, Virtex II, VirtexII, Virtex-II, RocketIO, RocketI/O, RocketIOs, RocketI/Os, Rocket IO, Rocket I/O, Rocket IOs, Rocket I/Os, Virtex2Pro, VirtexIIPro, MGT, SerDes, Gigabit Transmission, Infiniband, Beacon Signal, Synchronisation, Gbit, Gb, Gbit/s, Gbits, Gb/s, Gbs, P2P, IBAArticle: 72292
You can use the free Quartus II Web Edition which has a good schematic editor for Altera parts. The Quartus II Web Edition can be downloaded from: https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp Subroto Datta Altera Corp. "buke2" <cubah@tlen.pl> wrote in message news:cfhsd0$3e6$1@atlantis.news.tpi.pl... > The question is result of experience in designing Xilinx chip with Xilinx > Foundation 2.1i (very old tool)and ISE6.2. > The first have not good enough VHDL creating tool, the socond is newest but > schematic editor has many...many bugs!! > > Anybody has experience with other free GOOD schematic tools ? > > THX > Buke > >Article: 72293
Hi Joseph,
Thank you for your thoughtful reply. There are a couple of points I'd
like to clarify.
>For example, to use chip
> features (like PLL) you run a wizard to generate or modify "megafunction"
> macros which you then instantiate in your HDL design files. Also you need
> the GUI to enter timing and placement constraints (theoretically you could
> do it with text, but there's no documentation). For complex functions,
the
> wizard is probably better, but scripting people will still not like it.
>
Our experience has shown, that stamping out megafunction instances for
complex device functions like PLL's, LVDS etc. can be very error prone in
all but the simplest of cases. We have therefore provided Customized
Graphical Megawizards to help the user get their megafunction instance
correct the first time. The Megawizards provide extensive realtime error
checking and thereby allow the user to correct their design before they
start on a synthesis, place and route cycle. We feel the Megawizard approach
is important enough for all users and have it available in our free Quartus
II Web Edition. The Megawizard generates the blackbox files which can be
"cut and pasted" in your HDL, identical to what you allude to below.
> Also, it's all one monolithic tool: the different functions are not really
> exposed and the database is very closed. You do not get to see the output
> from one function and the input to another, or where one ends and another
> begins. Instead there is an integrated database which each tool accesses.
> This makes a 'makefile' somewhat meaningless.
>
With Quartus II 3.0 the compiler engine was monolithic was rearchitected
into 5 separate executables. These executables are called quartus_map
(netlist extraction and synthesis), quartus_fit (fitter), quartus_tan
(timing analysis), quartus_asm (assembler) and quartus_eda (netlist
generator for external verification tools). When you compile through the GUI
each of these executables are called in sequence just like you would from
the a shell script. The Message Window output shows the exact commands that
you can cut and paste into a shell script for compilation. These executables
can also be invoked from the command prompt repeatedly in any order. Infact
one of the common uses is to feed different devices speedgrades as a
command line option to quartus_tan to see how timing would vary without
refitting the entire design.
Each of these tools has their own databases, and we may choose to expose
them at a later time. If the definition of a makefile is to capture the
dependencies of the source files files and settings file, and to know when
each executable is to be run with command line options, I believe that the
makefile descrption provided in the Quartus Handbook Command Line Scripting
Chapter:
http://www.altera.com/literature/hb/qts/qts_qii52002.pdf Pgs 2-14 through
2-16 reflects this ability accurately.
Subroto Datta
Altera Corp.
Article: 72294Hi, I'm using Xilinx 804 aurora vhdl design and I saw that on their web-site that there was a patch for it (Record Number: 18554) but the file is not available on their server anymore. I asked them and they seem to have problem finding it back. If any of you sees what I mean and has downloaded the patch called aurora_804_sp_patch.zip Could you let me know and I'll contact you directly (I'm not too fond of spam). Best regards, Jeremie.Article: 72295
Why : - Do you post the same post at 40 minutes interval - Do you post the same post in at least 3 differents groups I'm subscibed to The only effect is that it's make people angry and lessen their motivation to answer you. So don't do it. If you feel your post could belong to several newsgroup, choose the ones that is more likely to have people you look for. Given the post, I'd say it's here in FPGA. design is too generic, and vhdl is more about the language itself than what you do with it. Sylvain Bruce wrote: > Hello, > at present I am working on an Infiniband implementation on a Virtex-II > Pro. As far as I know the build-in RocketIOs are fully compliant to > the Infiniband standard (beacon and variant CRC excluded). There are > two types of CRC, the invariant and the variant type. Although the > RocketIOs are able to calculate at least one type, i.e. the invariant > CRC, you cannot make use of it in this particular case. The reason for > this is that the invariant CRC is needed for the variant CRC type > which you have to handle yourself, anyway. Has anyone ever tried or > finished an Infiniband implementation inside the V2P/RocketIOs and > could share his experience with me? Or is there any example > implementation for the whole CRC calculation inside the FPGA fabric > available? I wonder how one could ever reach the typical 2.5 Gbit/s > Infiniband transmission rate when almost all functions must be handled > inside the FPGA fabric? Still some other questions: Could someone > please help me on the question how often the beacon signal should be > repeated before synchronisation is sufficiently established? And what > about the packet generation? There are several IBA packet structures. > If I assume a plain point-to-point connection it surely would not be > necessary to include all that global routing stuff inside the header. > So what would be the adequate format to use? The "local packet" > structure or maybe just "raw packets"? If someone got the slightest > clue, please post a write an email! Any answer is appreciated. Best > regards, Bruce > > Keywords: FPGA, Xilinx, Virtex 2, Virtex2, Virtex-2, Virtex II, > VirtexII, Virtex-II, RocketIO, RocketI/O, RocketIOs, RocketI/Os, > Rocket IO, Rocket I/O, Rocket IOs, Rocket I/Os, Virtex2Pro, > VirtexIIPro, MGT, SerDes, Gigabit Transmission, Infiniband, Beacon > Signal, Synchronisation, Gbit, Gb, Gbit/s, Gbits, Gb/s, Gbs, P2P, IBAArticle: 72296
On Thu, 12 Aug 2004 22:07:43 -0400, "Jerry" <nospam@nowhere.com> wrote: >I don't have a pop up blocker since I get all kinds of loan, lonely heart >and insurance offers as I >surf around looking for the latest tech advances. Google, the company that tries to "Do No Evil" , has a toolbar addon/plugin for common web browsers: http://toolbar.google.com/ It's Free, it's easy and convenient to use, and it has an excellent pop-up and pop-under blocker. Probbably the most anti-evil thing I have on my computer, and very well appreciated. Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 72297
Hi Jeremie,
I'm sorry to say that the zip file you are looking for only contains a
Verilog version of the patch. It was originally produced by special request
for a customer who could not upgrade to one of our newer designs: they had
made custom changes to the old module.
In general we recommend an upgrade to one of the modules from the
Xilinx Core Generator tool - these are the smallest Aurora designs we offer,
and have the same interface as the old designs. I would be happy to create a
VHDL version of the patch for you. If you contact me directly or pass the
message along via your FAE or hotline, I'll do my best to help you out.
In hindsight, we should have provided both languages in the zip file.
We're working to fix the broken link on the server - when its up and running
again, we'll add the VHDL version of the patch to the zip file.
Cheers,
Nigel
Jeremie Veyret wrote:
> Hi,
>
> I'm using Xilinx 804 aurora vhdl design and I saw that on their web-site
> that there was a patch for it (Record Number: 18554) but the file is not
> available on their server anymore.
> I asked them and they seem to have problem finding it back.
> If any of you sees what I mean and has downloaded the patch called
> aurora_804_sp_patch.zip
> Could you let me know and I'll contact you directly (I'm not too fond of
> spam).
>
> Best regards,
>
> Jeremie.
Article: 72298I would like to use a Virtex to connect a camera in LVDS ( camera Link). Is possible to do that directly, or should I use an external driver. Thanks to all. PippoArticle: 72299
On Fri, 13 Aug 2004 06:09:36 -0700, Bruce wrote: > Hello, > at present I am working on an Infiniband implementation on a Virtex-II > Pro. As far as I know the build-in RocketIOs are fully compliant to > the Infiniband standard (beacon and variant CRC excluded). There are > two types of CRC, the invariant and the variant type. Although the > RocketIOs are able to calculate at least one type, i.e. the invariant > CRC, you cannot make use of it in this particular case. The reason for > this is that the invariant CRC is needed for the variant CRC type > which you have to handle yourself, anyway. Has anyone ever tried or > finished an Infiniband implementation inside the V2P/RocketIOs and > could share his experience with me? Or is there any example > implementation for the whole CRC calculation inside the FPGA fabric > available? I wonder how one could ever reach the typical 2.5 Gbit/s > Infiniband transmission rate when almost all functions must be handled > inside the FPGA fabric? Still some other questions: Could someone > please help me on the question how often the beacon signal should be > repeated before synchronisation is sufficiently established? And what > about the packet generation? There are several IBA packet structures. > If I assume a plain point-to-point connection it surely would not be > necessary to include all that global routing stuff inside the header. > So what would be the adequate format to use? The "local packet" > structure or maybe just "raw packets"? If someone got the slightest > clue, please post a write an email! Any answer is appreciated. Best > regards, Bruce > > Keywords: FPGA, Xilinx, Virtex 2, Virtex2, Virtex-2, Virtex II, > VirtexII, Virtex-II, RocketIO, RocketI/O, RocketIOs, RocketI/Os, > Rocket IO, Rocket I/O, Rocket IOs, Rocket I/Os, Virtex2Pro, > VirtexIIPro, MGT, SerDes, Gigabit Transmission, Infiniband, Beacon > Signal, Synchronisation, Gbit, Gb, Gbit/s, Gbits, Gb/s, Gbs, P2P, IBA We have a 4X IBA core available that works with both Rocket IO and external SerDes. http://www.polybus.com/ib_link_layer_website/
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