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Peter Alfke wrote: > I was the one who added this sentence into the manual, in order to really > clarify the issue. Apparently I was not clear enough... > So: In a combined multiply-divide operation, only the input frequency and > the final output frequency must fall into the specified ranges. > Multiplication and division are not performed in sequence, but really as a > simultaneous combined mathematical operation, so the DCM never sees the > result of multiplication alone, or of division alone. Is there a description, even a relatively simple one, about how DCMs work? I understand analog PLL's with dividers on the input and output feeding the phase comparator, where the intermediate frequency does matter, at least a little bit. -- glenArticle: 74251
ben@ben.com (Ben Jackson) wrote in message news:<07E8d.206436$3l3.200253@attbi_s03>... > In article <bf59e739.0410051257.67b63d89@posting.google.com>, > John M <statepenn99@yahoo.com> wrote: > > > >I am looking for an efficient hashing algorithm that can be easily > >translated to an FPGA. > > Hash over what data? A 32 bit word? A variable length string of data? I need to hash over variable sized keys (from 72-288 bits) and produce a hash that is 20 bits. The bits would be presented in 32-bit words. I do have access to a sample data base that can be used to determine how well a hash will perform in terms of collisions. I can't really say what type of data it is, other than it is not text. Thanks for everyone's help so far. JohnArticle: 74252
Here is an IBM + Xilinx paper on comparisons of ASIC vs FPGA. Note that, this paper probably gives conservative numbers (since Xilinx co-authored it). http://www.sigda.org/Archives/ProceedingArchives/Iccad/Iccad2002/03c_1.pdf I have found that in general (the exact answer depends on speed you are running at etc), all three metrics of area, power and speed are off by 50 to 100x. For example, several FPGA dies are 100 sq.mm. And you can fit about 1 million gates on them. At the same technology node, you can fit about 100 million gates or more (especially if you are Intel/custom designers). To add to the discussion about Structured ASICs (SAs) vs FPGAs vs ASICs that took place on this thread, SAs save on NRE costs and some backend tools costs over ASICs. But all other costs, designing, verification, and testing are the same for all three, SAs, FPGAs, & ASICs. The reason why people feel that FPGAs take lower time to design and deploy is because of the size of designs you can fit on a FPGA. Don't be fooled by the "system gates" that FPGA vendors tout. In reality, those system gates should be divided by 5 to 10 depending again on what speed you are running your design at. This means that a 8million system gate device can fit less than 1 million ASIC gates for high performance designs and about 2 million ASIC gates at very slow speed. In as far as mask costs and when it makes sense to use FPGAs or SAs instead of ASICs can come down to a simple Excel sheet that has your design, verification, CAD tools etc cost for each (pretty much the same for all three, except for back-end tools) + the NRE costs for each ($0 for FPGAs, $100K-250K for SAs, $0.6-0.8M mask costs at 0.13u for ASICs) and the cost per chip (very high for FPGAs, lower for SAs and super low for ASICs) times the volume. (Hope that was not too much of a ramble). Of course, the folks from Xilinx & Altera on this board might/will disagree with me -- but this is just one man's opinion based on talking to a lot of FPGA designers and also, some inside info from marketing folks at Xilinx & Altera ... SumitArticle: 74253
John M wrote: (snip) > I need to hash over variable sized keys (from 72-288 bits) and produce > a hash that is 20 bits. The bits would be presented in 32-bit words. > I do have access to a sample data base that can be used to determine > how well a hash will perform in terms of collisions. I can't really > say what type of data it is, other than it is not text. Thanks for > everyone's help so far. With a 20 bit hash, you will have a reasonably collision probability at 1000 keys. The number of key pairs is N*(N-1)/2. CRC's are fairly easy to compute in FPGAs, even much larger than 20 bits. I did a 64 bit CRC (in software) once when N was in the millions to get the collision rate reasonably close to zero. -- glenArticle: 74254
Glen, Let me try to explain it. The digital frequency synthesizer uses a tapped delay line oscillator as its source of output clock. The taps are adjusted such that the output frequency is related to the input frequency by the M and D values. At every input clock divided by D, or every output clock divided by M (equivalent), the phase of the output is hard sync'ed to the input rising edge (what we refer to as 'concurrence'). In this way the total phase error is not unbounded (as in is in a PLL), but is never worse than the worst wrong guess at the tap value. Most folks will recognize after they perform some thought experiments that changing the tap value is too coarse to actually allow the phase error to remain as small as we claim. A clever design technique (patented) is used by which we a priori change tap values between concurrences to estimate in advance the proper combination of delays to exactly match one CLKFX cycle. I refer to this as a 'tap dance.' (please forgive my humor, but it is part of my personality....) Change the M, or D, or input frequency, and the 'tap dance' changes such that the loop stays locked, and the output remains phase and frequency locked to the input. In this way, the phase error (if the oscillator is perfect) is never worse than a tap value for one whole concurrence cycle (D cycles of input clock, or M cycles of output clock). Austin glen herrmannsfeldt wrote: > > > Peter Alfke wrote: > >> I was the one who added this sentence into the manual, in order to really >> clarify the issue. Apparently I was not clear enough... >> So: In a combined multiply-divide operation, only the input frequency and >> the final output frequency must fall into the specified ranges. >> Multiplication and division are not performed in sequence, but really >> as a >> simultaneous combined mathematical operation, so the DCM never sees the >> result of multiplication alone, or of division alone. > > > Is there a description, even a relatively simple one, about > how DCMs work? I understand analog PLL's with dividers on > the input and output feeding the phase comparator, where the > intermediate frequency does matter, at least a little bit. > > -- glen >Article: 74255
Here is another article that has comparisons of ASIC vs FPGA area. This is from Charles Rupp, who knows FPGA architectures inside out: http://suif.stanford.edu/~courses/cs343-spring03/l8.pdf SumitArticle: 74256
does any one know if there is a 64 bit windows or linux version of xilinx ISE available? thanks Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 74257
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > > This thread turns out into a contest to build the fastest JOP version. > > Choose an FPGA vendor of your choice and optimize HDL and tool > > settings. > > Maybe Martin should donate one of his boards to the winner ;-) > > OK, that's a good idea! > Here's the contest in two categories: > The smallest JOP in LC/LE count. > The fastest JOP in turn of fmax. That's fun! > Both versions must run the embedded benchmark to show that the processor > is still working (I can verify this for the Cyclone and Spartan-3. Target > devices are the low-cost FPGAs Cyclone and Spartan. > You can change the pipeline to achieve a higher famx, but the benchmaks > must still run AND be faster than with the original pipeline. However, I > would avoid the pipeline change. You might want to add the constraint that no instruction might be removed from the core even when they are not used by the benchmarks. > The prices: An ACEX 1K50 board Kolja SulimmaArticle: 74258
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0410052244.46ab4972@posting.google.com>...
> Hi,
>
> I have a question concerning my multi-clock design.
>
> A PLL is fed with a 30MHz external clock.
>
> There are three different clocks generated by the PLL:
>
> c0 : 48MHz (for internal use)
> c1 : 90MHz (for internal use)
> e0 : 90MHz (for external use)
>
> Apart from that I have a clock divider which generates an
> 12MHz clock out of c0 and an inverted 90MHz clock out of c1.
>
>
> When I compile the whole design I get the following warnings:
>
> 1.Found 1 node(s) in clock paths which may be acting as ripple and/or
> gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
> Info: Detected ripple clock CLOCK_DIVIDER
>
> Do I have to make some assignment for that? How?
>
> I would appreciate your help.
>
> Rgds
> André
Hello André,
Here is what you need to do:
1.- Define a Base Clock for your clock pin. This clock should have a
requirement of 30MHz (Use Assignments->Settings->Timing Requirements
and Options->Clocks)
2.- Define a derived clock for the CLOCK_DIVIDER. This clock should
have the following characteristics:
- based on the base clock defined on the clock pin (Step 1)
- multiply Fmax by 2
- divide Fmax by 5
30 * 2 / 5 = 12
- Do NOT set any offset value. This will make the Timing Analyzer auto
compute it.
(Use Assignments->Settings->Timing Requirements and
Options->Clocks->New->Based On)
Note that if there are any transfers between the pll input (30MHz) and
the pll output (12MHz), the timing analyzer is likely to find a setup
relationship (a requirement for this transfer).
That should be it. All PLL outputs do not need a clock setting as the
Timing Analyzer auto generates them. The inverted clock out of c0 will
also be processed correctly by the Timing Analyzer.
Hope this helps.
- Subroto Datta
Altera Corp.
Article: 74259
On 6 Oct 2004 04:17:07 -0700, matteopalma@libero.it (Matteo) wrote:
>Anyone know how to instantiate ( in Viewdraw ) a bus with a fixed
>value?
>
>I try to explain better: if for example I have to add the constant
>decimal value 7 to an incrementer every time I have a rising clock
>event, I suppose I have to enter in the incrementer with a 4-bit wide
>bus which holds the value 7 every time.
>
>How can I do it??
>
>Thanks in advance,
>Teo.
There are several ways to do this. The simplest is this:
Place the following 4 symbols on your schematic:
GND
VCC
BUF
BUF
Connect the GND to a BUF input.
Connect the VCC to a BUF input.
Place a net stub on the outputs of each of the BUFs
Label the net on the output of the BUF that has its input connected to GND: "L"
Label the net on the output of the BUF that has its input connected to VCC: "H"
(obviously, don't include the quote characters)
If for example you have an 8 bit adder, you can now place a bus stub
on one of its inputs. Label this bus stub
L,L,L,H,L,L,H,L
And you will get the HEX constant 0x12, which is 18 decimal.
Philip
===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
Article: 74260ALuPin wrote: > Hi, > Hi Andre, > I have a question concerning my multi-clock design. > > A PLL is fed with a 30MHz external clock. > > There are three different clocks generated by the PLL: > > c0 : 48MHz (for internal use) > c1 : 90MHz (for internal use) > e0 : 90MHz (for external use) > > Apart from that I have a clock divider which generates an > 12MHz clock out of c0 and an inverted 90MHz clock out of c1. > > > When I compile the whole design I get the following warnings: > > 1.Found 1 node(s) in clock paths which may be acting as ripple and/or > gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew > Info: Detected ripple clock CLOCK_DIVIDER > > Do I have to make some assignment for that? How? Just generate a new clock domain (12 MHz), and apply it to the output node of your clock divider. Quartus will stop yammering immediately. It's good to have a whiny, grumpy timing analyzer ;-) Best regards, BenArticle: 74261
In comp.arch.embedded hol <abol@hol.com> wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. ... look at gaisler.com. Regards Adam PrzybylaArticle: 74262
Peter Alfke wrote: > Mea culpa! > I was the one who added this sentence into the manual, in order to really > clarify the issue. Apparently I was not clear enough... > So: In a combined multiply-divide operation, only the input frequency and > the final output frequency must fall into the specified ranges. > Multiplication and division are not performed in sequence, but really as a > simultaneous combined mathematical operation, so the DCM never sees the > result of multiplication alone, or of division alone. > This is not intuitively obvious, and a circut description would be far too > complex, so we have to explain it in English, and you must take our word for > it. Well, you will also experience that it works. :-) > Peter Alfke Maybe you could try a maths based description, generally that's much better than English ? Fo = fi * M/D; Valid for LLimitM < M < ULimitM [You fill out the Limits ] LLimitD < D < ULimitD and if there are interactions (Limits depend on other variables value) , then expand this as necessary. > > > >>From: RobertP <r_p_u_d_l_i_k@poczta.onet.pl> >>Organization: news.onet.pl >>Newsgroups: comp.arch.fpga >>Date: Wed, 06 Oct 2004 16:16:09 +0200 >>Subject: DCM and CLKFX - is this allowed? >> >>Hello, >>I have an input clock of 125MHz coming to VirtexII device. I want to >>derive 80MHz clock from it. >>The way I wanted to go is to use CLKFX output with 16/25 (M/D) factor. >>Can I do this without violating timing requirements for the DCM? >>Both the input and output frequencies are within allowed range and I get >>no warnings neither from architecture wizard nor from online CLKFX >>jitter calculator, however I'm not fully understand the sentence from >>user guide ug002: >> >>"For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note >>that M and D values have no common factors and hence cannot be reduced). >>The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = >>1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far >>outside the range of the input frequency." >> >>Does this mean that I cannot use 16/25 factor in my case? >> >>-- >>RobertP. > >Article: 74263
Hi Austin, Austin Lesea wrote: > I refer to this as a 'tap dance.' (please forgive my humor, but it is > part of my personality....) Change the M, or D, or input frequency, and > the 'tap dance' changes such that the loop stays locked, and the output > remains phase and frequency locked to the input. > > In this way, the phase error (if the oscillator is perfect) is never > worse than a tap value for one whole concurrence cycle (D cycles of > input clock, or M cycles of output clock). Any ideas (or experience) on what happens if you twiddle DCM configuration bits on the fly (a la partial reconfig)? I'm guessing it would be safe to hold the DCM in reset, change the tap configuration, then restart it, but that's not much use if the DCM is clocking the very same logic that is driving the partial reconfiguration :) I'm picturing a self-reconfiguring microblaze uClinux system dynamically scaling its own clock... JohnArticle: 74264
> > > This thread turns out into a contest to build the fastest JOP version. > > > Choose an FPGA vendor of your choice and optimize HDL and tool > > > settings. > > > Maybe Martin should donate one of his boards to the winner ;-) > > > > OK, that's a good idea! > > Here's the contest in two categories: > > The smallest JOP in LC/LE count. > > The fastest JOP in turn of fmax. > > > You might want to add the constraint that no instruction might be > removed from the core even when they are not used by the benchmarks. This constraint is more or less implicit: You're not allowed to remove any functionality of JOP and it does not make sense to optimize the IO system (like reducing the buffer size of the UART). Only the CPU core is the optimizing target. And don't be too impressed by the saving (the 300 LCs) Kolja announced ;-) They're good, but broke JOP. I'm actually in the process of getting a version that works. He saved some LCs but not that many. I will not tell you the exact count, but if you can save 100 you're competing with Kolja... The chance to win the competition is still open. To Kolja: I will send you the results with comments tomorrow, when I'm through all tests. BTW: Let's set a deadline for the contest: I will accept all suggestions till next Friday (10/15) so I've time over the weekend to verify the results. The winner will be posted on Monday (10/18). Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74265
SG, I agree with you. Since IBM and Xilinx wrote the paper together, we both had to agree on what is in there. Since IBM is #1 in ASIC's, I would not argue with them, either. Just remember that the PPC, MGT, DCM, EMAC, DSP48, etc. are all 'hard cores' and do not 'suffer' from the same 10:1 disadvantages in speed and power as plain old interconnect and logic. Not mentioned here is that ASICs suffer a 10:1 disadvantage in single event upsets. Every single upset in an ASIC is a functional failure (plus they are a lot more sensitive being the smallest structure possible). Only 1:10 SEUs in a FPGA cause a functional failure. The two factors cancel out. We take 10X more to do the same job, but have 1/10 the upset rate, so we come back to parity on hardness against cosmic ray neutron showers. Many folks erroniously believe that ASICs are better with respect to SEUs (or conversely FPGAs are worse than ASICs): they are not. Page 7 of 8 details the comment I made about how incorporation of a FPGA core into an ASIC might offer benefits in test coverage. Since I did not know this had been published, I was unable to disclose it here (basically this is IBM's property). Since it is published, go read it and decide. An interesting thought: is a hybrid ASIC/FPGA a better choice than an ASIC alone? Is our FPGA becoming a big programmable fabric with little ASIC bits in it? Is IBM's ASIC becoming a bunch of ASIC stuff connected by little programmable fabric bits? You decide. If you do not go with our FPGA, then by all means go with IBM's ASIC/FPGA hybrid..... Austin SG wrote: > Here is an IBM + Xilinx paper on comparisons of ASIC vs FPGA. Note > that, this paper probably gives conservative numbers (since Xilinx > co-authored it). > http://www.sigda.org/Archives/ProceedingArchives/Iccad/Iccad2002/03c_1.pdf > > I have found that in general (the exact answer depends on speed you > are running at etc), all three metrics of area, power and speed are > off by 50 to 100x. For example, several FPGA dies are 100 sq.mm. > And you can fit about 1 million gates on them. At the same technology > node, you can fit about 100 million gates or more (especially if you > are Intel/custom designers). > > To add to the discussion about Structured ASICs (SAs) vs FPGAs vs ASICs that > took place on this thread, SAs save on NRE costs and some backend > tools costs over ASICs. But all other costs, designing, verification, > and testing are the same for all three, SAs, FPGAs, & ASICs. The > reason why people feel that FPGAs take lower time to design and deploy > is because of the size of designs you can fit on a FPGA. Don't be > fooled by the "system gates" that FPGA vendors tout. In reality, > those system gates should be divided by 5 to 10 depending again on > what speed you are running your design at. This means that a 8million > system gate device can fit less than 1 million ASIC gates for high > performance designs and about 2 million ASIC gates at very slow speed. > > In as far as mask costs and when it makes sense to use FPGAs or SAs > instead of ASICs can come down to a simple Excel sheet that has your > design, verification, CAD tools etc cost for each (pretty much the > same for all three, except for back-end tools) + the NRE costs for > each ($0 for FPGAs, $100K-250K for SAs, $0.6-0.8M mask costs at 0.13u > for ASICs) and the cost per chip (very high for FPGAs, lower for SAs > and super low for ASICs) times the volume. (Hope that was not too > much of a ramble). > > Of course, the folks from Xilinx & Altera on this board might/will > disagree with me -- but this is just one man's opinion based on > talking to a lot of FPGA designers and also, some inside info from > marketing folks at Xilinx & Altera ... > > SumitArticle: 74266
Hi, I've connected my FPGA (Xilinx Spartan 2E) to the PCI bus of my PC. The FPGA is powered from a seperate power supply. The problem is, when I turn the power supply to the FPGA off, the FPGA seems to keep running. It must be getting its power from the PCI bus. Only the I/O pins of the FPGA are connected to the PCI bus, so I'm suprised that it keeps running. Has anyone else experienced the same problem? Can it cause any damage and how can I stop it? I need to remove power from the FPGA to clear it (so it can be reprogrammed). Thanks for any help.Article: 74267
Mike, Wow, you've discovered a way to get super low power FPGAs, just disconnect the supply! However, what could be happening is the I/O is feeding the 3.3V supply on your board through the IO protection diodes. Does Vccint get generated from this 3.3V supply? Cheers, Syms. "Mike" <mike@mike.com> wrote in message news:ck1us3$ues$1@newsg2.svr.pol.co.uk... > Hi, > > I've connected my FPGA (Xilinx Spartan 2E) to the PCI bus of my PC. The > FPGA is powered from a seperate power supply. The problem is, when I turn > the power supply to the FPGA off, the FPGA seems to keep running. It must > be getting its power from the PCI bus. Only the I/O pins of the FPGA are > connected to the PCI bus, so I'm suprised that it keeps running. Has anyone > else experienced the same problem? Can it cause any damage and how can I > stop it? I need to remove power from the FPGA to clear it (so it can be > reprogrammed). > > Thanks for any help. > >Article: 74268
But Glen, you can get the whole circuit to a known state by just using strategically
placed resets. Take a simple example of a pipeline that has an accumulator in it.
All that needs to be reset is the registers at the pipeline input (these should be
held at a know value for some known number of clocks), and a reset on the accumulator,
which is needed to clear out the history stored in the accumulator (it won't self
clear regardless of the data coming in because of the feedback loop). If your
pipeline is say 10 clocks long, then holding the reset to the input registers and
accumulator for 10 clock cycles will get the entire circuit to a known state without
having to reset every flip-flop. You can take it a step further by also resetting the
output register and using some delays for the resets so that the operation as viewed
from outside is indistinguishable from a synchronous reset. In that case, the input
register is cleared as long as reset is held. The reset signal is delayed in a shift
register matching the length of the pipeline and tapped where needed to break loops,
and the reset for the output register is handled with a set-reset flip-flop that is
set by the reset input and reset by the delayed reset as the first valid input after
the reset is released reaches the pipeline output.
My point is that you do not have to reset every single flip-flop in the design to
reach a known state as long as you are willing to take a known number of clock cycles
to reach that state.
glen herrmannsfeldt wrote:
> (I believe it is important for testing purposes that a known state be
> reached with a known combination of reset, clocks, and other signals.
>
> It might be that a design would work perfectly well in any of the
> possible reset states, but it wouldn't be testable.
>
> Well, that is mostly for ASICs where test vectors need to be
> supplied to the fab. For FPGAs it might not be necessary,
> though test vector sets are nice to have.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74269Geoffrey Wall wrote: > does any one know if there is a 64 bit windows or linux version of xilinx > ISE available? The Linux/i386 version of ISE 6.2 works on 64bit Linux. I believe that even 32bit programs get another Gig of address space on 64bit Linux. (32bit Linux typically gives a process 2Gig of user mode address space, 64bit Linux gives it 3gig., but my memory may be fuzzy here.) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 74270
Mike wrote: > Hi, > > I've connected my FPGA (Xilinx Spartan 2E) to the PCI bus of my PC. The > FPGA is powered from a seperate power supply. The problem is, when I turn > the power supply to the FPGA off, the FPGA seems to keep running. It must > be getting its power from the PCI bus. Only the I/O pins of the FPGA are > connected to the PCI bus, so I'm suprised that it keeps running. Has anyone > else experienced the same problem? Can it cause any damage and how can I > stop it? I need to remove power from the FPGA to clear it (so it can be > reprogrammed). Sounds to me like a good way to damage the FPGA, and the PCI host as well. There is a /PROG pin on the FPGA for this purpose. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 74271
Hello, A Verilog project I'm working on uses 'include statement in some of its modules (.v files) to reference some pre-defined variables in this manner: 'include "file.vh". The file, "file.vh" is in the same path as the veil modules that use that statement. ISE complains that it "Could not find include file 'file.vh' in spite of copying file.vh to the project directory and adding it to the project source files so that it appears in the "Sources in Project" tab that displays the source hierarchy. What can I do to fix this error w/out having to add all the defined variables to each Verilog module. Thanks, NNArticle: 74272
I did a design a couple years ago in a VirtexE-7 that interfaced to an
Atmel 1GHz 8 bit ADC. IIRC, that ADC output 4 samples at a time (perhaps
there was a matching mux chip). Once inside the FPGA the signal was
mixed and FFT'd. The incoming sample rate was 960MHz. So yes, the
answer is most current FPGAs can handle the throughput with some
clever/careful design. The new crop of FPGAs are considerably faster
than the VirtexE devices.
Alex wrote:
> Hi,
>
> It's not the first time this question has been asked, but I'd like to
> know todays state of art:
> Are their any devices at Altera, Xilinx or others, capabable of
> handling the fast throughput of high-speed ADCs (1 GS), such as
> Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external
> DMUX-device...
> Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines
> per channel.
>
> Thanks,
>
> Alex
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74273Ray Andraka wrote: > But Glen, you can get the whole circuit to a > known state by just using strategically > placed resets. Take a simple example of a pipeline > that has an accumulator in it. > All that needs to be reset is the registers > at the pipeline input (these should be > held at a know value for some known number of > clocks), and a reset on the accumulator, > which is needed to clear out the history > stored in the accumulator (it won't self > clear regardless of the data coming in > because of the feedback loop). (snip) > My point is that you do not have to reset > every single flip-flop in the design to > reach a known state as long as you are willing > to take a known number of clock cycles > to reach that state. Yes. That is included in what I wrote as a known combination of reset and clocks. It gets more complicated if you have memory elements other than pipelines, such as registers in a CPU. While the processor might work just fine with them in a random initial state, testing might not. All these things have to be considered at design time. It might be that they don't add much logic, but they do add to the time it takes to verify the design. After I wrote: >>(I believe it is important for testing purposes >> that a known state be reached with a known combination > of reset, clocks, and other signals. -- glenArticle: 74274
I'm looking for advice and resources to help me learn about hardware design and FPGAs. So far I've done tons of googling, and I've found tons of information about microcontrollers and things like that, but in another newsgroup thread[1] it was suggested that an FPGA might be a better solution for my current goal project: An nes-level gaming 'console'. This is just something I think would be interesting to do, and I realize it won't be the first thing I complete, which is why I'm asking for help getting started with the first steps of thousands that will lead to it's completion. Since I've been doing CS for most of my life(as a hobby, though I'm now working on a CS degree) and I've only recently taken an interest in EE as a hobby, I don't know much at all about electronics or the like. From suggestions in another newsgroup thread[1], I've been reading the recommended books and learning the basic theory and practice, but I think I'm ready to start working on more advanced things as well. I'm also being exposed to VHDL in a Digital Logic(aka boolean algebra) class required for my degree. Really, the class doesn't cover VHDL, but it is covered in the book we're using so I've been learning it during class when I read the book and ignore the incomprehensible professor. I'm looking for a good starter kit for FPGAs. So far, Xilinx's Spartan-3 starter kit seems to be the least expensive kit that includes everything needed to get started. Like I said, I'm still learning electronics, so designing my own board is most likely out my reach at the moment, and I'm a college student so as the cliche goes I don't have tons of money to spend on hobbies. Any suggestions for books, sites to read, FPGA starter kits, etc would be greatly appreciated. [1] = http://groups.google.com/groups?threadm=4781a87e.0409061701.5eef2236%40posting.google.com PS: If you reply via electronic mail, include "comp.arch.fpga" (with or without the quotes) in the subject or it will get filtered to the trash.
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