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statepenn99@yahoo.com (John M) wrote in message news:<bf59e739.0410051257.67b63d89@posting.google.com>... > All, > > I am looking for an efficient hashing algorithm that can be easily > translated to an FPGA. The hash does not have to be cryptographically > secure, as I am just using it for a hash table lookup. Instead, I > need it to run very fast (~25 Million hashes per second). Does anyone > know of any resources where I could find such an algorithm? I have > found a couple CRC-based algorithms, but I am concerned they will > result in too many collisions. Thanks for your help. The hash function used in Java of strings multiplies each byte by 31^n. A multiplication by 31 requires just one adder this means that you can implement it using only one adder in n clock cycles for n input words. Kolja SulimmaArticle: 74226
Naimesh wrote:
> I was doing a project with Actel FPGA ex128 with Libero Platinum Eval
> version software.
>
> in my project I had to use some counters,Multiplexers etc. which I
> wrote myself.
Good work. Writing your own code makes your design
portable and easy to simulate.
> Now as I was a beginner I didnt use the ActGen.
Libero has Synplify synthesis which makes using ActGen
unnecessary in most cases.
> Is it worth the effort to write the code partly by using ActGen macros
> for counter and muxes and etc.
Only if your design fails to fit or meet timing.
The downside to a core generator is that it makes
your design non-portable and harder to simulate.
-- Mike Treseler
Article: 74227I've used Actel's ActGen for numerous modules with good success. Being specific to Actel parts and specific families, you should get better performance than generic VHDL. NOTE: I have had problems with the input bus naming convention they use in their Multiplexers with my simulator. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Naimesh" <naimesh.thakkar@gmail.com> wrote in message news:1097051471.183335.310010@k26g2000oda.googlegroups.com... > Hello, > > I was doing a project with Actel FPGA ex128 with Libero Platinum Eval > version software. > > in my project I had to use some counters,Multiplexers etc. which I > wrote myself. > > Now as I was a beginner I didnt use the ActGen. > > Is it worth the effort to write the code partly by using ActGen macros > for counter and muxes and etc. > > Thanks > Naimesh >Article: 74228
I have the same board with a XC4003 part installed in it. I would be interesed in finding the details of this board and what release of Xilinx's software support this device. Thanks, Derek SimmonsArticle: 74229
Hello again
I hope this is the last time I have to contact the newsgroup concerning the
FSL interface of the Microblaze processor.
I just added a simple Adder modul, which sums up two input signals.
But there is one problem. The first and the second value are always the
same, so the result is 2 times op1. So although I send 2 different values to
my FIFO it only reads out the first one and this two times. Example: 2+3 =
4, 125+3= 250
Here is the corresponding code, i have divided the Adder in a Controller and
Datapath Modul:
Controller: Read is in this case the FSL_S_READ signal, Statemachine starts
in the the IDLE State. Start is the
FSL_S_Exists signal from the FSL interface. And Finish is the FSL0_M_Write!
I have added a Wait Statement where the Read signal is Low for one clock
signal, I tried to adopt it from the FSL Documenation!
comb: process(current_state, start)
begin
finish<= '0';
loada <= '0';
loadb <= '0';
add <= '0';
read <= '0';
case CURRENT_STATE is
when IDLE =>
if start = '1' then
next_state <= STLDA;
read <= '1';
else
next_state <= IDLE;
end if;
when STLDA =>
loada <= '1';
next_state <= WAIT0;
when WAIT0 =>
read <= '1';
next_state <= STLDB;
when STLDB =>
loadb <= '1';
next_state <= ADDS;
when ADDS =>
add <= '1';
next_state <= FINISHS;
when FINISHS =>
finish <= '1';
next_state <= IDLE;
end case;
end process;
sync: process(clk, reset)
begin
if reset = '1' then
current_state <= IDLE;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
Datapath:
comb: process(add)
variable pp: std_logic_vector(width-1 downto 0);
variable pi: integer;
begin
if add = '1' then
pi := conv_integer(unsigned( areg )) + conv_integer(unsigned( breg ));
pp := std_logic_vector(conv_unsigned(pi, width));
end if;
res <= pp;
end process;
sync: process(clk, reset)
begin
if reset = '1' then
dout <= (others => '0');
areg <= (others => '0');
breg <= (others => '0');
elsif clk'event and clk = '1' then
dout <= res;
if loada = '1' then
areg <= din;
elsif loadb = '1' then
breg <= din;
end if;
end if;
end process;
Article: 74230John Smith <user@example.net> wrote in message news:<4163075F.4080208@example.net>... > Viswan wrote: > > hi, > > > > I have a doubt on using inout ports in FPGA design. I am implementing > > an application on FPGA, that should be interfaced to SHT71(Sensirion > > humidity and temperature sensor). My FPGA gets the value of > > temperature and humidity from the sensor and calculates > > moisture(output) using certain equations. > > > > I have designed the arithmetic unit required to calculate the moisture > > value in VHDL, and synthesized on to FPGA. But now I have to > > interface this unit to the sensor(SHT71), and the sensor needs to have > > a controller(any microcontroller as specified in the SHT71 datasheet) > > to control its operations and get the values of temperature and > > humidity. The sensor has a bidirectional data signal as one of the > > ports, and that should be connected to the controller to send and > > receive data. I want to implement the controller also on the same > > FPGA itself. But is it possible? Is it possible to handle a > > bidirectional port from an FPGA to send and receive data? I am using > > Virtex XCV800 HQ240I. Or is it suggestible to use any standard > > microcontroller as an interface between sensor and FPGA? > > > > Any suggestion on this is highly appreciated. > > Do you really need an FPGA to do the job? Wouldn't a simple uC do the > trick cheaper and easier? Unless you need the FPGA anyway for some other > stuff. (or if this is homework for an FPGA class ;) > > Anyway, this is certainly doable in FPGA (it's an overkill, actually) > and bi-directional I/O is not an issue. As John mentioned, the interface > can be done easily with a simple FSM. > > J.S. > > > Thanks hi, thanks a lot for all your suggestions. they are really helpful. as i mentioned already, I have a lot of arithmetic operations to be done after obtaining the values of temperature and humidity from the sensor. I need to go through some complex floating point equations which involve addition, subtraction, multiplication and division. So I chose FPGA. I have to perform around 15 multiplications, 4 divisions, 4 additions and 2 subtractions.. would microcontroller be fine for those stuff? Thanks a lot V.N.Article: 74231
Hi, First have you simulated this to see that the waveform is correct? Secondly you don't check for an Exists signal before loading breg. We can take this offline if you want. Göran Roger Planger wrote: > Hello again > > I hope this is the last time I have to contact the newsgroup concerning the > FSL interface of the Microblaze processor. > I just added a simple Adder modul, which sums up two input signals. > > But there is one problem. The first and the second value are always the > same, so the result is 2 times op1. So although I send 2 different values to > my FIFO it only reads out the first one and this two times. Example: 2+3 = > 4, 125+3= 250 > > Here is the corresponding code, i have divided the Adder in a Controller and > Datapath Modul: > Controller: Read is in this case the FSL_S_READ signal, Statemachine starts > in the the IDLE State. Start is the > FSL_S_Exists signal from the FSL interface. And Finish is the FSL0_M_Write! > I have added a Wait Statement where the Read signal is Low for one clock > signal, I tried to adopt it from the FSL Documenation! > > comb: process(current_state, start) > begin > finish<= '0'; > loada <= '0'; > loadb <= '0'; > add <= '0'; > read <= '0'; > case CURRENT_STATE is > when IDLE => > if start = '1' then > next_state <= STLDA; > read <= '1'; > else > next_state <= IDLE; > end if; > when STLDA => > loada <= '1'; > next_state <= WAIT0; > when WAIT0 => > read <= '1'; > next_state <= STLDB; > when STLDB => > loadb <= '1'; > next_state <= ADDS; > when ADDS => > add <= '1'; > next_state <= FINISHS; > when FINISHS => > finish <= '1'; > next_state <= IDLE; > end case; > end process; > > sync: process(clk, reset) > begin > if reset = '1' then > current_state <= IDLE; > elsif clk'event and clk = '1' then > current_state <= next_state; > end if; > end process; > > Datapath: > > comb: process(add) > variable pp: std_logic_vector(width-1 downto 0); > variable pi: integer; > begin > if add = '1' then > pi := conv_integer(unsigned( areg )) + conv_integer(unsigned( breg )); > pp := std_logic_vector(conv_unsigned(pi, width)); > end if; > res <= pp; > end process; > > sync: process(clk, reset) > begin > if reset = '1' then > dout <= (others => '0'); > areg <= (others => '0'); > breg <= (others => '0'); > elsif clk'event and clk = '1' then > dout <= res; > if loada = '1' then > areg <= din; > elsif loadb = '1' then > breg <= din; > end if; > end if; > end process; > >Article: 74232
Some additional thing: The clock_divider is synchronous! Rgds AndréArticle: 74233
I use QuartusII version 4.1 SP2Article: 74234
Hello, I have an input clock of 125MHz coming to VirtexII device. I want to derive 80MHz clock from it. The way I wanted to go is to use CLKFX output with 16/25 (M/D) factor. Can I do this without violating timing requirements for the DCM? Both the input and output frequencies are within allowed range and I get no warnings neither from architecture wizard nor from online CLKFX jitter calculator, however I'm not fully understand the sentence from user guide ug002: "For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note that M and D values have no common factors and hence cannot be reduced). The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = 1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far outside the range of the input frequency." Does this mean that I cannot use 16/25 factor in my case? -- RobertP.Article: 74235
RobertP schrieb am 06.10.2004 16:16: > "For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note > that M and D values have no common factors and hence cannot be reduced). > The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = > 1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far > outside the range of the input frequency." > > Does this mean that I cannot use 16/25 factor in my case? There should not be any problems with that. The paragraph from the user guide is just supposed to tell you that you can do a COMBINED multiply by 16 and divide by 25, even if the SINGLE operations would violate the allowed frequency ranges. That means even though you cannot multiply 125MHz*16=2000MHz or divide 125MHz/25=5MHz on its own, you can do the COMBINED operation. cu, SeanArticle: 74236
> Imaging a MP3 player where only the gates being used are being clocked and > even then... only at the rate they are being used! You don't necessarily have to use async logic to achieve this. Fine grained clock-gating can get you most of these power savings, but this is something that so far can only be done in an ASIC. However, as far as battery operation is concerned, for quite a few applications it's not so much the dynamic power that is a problem, but the huge static power consumption of FPGAs. Here we talking the difference between a FPGA running for a few hours, compared to an ASIC running for a couple of years. Cheers, JonBArticle: 74237
You need the XACT hardware & Peripherals Guide, but good luck finding
one. It was printed in 1994. It is a white paperback book about 9"tall
x 6" wide x 1/2" thick. You'll also need the old XACT tools, as the
straight 4003 (not the 4003E) has not been supported in any of the M
series tools. Good chance the XACT won't run on a recent computer nor
operating system either. When all is said and done, it may be cheaper
to pick up a board with a current FPGA on it and use the current tools.
You'll certainly get more capability out of a modern FPGA.
Derek Simmons wrote:
> I have the same board with a XC4003 part installed in it. I would be
> interesed in finding the details of this board and what release of
> Xilinx's software support this device.
>
> Thanks,
> Derek Simmons
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74238Oh you are great Goeran, I have just checked now for the exists signal a second time and it seems like that my adder works!! Awesome! Now I will add my IP to be sure, that not the processor is executing the addition :) Thanks so much! Cheers R "Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:ck0tpj$60d1@cliff.xsj.xilinx.com... > Hi, > > First have you simulated this to see that the waveform is correct? > Secondly you don't check for an Exists signal before loading breg. > > We can take this offline if you want. > > Göran > > > Roger Planger wrote: >> Hello again >> >> I hope this is the last time I have to contact the newsgroup concerning >> the FSL interface of the Microblaze processor. >> I just added a simple Adder modul, which sums up two input signals. >> >> But there is one problem. The first and the second value are always the >> same, so the result is 2 times op1. So although I send 2 different values >> to my FIFO it only reads out the first one and this two times. Example: >> 2+3 = 4, 125+3= 250 >> >> Here is the corresponding code, i have divided the Adder in a Controller >> and Datapath Modul: >> Controller: Read is in this case the FSL_S_READ signal, Statemachine >> starts in the the IDLE State. Start is the >> FSL_S_Exists signal from the FSL interface. And Finish is the >> FSL0_M_Write! >> I have added a Wait Statement where the Read signal is Low for one clock >> signal, I tried to adopt it from the FSL Documenation! >> >> comb: process(current_state, start) >> begin >> finish<= '0'; >> loada <= '0'; >> loadb <= '0'; >> add <= '0'; >> read <= '0'; >> case CURRENT_STATE is >> when IDLE => >> if start = '1' then >> next_state <= STLDA; >> read <= '1'; >> else >> next_state <= IDLE; >> end if; >> when STLDA => >> loada <= '1'; >> next_state <= WAIT0; >> when WAIT0 => >> read <= '1'; >> next_state <= STLDB; >> when STLDB => >> loadb <= '1'; >> next_state <= ADDS; >> when ADDS => >> add <= '1'; >> next_state <= FINISHS; >> when FINISHS => >> finish <= '1'; >> next_state <= IDLE; >> end case; >> end process; >> >> sync: process(clk, reset) >> begin >> if reset = '1' then >> current_state <= IDLE; >> elsif clk'event and clk = '1' then >> current_state <= next_state; >> end if; >> end process; >> >> Datapath: >> >> comb: process(add) >> variable pp: std_logic_vector(width-1 downto 0); >> variable pi: integer; >> begin >> if add = '1' then >> pi := conv_integer(unsigned( areg )) + conv_integer(unsigned( breg )); >> pp := std_logic_vector(conv_unsigned(pi, width)); >> end if; >> res <= pp; >> end process; >> >> sync: process(clk, reset) >> begin >> if reset = '1' then >> dout <= (others => '0'); >> areg <= (others => '0'); >> breg <= (others => '0'); >> elsif clk'event and clk = '1' then >> dout <= res; >> if loada = '1' then >> areg <= din; >> elsif loadb = '1' then >> breg <= din; >> end if; >> end if; >> end process;Article: 74239
Great that it works. I have been doing some FSL modules and if you need more help optimizing your functions, just send me an email. Göran Bilski Roger Planger wrote: > Oh you are great Goeran, I have just checked now for the exists signal a > second time and it seems like that my adder works!! > > Awesome! Now I will add my IP to be sure, that not the processor is > executing the addition :) > > Thanks so much! > > Cheers > R > > "Göran Bilski" <goran.bilski@xilinx.com> wrote in message > news:ck0tpj$60d1@cliff.xsj.xilinx.com... > >>Hi, >> >>First have you simulated this to see that the waveform is correct? >>Secondly you don't check for an Exists signal before loading breg. >> >>We can take this offline if you want. >> >>Göran >> >> >>Roger Planger wrote: >> >>>Hello again >>> >>>I hope this is the last time I have to contact the newsgroup concerning >>>the FSL interface of the Microblaze processor. >>>I just added a simple Adder modul, which sums up two input signals. >>> >>>But there is one problem. The first and the second value are always the >>>same, so the result is 2 times op1. So although I send 2 different values >>>to my FIFO it only reads out the first one and this two times. Example: >>>2+3 = 4, 125+3= 250 >>> >>>Here is the corresponding code, i have divided the Adder in a Controller >>>and Datapath Modul: >>>Controller: Read is in this case the FSL_S_READ signal, Statemachine >>>starts in the the IDLE State. Start is the >>>FSL_S_Exists signal from the FSL interface. And Finish is the >>>FSL0_M_Write! >>> I have added a Wait Statement where the Read signal is Low for one clock >>>signal, I tried to adopt it from the FSL Documenation! >>> >>> comb: process(current_state, start) >>> begin >>> finish<= '0'; >>> loada <= '0'; >>> loadb <= '0'; >>> add <= '0'; >>> read <= '0'; >>> case CURRENT_STATE is >>> when IDLE => >>> if start = '1' then >>> next_state <= STLDA; >>> read <= '1'; >>> else >>> next_state <= IDLE; >>> end if; >>> when STLDA => >>> loada <= '1'; >>> next_state <= WAIT0; >>> when WAIT0 => >>> read <= '1'; >>> next_state <= STLDB; >>> when STLDB => >>> loadb <= '1'; >>> next_state <= ADDS; >>> when ADDS => >>> add <= '1'; >>> next_state <= FINISHS; >>> when FINISHS => >>> finish <= '1'; >>> next_state <= IDLE; >>> end case; >>> end process; >>> >>> sync: process(clk, reset) >>> begin >>> if reset = '1' then >>> current_state <= IDLE; >>> elsif clk'event and clk = '1' then >>> current_state <= next_state; >>> end if; >>> end process; >>> >>>Datapath: >>> >>> comb: process(add) >>> variable pp: std_logic_vector(width-1 downto 0); >>> variable pi: integer; >>> begin >>> if add = '1' then >>> pi := conv_integer(unsigned( areg )) + conv_integer(unsigned( breg )); >>> pp := std_logic_vector(conv_unsigned(pi, width)); >>> end if; >>> res <= pp; >>> end process; >>> >>> sync: process(clk, reset) >>> begin >>> if reset = '1' then >>> dout <= (others => '0'); >>> areg <= (others => '0'); >>> breg <= (others => '0'); >>> elsif clk'event and clk = '1' then >>> dout <= res; >>> if loada = '1' then >>> areg <= din; >>> elsif loadb = '1' then >>> breg <= din; >>> end if; >>> end if; >>> end process; > > >Article: 74240
Thanks for quick response. I looked into Spartan3 xapp462. It confirms what you are telling (this time without any doubts). -- RobertP.Article: 74241
Okay thats tremendous, I think a little bit later on I will come back to this offer, when I extend the function of my IP Thanks a lot Roger "Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:ck11il$6fo3@cliff.xsj.xilinx.com... > Great that it works. > > I have been doing some FSL modules and if you need more help optimizing > your functions, just send me an email. > > Göran BilskiArticle: 74242
In article <416403CA.9FE90802@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >You need the XACT hardware & Peripherals Guide, but good luck finding >one. It was printed in 1994. It is a white paperback book about 9"tall >x 6" wide x 1/2" thick. You'll also need the old XACT tools, as the >straight 4003 (not the 4003E) has not been supported in any of the M >series tools. Good chance the XACT won't run on a recent computer nor >operating system either. When all is said and done, it may be cheaper >to pick up a board with a current FPGA on it and use the current tools. >You'll certainly get more capability out of a modern FPGA. Especially when the Spartan 3 starter kit is a $100 system. Or if you have a gameboy, the Charmed Labs XPort board is $150 or so. The old 4000 boards were good for student projects back when I was an undergrad (our class project then was a sample-based MIDI synthesizer in a 4005 on the board), but that was, umm, gosh, nearly a decade ago. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 74243
hol wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > In digging around a few enthusiast websites, I think I > the normal flow requires SNIP I agree with some of the posters that you may not need an OS. If you decide to use one you should look at MicroC/OS-II (www.ucos-ii.com) It has been ported to both PowerPC and MicroBlaze. If you can't find the particular flavor of PPC on the uCOS ports page we can help you with custom ports. -- Scott Validated Software Corp.Article: 74244
The magic of google says... http://www.seas.upenn.edu/ese/rca/pchardware/demoboard/demoboard.html regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. "EdiBen612" <ediben612@aol.com> wrote in message news:20041005011102.18603.00001958@mb-m07.aol.com... > I got an old version of xilinx demo board, XC40XX-PC84. I can't find a user > manual or document to use it with Xilinx software. I'm a student learner and I > really need your help. Can anyone send me a link or documentation on this Demo > board. My email is: hb11us@yahoo.com > Thank U. >Article: 74245
Kevin, All of the outputs for the DCM are generated in the "outgen" block, which uses matched paths and devices, fully buffered. All of the outputs are derived from the delay line, so all of the timing is related. That is how we can do it. The skew is +/- 100 ps (as I recall) to acount for all the mismatches possible at the output of the DCM. Now going into the BUG trees (which is fully buffered, so loads don't count) puts another uncertainty on the values, but from BUFG to BUFG these are also matched pretty well (less than a few tens of ps mismatch). The flight time along the BUFG tree will vary, and if you get off near the center, or get off in the top right hand corner on a large part (ie 2VP100), you may also have 500 to 700 ps of time difference between these two nets. Add system jitter, and DCM jitter to it, and if you are not careful, at a high frequency, you might get the result you did. On the other hand, 'being careful' means having to relationally place things, or hand place things, so that may not be something you want to do (I wouldn't unless I had to). One very common misconception is that using CLK2X FB is somehow better than CLK0 FB: it is not. There is no difference specification wise. The CLK2X gets divided by two just before the phase detector, so any belief that it is better matched somehow assumes we did a perfect job matching a /2 to a straight thru path (which, again, we do our best). If you believe the CLK2X is better, then why do you not believe the 'outgen' is just as good? I am all for full synchronous design, (simpler, easier to verify), but it seems that folks keep finding ways to use the DCM in what I might call "isochronous design." Austin Kevin Neilson wrote: > I would answer that NO, the skew has not been eliminated. The literature > gives the impression that all the DCM outputs are perfectly phase-aligned > when it appears to be just not true. How can it be? The DCM can only > account for the delay across the BUFG *in its feedback path*. That means > only the CLK0 or CLK2X can be perfectly phase-aligned, and not even the > latter in the V2Pro because of the erratum disallowing the use of CLK2X for > the feedback. The other outputs (CLKFX, CLKDV) have different loads and > should have different delays across their respective BUFGs. I don't see how > they could possibly be aligned with the input. > > I recently had a problem on a V2Pro trying to transfer data from a 2X domain > to a 1X domain, where both domains were driven by DCMs. The transfers had > multiple errors indicating that the skew between the domains was too large. > I resolved the problem by transferring across domains away from the edge of > the receiving domain. Everything I have read implies that this isn't > necessary. > > Creating a copy of the slow clock in the fast domain is the method I use. > The slow clock has to be sampled; actually I think I sampled the CLK90 or > one of those to ensure I meet setup. With the copied clock I can always do > the transfer in the middle of the slow clock cycle (or, in the poster's > case, on the first third of the slow clock's cycle). > > The DCMs work very well; I just think that the caveats for their use are not > well-specified. An app-note explaining the clock-copying method Ray > describes would be very helpful, if such a note does not yet exist. > -Kevin > > "Ray Andraka" <ray@andraka.com> wrote in message > news:41632CBB.AD3368E0@andraka.com... > >>Austin, >> >>Has the possibility of skew between the 1x and Nx clock due to loading and > > input > >>jitter been eliminated then? I had a problem back when SpartanII was > > first > >>released with a design where the incoming clock had enough jitter on it >>(introduced apparently by switching of outputs on the same bank as the > > clock pin) > >>and vastly different loading on the 1x and 2x clocks so that I had > > problems > >>crossing clock domains where I had a flip flop in one domain driving the > > direct > >>input of a flip-flop in the other domain via the direct slice to slice > > connect > >>inside a clb. Ever since then, I have been very careful about crossing > > domains > >>even if they are generated by the same DLL/DCM. >> >>One way to do it is to make a copy of the slower clock in the faster clock > > domain, > >>and then use that for clock enables to make sure the signal is sensed away > > from > >>the edge where it changes. >> >> >> >>Austin Lesea wrote: >> >> >>>Brad, >>> >>>All DCM outputs are phase aligned. >>> >>>So, for example, if you use the CLK0 output, and the CLKFX output with >>>M=3/D=1, every time CLK0 has a rising edge, there will be a rising edge >>>for the CLKFX +/- the jitter of the DCM. >>> >>>Or saying it differently, every third edge of the CLKFX corresponds to a >>>CLK0 edge. >>> >>>That is why the DCM is useful, is that it phase aligns everything to >>>known phases and known phase alignments. >>> >>>This accuracy in alignment is covered in the DCM specifications, as the >>>skew between DCM outputs, in the datasheet. >>> >>>Austin >>> >>>Brad Smallridge wrote: >>> >>>>Is there any "how to" documents on how to negotiate a two clock > > domain? I > >>>>want to run an SRAM with a 3X clock and have everything else run > > slower. > >>>>One of my issues is how the slower clock domain knows the phase of the >>>>faster domain, such that data can come across the clock domain, from > > fast to > >>>>slow, at the right time. If I have a clock divider, such issues can be >>>>resolved in the logic, but I am using a DCM, and the internal workings > > don't > >>>>seem to be as available, that is you just have two outputs, one fast, > > one > >>>>slow. >>>> >>>>I also need to simulate this in ModelSim. I haven't yet even seen the > > fast > >>>>clock signal appear in the signals or waveform generator. Do I need > > an > >>>>upgrade? Barring this, I suppose I could develop a component with the > > core > >>>>design and then drive it with a VHDL module with a fast clock and > > another > >>>>clock divided by three. Is this a good plan? >>>> >>>> >>>> >>>> >> >>-- >>--Ray Andraka, P.E. >>President, the Andraka Consulting Group, Inc. >>401/884-7930 Fax 401/884-7950 >>email ray@andraka.com >>http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759 >> >> > > >Article: 74246
Brian,
I respect you opinion, but I do not agree with you ('insults and
opinions' & FUD?).
I have never been silent on an issue.
I have been wrong, and admitted it on occasion.
And, I believe I have been right, and had folks disagree with me.
But never silent.
Austin
Brian Davis wrote:
> John H wrote:
>
>>>That is right. Did you make the same comment to Austin?
>>
>>Honestly, no. To me, you appear to be the one predisposed to
>>being argumentative in the posts back and forth.
>>
>
>
> I'd have to side with Rick on this one - Austin's 'bad hair day'
> comment is what prompted Rick's response.
>
> Personally, I can easily ignore Austin's marketing spiels.
>
> My real beef with Austin is when he flames up an accurate technical
> post with an insult-and-opinion laden response, for no apparent reason
> other than to spread FUD when someone has taken the time and effort
> to document tool or device problems about which Xilinx has been less
> than forthcoming.
>
> He makes lots of noise when you point out the flaws in his reasoning,
> yet when you pin him down by asking a detailed technical question, he
> becomes strangely silent.
>
> Brian
Article: 74247Mea culpa! I was the one who added this sentence into the manual, in order to really clarify the issue. Apparently I was not clear enough... So: In a combined multiply-divide operation, only the input frequency and the final output frequency must fall into the specified ranges. Multiplication and division are not performed in sequence, but really as a simultaneous combined mathematical operation, so the DCM never sees the result of multiplication alone, or of division alone. This is not intuitively obvious, and a circut description would be far too complex, so we have to explain it in English, and you must take our word for it. Well, you will also experience that it works. :-) Peter Alfke > From: RobertP <r_p_u_d_l_i_k@poczta.onet.pl> > Organization: news.onet.pl > Newsgroups: comp.arch.fpga > Date: Wed, 06 Oct 2004 16:16:09 +0200 > Subject: DCM and CLKFX - is this allowed? > > Hello, > I have an input clock of 125MHz coming to VirtexII device. I want to > derive 80MHz clock from it. > The way I wanted to go is to use CLKFX output with 16/25 (M/D) factor. > Can I do this without violating timing requirements for the DCM? > Both the input and output frequencies are within allowed range and I get > no warnings neither from architecture wizard nor from online CLKFX > jitter calculator, however I'm not fully understand the sentence from > user guide ug002: > > "For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note > that M and D values have no common factors and hence cannot be reduced). > The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = > 1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far > outside the range of the input frequency." > > Does this mean that I cannot use 16/25 factor in my case? > > -- > RobertP.Article: 74248
Viswan wrote: > thanks a lot for all your suggestions. they are really helpful. as i > mentioned already, I have a lot of arithmetic operations to be done > after obtaining the values of temperature and humidity from the > sensor. I need to go through some complex floating point equations > which involve addition, subtraction, multiplication and division. So > I chose FPGA. > I have to perform around 15 multiplications, 4 divisions, 4 additions > and 2 subtractions.. > would microcontroller be fine for those stuff? This depends really on how often you have to do this. In other words, how much time do you have to do the calculations? I'd suppose that the temperature and humidity values change quite slowly and it does not make sense to update the values more than once per second. Or even once per minute? You can do quite a lot of number crushing in a microcontroller in one second. I think that using an FPGA for this case is OK for educational purposes, but for a real life case it does not make sense. J.S. > > Thanks a lot > V.N.Article: 74249
Bruce Sam wrote: > I have never used Xilinx's product before.In some articles are said > the Xilinx's silicon is better than Altera.Is it realy?I'm only a > university student and not have enough money to validate it.Can give > some advice to me? Both Altera and Xilinx have free tools available. Take some test design and do the synthesis, P&R and static timing analysis for both vendors. Make sure to select target devices so that the comparison is fair enough. This does not cost you any $$, only some time and effort. And you also get to see the good and bad side of the design flow of both vendors. If you are not really pushing the limits of the latest FPGAs in your design, a smooth and intuitive tool flow is much more relevant than comparing "whose silicon is best". IMHO at least. HTH J.S.
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