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John_H wrote: > > Please try to make your points, not argue them. It's typical of your posts > to others to be informative as it is with Austin's. If either of you come > to a post by the other as a challenge to his manhood, the conversation won't > be productive for anyone. Do you recall the post I responded to? Austin is prone to making personal comments bordering on redicule. His "technical" points often come off as posturing rather than rational discussion. My beef with Austin is that he refuses to acknowledge (or is unable to understand) these points. > It takes two to tango. That is right. Did you make the same comment to Austin? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74151
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4161D8A3.38B5DD51@yahoo.com... > John_H wrote: > > It takes two to tango. > > That is right. Did you make the same comment to Austin? Honestly, no. To me, you appear to be the one predisposed to being argumentative in the posts back and forth. The usenet does not allow a "proper" form of factual documentation that is typically left to footnotes or bibliography in industry journals and academic papers. The statements made by any individuals on this forum as "fact" should be taken by the reader with a grain of salt. Caveat emptor and all that. I think most readers realize that if you read it on the internet it isn't *necessarily* true. Even the most informed people with the best of intents will not have a complete documentation trail back to the origins of their knowledge. It seems that if this trail is not stated, you're assuming that Austin - as opposed to any typical poster - is "talking out of his hats." This is my view. I do notice that Austin may get frustrated by people stating that he's wrong about what he posts, probably half of which comes from rickman. In the previous post I did mention the frustrations as being the only detractor from complete professionalism and I'm assuming that that comment is being considered in the whole of his usenet experience. Personally, I don't consider it a negative at all. Stubbornness is tough for me to deal with as well.Article: 74152
"Thomas Reinemann" <thomas.reinemann@masch-bau.uni-magdeburg.de> wrote in message news:cjrehb$mp1$1@fuerst.cs.uni-magdeburg.de... > Hello, > > is there a possibility to use the Chipscope to inspect the content of > BlockRam? > > Bye Tom only if you implement your own core that you can connect to ICON you should used your own application to inspect the content as well. Both are doable (we have done it). it is unfortunate that ChipScope Pro does not have the memory load/inspect function built in like SignalTap has :( anttiArticle: 74153
"Jock" <ian.mcneil@nospam.com> wrote in message news:cjrr8p$bt5$1@rdel.co.uk... > Is it possible to take the FPGA.hex file, for example and given that you > know the device, reverse-engineer it into either it's CLB map or back to > it's high-level HDL code? everything is possible if there is a commercial gain from doing it. usually there isnt. anttiArticle: 74154
I got an old version of xilinx demo board, XC40XX-PC84. I can't find a user manual or document to use it with Xilinx software. I'm a student learner and I really need your help. Can anyone send me a link or documentation on this Demo board. My email is: hb11us@yahoo.com Thank U.Article: 74155
Hi Steve, > Danger, Danger, Will Robinson, my B.S. sensors have detected significant > marketing content. :-) I have presented some of this (or similar) data at an academic conference. I would not have done so if I could not vouch for its veracity. Of course, I would not be talking about it if it were not good news, so in that sense it's marketing :-) > Like Altera, Xilinx marketing has a benchmark suite showing that Spartan-3 > performs better than Cyclone (shocking, I know). My own personal suite uses > more typical customer designs and shows a healthy mix of wins and losses, > very much depending on the characteristics of the design. I agree that benchmarking results can be made to show what you would like. And in our results, we too see a few poor performers. Honestly, in the end averages and sweeps mean nothing to an end user; all they care about is that for their design, they get the performance they want/need. That's why the best thing a user can do is run Cyclone, and run Spartan-3, using the freely available tools. I would love nothing more than for every person considering Spartan out there to do this -- I firmly believe that 9/10 will be very happy with the results. > If Cyclone were _really_ 80% faster on _average_ than Spartan-3 comparing > fastest to fastest speed grades, do you _really_ think that this real-world > customer design, using out-of-the-box, default "push-button" settings, is > all that pathological? The two out-of-the-box results were roughly the same > when you compare the slowest speed grades for each family. Yes. As I have previously posted, this design appears to fall into a known category of designs that exhibit a much smaller performance advantage; and still it seems to exhibit a ~15% advantage. I'll also take a deeper look at the design when I'm back at the office later in the week to make sure nothing weird is going on in Quartus -- always good to understand our failures. BTW, the numbers from http://www.altera.com/products/devices/performance/lowcost_performance/per-lowcost_performance_fpga.html I believe are most relevant to users are the "best effort" DSE vs. Iteration at 70% fastest-to-fastest; I'd remove the seed-sweep aspect of DSE and instead include only the Physical Synthesis Optimizations which give most of the DSE gain. This should still end up at around a ~65% advantage for Cyclone vs. Spartan-3. > This is further borne out when you consider that Xilinx chose to have only > two speed grades for Spartan-3. For Xilinx devices, a speed grade > represents about a 15% speed difference. > Cyclone -6 speed grade (fastest of 3 speed grades): 98 MHz > Spartan-3 -5 speed grade (fastest of 2 speed grades): 82 MHz > 15% over Spartan-3 -5 would result in 96.5 MHz Do you have a faster speed grade? Are you implying you could choose to release and reliably yield one? Until then, I fail to see how this argument is relevant. Happy Marketeering :-) Paul Leventis Altera Corp.Article: 74156
Hi, We have a VirtexPro40 on a PCI-Express board. Right now we want to write some rtl to test the RocketIO inside of the FPGA. Since I am new to this area, can anyone suggest some plan for testing. we have eight LED connected to the FPGA. Thanks. JinArticle: 74157
"zg" <zohargolan@hotmail.com> wrote in message news:e24ecb44.0410041000.52c773c2@posting.google.com... > Hi david, > > Apperently we have similar problems. > I am designing my own peripheral that needs to read/Write a word in > every clock cycle. This peipheral is connected to the SDRAM controller > as a master on the Avalon bus. What I see in simulation, when I am > connecting to the SDRAM controller, is bursts of 2 words and then 2 or > 3 clocks delay etc. > I think the difference between my application (and I guess yours too) > and Kenneth's, is that Kenneth is using a DMA to burst data whereis we > are using a simple master to slave transactions. Maybe by > instantiating the DMA in the SOPC builder, the SDRAM contoller is > configured to longer bursts. I started develpoing my own SDRAM > controller that will support full page bursts, but if I will find a > way the SDRAM controller is working, I might return to it. > > Zohar I'm not using the standard DMA peripheral, but I am using intelligent masters. Both the reader and the writer are designed to work with continuous bursting - they feed to or from fifos with a depth of 256 32-bit words. In each case, the other end of the fifo is slower than this - the idea is to use bursting so that they occupy the minimum bus bandwidth. When running them on a different board with a fast synchronous ram, each runs one transfer per cycle (the reader is latency-aware). > > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:<cjrh8o$ck5$1@news.netpower.no>... > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message > > news:10lnrtjlg7sff75@news.supernews.com... > > > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message > > > news:aaaee51b.0409290819.a6020e5@posting.google.com... > > > > Hi all [SOPC users], > > > > > > > > is there a way a can configure the read burst length of the > > > > standard SDRAM controller within SOPC 4.1? > > > > > > > > Best Regards > > > > Markus > > > > > > Hi Markus, > > > > > > You might try asking this over on the Nios Forum (www.niosforum.com). I'd > > > like to know the answer as well. I looked through the controller's > > > class.ptf file and even the verilog source and don't see anything. > > > > > > On writes however, I'm getting bursts of at least 480 long words at one > > > clock per word. (my system is running at 75MHz) > > > > > > > Did you have to do anything special to achieve that? I have a custom > > peripheral that is writing as fast as it can to the sdram, but I'm getting > > one 32-bit write every 3 clocks. With the prototype system I have at the > > moment, that's good enough, but I'd like to improve on it when we start > > making the real thing. When reading, I'm getting one read every 2 clocks - > > again, it's not ideal but it works. I'd expect one read/write per clock for > > most of the burst, with some waits while changing banks or refreshing. > > > > Also, my reader and writer peripherals are independant, so sometimes they > > coincide. The Avalone bus arbitration apparently cannot take bursting into > > account, and swaps between the two accesses. Is there any way this can be > > improved upon, or do I have to implement my own mini-arbitrator to control > > the two peripherals?Article: 74158
"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0410041334.4b0bd5b1@posting.google.com... > > Did you have to do anything special to achieve that? I have a custom > > peripheral that is writing as fast as it can to the sdram, but I'm getting > > one 32-bit write every 3 clocks. With the prototype system I have at the > > moment, that's good enough, but I'd like to improve on it when we start > > making the real thing. When reading, I'm getting one read every 2 clocks - > > again, it's not ideal but it works. I'd expect one read/write per clock for > > most of the burst, with some waits while changing banks or refreshing. > > > > Also, my reader and writer peripherals are independant, so sometimes they > > coincide. The Avalone bus arbitration apparently cannot take bursting into > > account, and swaps between the two accesses. Is there any way this can be > > improved upon, or do I have to implement my own mini-arbitrator to control > > the two peripherals? > > Hi David, > > There are a number of factors that affect SDRAM performance in the > general sense. Typically you'll achieve best performance (approaching > one clock per word read or write) if the accesses to SDRAM that are > presented by your peripheral are burst-like. That is, you are reading > from or writing to sequential accesses without interruption; this > applies to our SDRAM controller. The transfers should be optimal (except when the reader and writer coincide, or another master uses the same memory). I've tested the reader on a board with a synchronous ram, and it runs one transfer per cycle (it is latency-aware). I haven't done as intensive testing on the write master, but it should work fine at one transfer per clock. I've got a few things still to look at. My design is purely synchronous on the rising edge of the system clock - perhaps the waitRequest signal is comming for a short glitch and is being captured as high. So I've got a bit of testing with an oscilliscope to do first - signalTap uses the same clock to capture bits, and therefore would suffer from the same problem. > Even when transactions are optimal, you'll still face the occasional > bank-switch delay when your address causes a bank changes, and of > course, the inevitable refresh delay every so often. > I'm aware of that, and it's not a problem. I also have the Nios II program and data in the same memory device, so that will grab occasional cycles (not many, since the Nios has cache and is busy-waiting during the transfers). > By contrast "thrashing" SDRAM, like thrashing a microprocessor cache, > will have negative performance consequences... by thrash I mean > accesses that are all over the place, requiring the SDRAM controller > to take time switching banks continuously. > > To address your concerns: first, we have some enhancements to Avalon > in the works that will address a lot of these problems for the case > you present (wanting to achieve burst-performance between multiple > peripherals). If the results you're getting are good enough for now, > I'd suggest waiting for the next SOPC Builder release as it will > include these Avalon enhancements. > Sounds good - that should save me from handling the overlap between the reader and writer (and other masters). I have fifos connected to both bursting masters, giving me a fair amount of slack - my main interest in bursting is to cut downt the bus time used to fill/empty the fifos. > If you need better performance right now with your setup, feel free to > send me an email and I'd be happy to give you a few pointers (about > avalon arbitration and a couple other things) that may help. > I think I have a fair overview of the arbitration - conflicts when both masters want the bus at the same time is not by biggest problem, and the enhancements you're planning to SOPC Builder will help there. It's more the bursting that I haven't got 100% yet. I suppose another possibility for me would be to use a standard DMA component to transfer between the fifo and the main memory, with a little component inbetween to act as a Avalon slave tied to the fifo and changing "fifo used" information into streaming control signals. Do you think it would be easier to get full-speed bursting using the standard DMA component? David david at westcontrol dot com > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 74159
"Ben Twijnstra" <btwijnstra@chello.nl> wrote in message news:Soj8d.3066$Ye1.2891@amsnews05.chello.com... > Kenneth Land wrote: > > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message > > news:aaaee51b.0409290819.a6020e5@posting.google.com... > >> Hi all [SOPC users], > >> > >> is there a way a can configure the read burst length of the > >> standard SDRAM controller within SOPC 4.1? > >> > >> Best Regards > >> Markus > > > > Hi Markus, > > > > You might try asking this over on the Nios Forum (www.niosforum.com). I'd > > like to know the answer as well. I looked through the controller's > > class.ptf file and even the verilog source and don't see anything. > > > > On writes however, I'm getting bursts of at least 480 long words at one > > clock per word. (my system is running at 75MHz) > > > > Ken > > Have you guys looked at increasing the arbitration priority for the SDRAM > controller? The NIOS needs to fetch opcodes every once in awhile. > Yes - it's not the source of the problem (for me, anyway). The Nios is running an empty loop most of the time during these bursts, and it's configured with instruction cache. > Ben >Article: 74160
Hi, I have the following problem: When I archive my project on disk H there are user libraries defined for the project which are also on H. When I run the .qar-file everything is ok (I have copied the archived project to disk E). But how can I manage that the user libraries are not linked to H anymore? I mean if I want to safe a running system and make some tests on the design on H or on the user libraries on H then I would not have the original design anymore. That is how can I freeze everything of the original design? I would appreciate your help. RgdsArticle: 74161
Antti Lukats <antti@case2000.com> wrote: : Quote from Xilinx Website (the best support web as many seem to claim!): : "Support for 3S1000 and 3S1500 devices is available in ISE WebPACK 6.3i only : when the product is downloaded and installed from the Web at : www.xilinx.com/ise/webpack6" : if you go to the link to download 6.3 you get what ? : guess: you land to 6.2 download pages!! 6.3 webpack is out now -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 74162
After receiving a few emails I have now placed a compiled version of the 8086 processor on my website. http://ht-lab.com/freecores/cpu8086/cpu86.html Regards, Hans. www.ht-lab.com "mep" <mpe@metanic.dk> wrote in message news:41575306$0$284$edfadb0f@dread14.news.tele.dk... > Hi Hans, > Yes to me there is. I am working at the technical university of Denmark and > we have for many years used a 8088-based system to teach microprocessor > design. The hardware is worn out and have to be replaced by a FPGA-based > board. But all our examples, projects, drills etc. are based on this system. > To make the transition easier, we are looking for an IP-core, which can > execute 8088-compatibel code and make it possible to use the old "software" > at least for a period.. > > Is your core for sale? > > Mogens >Article: 74163
(I start a new thread, so maybe there will be more answers.) I wrote (in thread "Differences between Xilinx ISE Foundation and WebPACK"): > Here follows more newbie-questions. > > As the Spartan-3 Starter Kit comes with only sixty > days evaluation version of "ISE Foundation", and > not time-limited version of "ISE WebPACK", I listed > their differences from > http://www.xilinx.com/ise/devsys_feature_guide.pdf > > and realized that WebPACK is lacking at least > these features that come with the Foundation: > > CORE Generator System > Modular Design > FPGA Editor with Probe > SMARTModels for PowerPC and RocketIO. > > What are these, and how essential they are > if I (eventually/immediately) want to do my own designs? At least on Xilinx DS099 Spartan-3 Complete data sheet: http://www.xilinx.com/bvdocs/publications/ds099.pdf in "CLB Overview" it mentions both "FPGA Editor" (on page 10), and later, on page 13: "Other memory functions - e.g., FIFO's data path width conversion, ROM, etc. - are readily available using the CORE Generator system, part of the Xilinx development software." I guess the latter is some kind of a macro library, but the former, the "FPGA Editor" seems to be more important. As it is lacking from WebPACK, does this mean that I cannot specify in my designs with an explicit control how everything is done down at CLB-level? (But instead, write just VHDL or Verilog code, and hope that some other part of the development system "compiles" it sensibly.) > Also, does WebPACK support both VHDL and Verilog > fully? > Anybody knows if there there plans to port it (WebPACK) > to Linux or other Unix-systems, and when? > (And similar question for Altera's Quartus-II software.) Also, I would like to know whether the free version of Altera's Quartus-II contain similar subsystems: "FPGA Editor", "CORE generator", "Modular design", etc. of Xilinx ISE Foundation that have been excluded from ISE WebPACK, or is it likewisely stripped version? Please have patience with my questions, I come from the software world... Yours, Antti KarttunenArticle: 74164
> As it is lacking from WebPACK, does this mean that I cannot > specify in my designs with an explicit control how everything is > done down at CLB-level? > > (But instead, write just VHDL or Verilog code, and hope > that some other part of the development system > "compiles" it sensibly.) > ........... > Altera's Quartus-II contain similar subsystems: "FPGA Editor", "CORE > generator", "Modular design", etc. of Xilinx ISE Foundation that The very nice feature of both solution is that they are free! The simplest way to get your questions answered is just download both and try out your design. After this experiment ask yourself if you really want to struggle with the placement of the cells. The P&R tools are pretty smart now. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74165
Steven, > > BTW, nice job on the Java processor! Very cool. Thanks :-) However, Xilinx has its own Java processor, the Lightfoot: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?k ey=Lightfoot Is it possible to get an evaluation license? You know what I want to do: Produce new lies.... I mean benchmark it against JOP ;-) Or has somebody this processor running in an FPGA and can provide results for an embedded Java benchmark? downloadable from: http://www.jopdesign.com/perf.jsp Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74166
Hi Goeren
Yeah finally, this was the mistake the non blocking Read Statement! Thanks a
lot for this hint, now it works!
So in the future when I wanna read out from FIFO I should use the blocking
statement, shouldn't I?
Cheers
Roger!
-----
"Goran Bilski" <goran@xilinx.com> wrote in message
news:cjs1r1$ii11@cliff.xsj.xilinx.com...
Hi,
Sorry I didn't look careful enough on your C code.
You are using the nonblocking version of the FSL macros but in this case you
should do the blocking versions.
use "microblaze_bread_datafsl" instead of the "microblaze_nbread_datafsl".
Could you also share the .mhs file so I could see that everything is
connected correctly?
Göran
Roger Planger wrote:
Thanks for your help, I have updated the file as you said, but unfortunately
I have still the same problem, I only get 0 values thats so strange...
Cheers
Roger
"Goran Bilski" <goran@xilinx.com> wrote in message
news:cjrovc$ihq2@cliff.xsj.xilinx.com...
Hi,
The problem is that the Write signal is not a ready signal for MicroBlaze
but it's a write signal into a FIFO.
So what you have done is to write new values EVERY clock cycle into the
FIFO which will get full very fast.
If you only want to write back the value that you read, then you should do
this instead.
FSL0_M_Write <= FSL_S_Read_i;
This will ensure that you only write when you have valid input data.
Göran
Roger Planger wrote:
Hello Everybody.
First of all thanks antti for your FSL File, now I understand the Read in
Process.
http://xilinx.openchip.org
But for me also very important is to write the data out after the
calculation is finished. Here is my actual
VHDL Code, so the readin should be okay, and then I only assign the output
value the input value after this
valid. Then I want to read it out, but unfortunately I always get Output =
0, althought I write different values from 1 up to 5 at the data input
port!
So can perhaps someone give me a hint what is wrong here? Antti do you
have a solution for this perhaps?
begin -- architecture IMP
FSL0_S_Read <= FSL_S_Read_i;
FSL_S_Read_i <= FSL0_S_Exists;
FSL0_M_DATA <= FSL0_S_Data; -- Output = Input
FSL0_M_Write <= '1'; -- Indicates Data is
available for reading
end architecture IMP;
Test Code
int data_to_local_link[] = { 1,2,3,4,5 };
int data_back_local_link[5];
for (k=0;k<5;k++){
microblaze_nbwrite_datafsl(data_to_local_link[k],0);
microblaze_nbread_datafsl(data_back_local_link[k],0);
xil_printf("Testvalue :%x\n\r",data_back_local_link[k]);
Output:
Testvalue :0
Testvalue :0
Testvalue :0
Testvalue :0
Testvalue :0
Cheers
Roger
Article: 74167I have the same feelings as John. Take it easy Rick! You don't need to agree to Austin, but you really crossed the line when you started to offend him. Remember, we are not discussing religion! Luiz Carlos.Article: 74168
Peter Alfke <peter@xilinx.com> wrote in message news:<BD86D0B7.8FAE%peter@xilinx.com>... > > This thread seems to have run its course. The original question about the > area ratio between ASICs and FPGA was (as I wrote) meanigless and cute. > Which one is smaller, uses which process, and takes how long to test is all > reflected in one single number, the price charged by the vendor. And there > is intense competition which keeps us all on our toes... > > The user (that is most of the people in this newsgroup) should only be > interested in cost, performance, power consumption, design effort, > reprogrammability, time to market, availability, and general risk. > Smart engineers will know how to make a rational choice. > > ASICs will be the right choice sometimes, FPGAs will be the right choice in > most cases. But we know that in spite of less than 2000 new ASIC designs > worldwide per year(!), the high-volume ASIC business is still much larger > than the FPGA business. That gives FPGAs a tremendous opportunity to grow. > We like that! > > Peter Alfke I think we all understand that Peter likes banging the FPGA drum -- but the real relevence of the area difference is nothing to do with price/flexibility/design effort/time to market/risk, it's power consumption and often total number of chips/packages, which are directly linked to the silicon area inefficiency of FPGAs compared to ASICs. The inescapable fact is that an FPGA solution will always consume a lot more power than an ASIC solution in a similar technology, typically 10x higher. For applications where this matters an FPGA solution is often just not viable; examples include portable equipment where 5-10W for an FPGA rules it out compared to 0.5-1W for an ASIC, or high-complexity system application where we're comparing 5-10W for a single big ASIC with 50-100W for 5-10 big FPGAs. For either of these types of application FPGAs will never catch up with ASICs -- and before anyone says "ah, but FPGA power goes down with improving technology", so do ASICs, and all that happens is that the complexity of the systems expands to use the increased processing power available i.e. the chips don't shrink! One implication of this could be that the "China Syndrome" problem (increasing power density per mm2 as technologies shrink and clock rates increase) will actually reduce the chances of FPGAs addressing these applications. And if the major end use application of silicon switches from mains-powered equipment to portable (as some market surveys predict) FPGAs could even migrate back to being used for prototyping only...:-) Ian P.S. Of course price and so on matter -- but would you buy a mobile phone nowadays whose battery weighed a pound, however cheap it was?Article: 74169
Hi Roger,
I'm glad that you got it working.
Depending on how long time it take to get the result.
If the execution of the FSL modules take too many clock cycle and you
want to do something else during that time or just enabling interrupts,
you need to use the non blocking versions.
But it that case you need to check if the execution of the FSL was
successful or not.
But normally the execution of the FSL modules is not that many clock
cycles and you can therefore in most cases use the blocking instructions.
With the blocking instructions, you don't have to spend instructions and
clock cycle to determine if the FSL instruction was successful or not.
Göran
Roger Planger wrote:
>Hi Goeren
>
>Yeah finally, this was the mistake the non blocking Read Statement! Thanks a
>lot for this hint, now it works!
>So in the future when I wanna read out from FIFO I should use the blocking
>statement, shouldn't I?
>
>Cheers
>Roger!
>
>-----
>"Goran Bilski" <goran@xilinx.com> wrote in message
>news:cjs1r1$ii11@cliff.xsj.xilinx.com...
>Hi,
>
>Sorry I didn't look careful enough on your C code.
>You are using the nonblocking version of the FSL macros but in this case you
>should do the blocking versions.
>use "microblaze_bread_datafsl" instead of the "microblaze_nbread_datafsl".
>
>Could you also share the .mhs file so I could see that everything is
>connected correctly?
>
>Göran
>
>Roger Planger wrote:
>
>Thanks for your help, I have updated the file as you said, but unfortunately
>I have still the same problem, I only get 0 values thats so strange...
>
>Cheers
>Roger
>
>"Goran Bilski" <goran@xilinx.com> wrote in message
>news:cjrovc$ihq2@cliff.xsj.xilinx.com...
>
>Hi,
>
>The problem is that the Write signal is not a ready signal for MicroBlaze
>but it's a write signal into a FIFO.
>So what you have done is to write new values EVERY clock cycle into the
>FIFO which will get full very fast.
>
>If you only want to write back the value that you read, then you should do
>this instead.
>FSL0_M_Write <= FSL_S_Read_i;
>
>This will ensure that you only write when you have valid input data.
>
>Göran
>
>Roger Planger wrote:
>
>
>Hello Everybody.
>
>First of all thanks antti for your FSL File, now I understand the Read in
>Process.
>
>http://xilinx.openchip.org
>
>But for me also very important is to write the data out after the
>calculation is finished. Here is my actual
>VHDL Code, so the readin should be okay, and then I only assign the output
>value the input value after this
>valid. Then I want to read it out, but unfortunately I always get Output =
>0, althought I write different values from 1 up to 5 at the data input
>port!
>So can perhaps someone give me a hint what is wrong here? Antti do you
>have a solution for this perhaps?
>
>begin -- architecture IMP
> FSL0_S_Read <= FSL_S_Read_i;
> FSL_S_Read_i <= FSL0_S_Exists;
> FSL0_M_DATA <= FSL0_S_Data; -- Output = Input
> FSL0_M_Write <= '1'; -- Indicates Data is
>available for reading
>end architecture IMP;
>
>Test Code
>
>int data_to_local_link[] = { 1,2,3,4,5 };
>int data_back_local_link[5];
>
>for (k=0;k<5;k++){
> microblaze_nbwrite_datafsl(data_to_local_link[k],0);
> microblaze_nbread_datafsl(data_back_local_link[k],0);
>xil_printf("Testvalue :%x\n\r",data_back_local_link[k]);
>
>Output:
>
>Testvalue :0
>Testvalue :0
>Testvalue :0
>Testvalue :0
>Testvalue :0
>
>Cheers
>Roger
>
>
>
>
>
>
>
>
>
>
>
>
Article: 74170As far as I remember, at the start, Xilinx called them just PGA (no F). Luiz CarlosArticle: 74171
Hello£¬All
I want to use this chip to read and write a NAND FLASH(SAMSUNG
K9W4G08U1M) in a speed of 100Mbps by using GPIO.but I find it very difficult
to find a reference design.And my design was fail to read and write.So I
write this E-mail just to ask you if you have experience in doing this kind
of project.I also want to know how many Mbps this chips can get in reading
and writing FLASH memroy .
BTW: If you have the same design,I am greatly appreciate that you can send
me your design and your advices.
thanks
carter
Article: 74172Take a look at PicoBlaze, available free from Xilinx with VHDL source. I've used this tiny micro to do similar tasks (I2C interface is very similar to the two wire sensirion interface). If you're not out of Block RAM it should fit handily in your large Virtex part. Also see: http://toolbox.xilinx.com/cgi-bin/forum?14@@/Embedded%20Processors/PicoBlaze%20Soft%20Processor "John_H" <johnhandwork@mail.com> wrote in message news:<V6g8d.8$Be6.457@news-west.eli.net>... > Bidirectional communications are fine. > > You probably don't need a full-blown microcontroller for the implementation, > you just need the intelligence in the FPGA to perform the proper setup and > interrogation over the link. > > You could probably interface the sensor to the smallest CPLDs available with > a simple state machine. Your FPGA choice is fine. > > > "Viswan" <viswan_1981@hotmail.com> wrote in message > news:c9cb3993.0410040849.608c9f4f@posting.google.com... > > hi, > > > > I have a doubt on using inout ports in FPGA design. I am implementing > > an application on FPGA, that should be interfaced to SHT71(Sensirion > > humidity and temperature sensor). My FPGA gets the value of > > temperature and humidity from the sensor and calculates > > moisture(output) using certain equations. > > > > I have designed the arithmetic unit required to calculate the moisture > > value in VHDL, and synthesized on to FPGA. But now I have to > > interface this unit to the sensor(SHT71), and the sensor needs to have > > a controller(any microcontroller as specified in the SHT71 datasheet) > > to control its operations and get the values of temperature and > > humidity. The sensor has a bidirectional data signal as one of the > > ports, and that should be connected to the controller to send and > > receive data. I want to implement the controller also on the same > > FPGA itself. But is it possible? Is it possible to handle a > > bidirectional port from an FPGA to send and receive data? I am using > > Virtex XCV800 HQ240I. Or is it suggestible to use any standard > > microcontroller as an interface between sensor and FPGA? > > > > Any suggestion on this is highly appreciated. > > > > ThanksArticle: 74173
Hello£¬All I am just using Xilinx Virtex-II Pro chips, and have some difficulties in using this chips. I want to use this chip to read and write a NAND FLASH(SAMSUNG K9W4G08U1M) in a speed of 100Mbps by using GPIO.but I find it very difficult to find a reference design.And my design was fail to read and write.So I write this E-mail just to ask you if you have experience in doing this kind of project.I also want to know how many Mbps this chips can get in reading and writing FLASH memroy . BTW: If you have the same design,I am greatly appreciate that you can send me your design and your advices. thanks CarterArticle: 74174
In article <ccd4e670.0410050203.1989f076@posting.google.com>, Ian Dedic <ian.dedic@fme.fujitsu.com> wrote: >The inescapable fact is that an FPGA solution will always consume a >lot more power than an ASIC solution in a similar technology, >typically 10x higher. For applications where this matters an FPGA >solution is often just not viable; examples include portable equipment >where 5-10W for an FPGA rules it out compared to 0.5-1W for an ASIC, >or high-complexity system application where we're comparing 5-10W for >a single big ASIC with 50-100W for 5-10 big FPGAs. For the huge system applications, however, there are cooling solutions (eg, IA64 heatsinks which are rated for 140W of power) which work, so the cooling cost can get just added onto one more side for the asic and against the FPGA, to balance out that $1M mask set. But portable will never be a strong suite of conventional SRAM-based FPGAs: programmable interconnect is simply too much capacitence compared with wires, and thats an ugly fact of life for dynamic power (let alone the static power of all those SRAMs). -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
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