Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Philip Freidin wrote: > On Thu, 14 Oct 2004 12:04:08 -0600, "E.S." <emu@ecubics.com> wrote: > >>Dan DeConinck of PixelSmart wrote: >> >>>I would like to read about any details on the Xilinx Image Processing FPGA >>>which is mentioned in the below press release. >>> >>>Does anybody know what Xilinx has planned ? >> >>As I understand it, this article just mentioned FPGA and Devices which >>have image processing capabilities. Doesn't mean, there are new FPGA to >>expect with image processing capabilities ... >> >>" production of FPGA chips, which are used in such products as TV sets >>and mobile computerized terminals with image-processing features." >> >>And, there is nothing about imaging in the xilinx article ... >> >>So, for you, it is same busines as usual ;-) >> >>just my .0002 > > > I agree with E.S. 's assessment. The Xilinx press release is clear that > this is an extension of their fabless manufacturing strategy, and they > are adding another foundry to their list of foundries that manufacture > chips for them. > > The Forbes article is less clear, because they have latched onto one > of the applications for high end FPGAs, and managed to promote it all > the way to the article title. Yes, this is very similar to the previous tie up with Lattice and Fujitsu, (also for FPGAs, but that deal included a FLASH process) - in both cases US companies provide $ignificant $ums, to give the Japanese IC suppliers a leg-up into the newer processes, in return for good price and queue arrangements. It makes sense, and helps spread the geography of supply. -jgArticle: 74601
shankar.sb@gmail.com (Shankar B) wrote in message news:<b1296d94.0410132245.200a7019@posting.google.com>... > > >mete wrote: > > > > > >> Is there method that is more efficient than regular division for > > >> calculating modulus ? > > Well, it depends on what your divisor for the modulus operation is. If > you are looking at some small values of divisor, then you can do > something of this sort : > > 1. Start with modulus m = 0. > 2. Take one bit at a time starting from the most significant bit. > 3. Have one state for every modulus value (0..n-1, if you are doing > modulo n). > 4. Have a state diagram with the following transitions. If input is > `1', then go to m = (2*m+1) mod n. If current input is `0' go to m = > (2*m) mod n state. > 5. You will have n states with 2n transitions. Run your dividend > through this machine. > 6. This is generic and well suited for small values of n. > > Of course, if you need a combinational implementation, or if you have > special values of n, or if the operation needs to be signed, then the > whole ballgame is different. > > Hope this helps. > --shankar This one sounds neat, here's a first cut at a combinatorial implementation. Modulus distributes over addition, i.e., MODn(A+B) = MODn( MODn(A) + MODn(B) ) So the input value, I, can be partitioned into 4-bit groups, each of which feeds an array of 4-LUTs. Array A produces modulus for bits (4*i .. 4*i+3). For large values of n, the low order bits that sum to less than n don't need to pass through LUTs. Sum the results from each array. If n and I are large, this first stage will put you a lot closer to the final result. Repeat as necessary till result is guaranteed less than 2*n, then subtract n if result is >= n. How long is necessary? Take an example. Assume I is 48 bits, and n is 13 bits. In the first stage, the lower 12 bits of I can be passed through to the addition, and the remaining 36 bits produce 9 more addends. The result is at most 10*(n-1), having at most 13+4 = 17 bits. Repeat the process, pass lower 12 bits, and two LUT arrays convert the remaining 5 bits, giving 3 addends with a result that is at most 3*(n-1). Last stage gives result F that is at most 2*(n-1), which can be compared to n to determine if a final subtraction is required (carry logic does comparision, LUT logic selects F or (F-n) based on carry result). Still requires 13 additions (= 9 + 2 + 1 + 1), but is somewhat shorter than doing long division. What sizes input and modulus is OP interested in? Is variable modulus needed? John (always interested in these type circuits)Article: 74602
Chris <> wrote in message news:<ee896a8.3@webx.sUN8CHnE>... > Nice chip, but it's MPEG-4 at 30 fps (good), CIF resolution (320x240 - yuck). They list one of its applications is a PVR.... Who's going to build a PVR out of that? Maybe for a wrist watch. DerekArticle: 74603
Followup to: <416EE08B.443D61B5@yahoo.com> By author: john@bluepal.net In newsgroup: comp.arch.fpga > > Have you been able to verify if this board can be used with conventional > tools? Does it have connectors for a Xilinx or other cable? > Well, at least the schematics for the Altera version of the board has "Printer Port JTAG Interface - ByteBlaster compatible" in big letters on page 3. -hpaArticle: 74604
Hi All,
> I *think* you have uncovered a bug in Quartus 4.1 synthesis. I'll confirm
> this with the synthesis team tomorrow.
First of all, I should point out that this is sub-optimal synthesis, NOT a
"bug" -- the design will function, it just uses more logic elements than
necessary. We *may* fix this in a future release of Quartus, but the
solution will not be easy to implement so don't hold your breath. The value
is rather limited due to the input limitations explained below, and the
relative rarity of this combination of functions.
In the meantime, there is a work-around. You can directly instantiate
"stratix_lcells" (the WYSIWYG cell for Stratix/Cyclone LEs). Below I give
the code (thanks to a helpful synthesis guy) for a registered
adder/subtractor with oodles of extras. Features:
- Implements A - B or A + B (depending on signal "addnsub")
- Registers are synchronously loadable with "data" when synchronous load
"sload" is asserted
- There is shared clock "clk", clock enable "ena", synchronous clear
"sclr", asynchronous clear "aclr"
A couple caveats:
- There are only 26 non-global inputs to each LAB in Cyclone (and 30 in
Stratix). So the fitter will have to split the design over multiple labs if
you use more than 7 bits in Cyclone, since you need 3 bits/bit (A, B,
sload_data) plus a 4 local control signals and 2 global signals. Assuming
aclr and clk are global, and the others are local, that's 4 extra signals
you need.
- When you stress the number of inputs on a LAB, you run the risk of
having reduced routability, resulting in longer run-times, poor performance,
or unroutable designs in the worst case. You should try to keep # of LAB
inputs around 22-24.
When Quartus splits the carry-chain, it must insert extra logic elements to
end the chain and begin the next. For example, to implement a 10-bit
add/sub/load/ena/aclr/sclr/sload requires 13 LEs. Still better than 20 LEs,
but not 1:1. Also, the remaining unused in the lab will not be too useful,
since the lab inputs are nearly saturated.
If you have no sload or a constant sload, you can implement 10 bits/LAB
since you only need 2n + 4 lab lines.
Hope this helps!
Paul Leventis
Altera Corp.
************************* VERILOG CODE ******************
// Thanks to Gregg Baeckler for code!
module addsub (clk,a,b,addnsub,sload,sclr,aclr,ena,data,out);
parameter WIDTH = 7;
input [WIDTH-1:0] a; // Operand A
input [WIDTH-1:0] b; // Operand B (+B or -B based on addnsub)
input [WIDTH-1:0] data; // Data to load upon sload
input clk; // Clock
input addnsub; // ADD=1, SUBTRACT=0
input sload; // Triggers synchronous load of register
input sclr; // Synchronous clear
input aclr; // Asynchronous clear
input ena; // Clock enable
output [WIDTH-1:0] out;
wire [WIDTH-1:0] out;
wire [WIDTH-1:0] cout_wires;
// The first cell CIN is special since it has no carry-in.
// Its carry-in will be the addnsub signal
stratix_lcell first_cell (
.dataa(b[0]),
.datab(a[0]),
.datac(data[0]),
.sload(sload),
.sclr(sclr),
.ena(ena),
.aclr(aclr),
.clk(clk),
.inverta(addnsub),
.regout(out[0]),
.cout(cout_wires[0])
);
defparam first_cell .operation_mode = "arithmetic";
defparam first_cell .synch_mode = "on";
defparam first_cell .sum_lutc_input = "cin";
defparam first_cell .lut_mask = "96b2";
defparam first_cell .output_mode = "reg_only";
// fill in the rest of the cells in this loop
genvar i;
generate
for (i=1; i<WIDTH; i=i+1)
begin : ads
stratix_lcell my_cell (
.dataa(b[i]),
.datab(a[i]),
.datac(data[i]),
.sload(sload),
.sclr(sclr),
.ena(ena),
.aclr(aclr),
.clk(clk),
.cin(cout_wires[i-1]),
.inverta(addnsub),
.regout(out[i]),
.cout(cout_wires[i])
);
defparam my_cell .operation_mode = "arithmetic";
defparam my_cell .synch_mode = "on";
defparam my_cell .sum_lutc_input = "cin";
defparam my_cell .lut_mask = "96b2";
defparam my_cell .output_mode = "reg_only";
end
endgenerate
endmodule
Article: 74605Chris wrote: > > > Did you *simulate* this design? > > No, I don't have a simluation tool -- startup company, shoestring budget, etc. I've always been a fan of the big simulator called real life anyway. > > > Check to make sure your synthesis didn't do you a "favor" by replicating > one or more registers in your synchronizing pipe > > I'll look into it. I've had this sort of trouble with CPLDs before. I don't understand. You can get a *free* copy of the Modelsim simulator that will work with Xilinx tools. I thought that came with the Foundation tools, but maybe not. It does come with the free webpack package. I really have no idea how you can expect to get an FPGA working in a reasonable time without a simulator. Even if yo have no money, you can't afford to do without a simulator. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74606
On 14 Oct 2004 18:38:32 -0700, john.l.smith@titan.com (John) wrote: >shankar.sb@gmail.com (Shankar B) wrote in message news:<b1296d94.0410132245.200a7019@posting.google.com>... >> > >mete wrote: >> > > >> > >> Is there method that is more efficient than regular division for >> > >> calculating modulus ? [snip] >John (always interested in these type circuits) You might be interested in this thread: http://groups.google.com/groups?threadm=18c289aa.0304230854.6897fb3b%40posting.google.com which discusses a combinatorial circuit for evaluating a ten bit number mod 3 in a single CLB. Regards, AllanArticle: 74607
Austin Lesea <austin@xilinx.com> wrote in message news:<ckjgil$5pe1@cliff.xsj.xilinx.com>... > Colin, > > Our SSO rules assume you have dedicated planes for Vccint, Vcco. If you > do not have both a power and a ground plane for each of these supplies, > the SSO numbers must be reduced. This also goes for simultaneously > switching CLBs, and not just IOs. We assume a power and ground plane > (yes that would be four layers just for power) for low inductance on the > Vccint/Vcco. > > You might want to investigate the Point of Load concept (POL or POLA) > from TI (US) and Belkin (Japan). > > By placing power supplies directly at the load, the loop inductance is > greatly reduced. > > I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very > well. Perhaps you pay more for a more capable power supply, but you pay > less for the PCB. > > Remember that V=-LdI/dt. There is no way to reduce ground and Vcc > bounce without reducing either the I (current switched by reducing the > number of things switching), or reducing the L (indutance). The time > (dt) is not something that can be changed (as in internal nodes switch > time is fixed by process and design). > > No amount of bypass caps will fix a bad pcb. This is a very curious statement. Bypass caps provide virtually all of the high frequency current-they get recharged by power supply. Granted, you need low impedance to recharge the caps before they are used again, but the power supply is not supplying the fast edge currents.Article: 74608
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:416F4D90.B0C396CB@yahoo.com... > I really have no idea how you can expect to get an FPGA > working in a reasonable time without a simulator. Even if yo have no > money, you can't afford to do without a simulator. :) I wouldn't be without my simulator but ChipScope offers a possible alternative which makes sense in certain circumstances. The simulation time is certainly reduced! At the expense of synthesis/compilation time! Cheers, Syms.Article: 74609
Subroto Datta wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<41583A6C.827D2CFF@yahoo.com>... > > Isn't this a rather clumsy piece of code? Isn't there a way to use a > > few simple lines to infer a block ram (that is not written) and then > > init the contents separately? It is not often that I want to hard code > > my ROM contents. > > > > > > > > I was adhering to the customer's code sample when formulating the > original reply reply. To achieve what you want you can do the > following: > > The easiest way to make a ROM that can be initialized separately is to > instantiate an Altera megafunction. You can use the MegaWizard > Plug-In Manager (Tools menu) to configure the block and look at a > specific initialization file and then you can change the contents of > the file later on. > > The LPM_ROM is a part of the LPM standard and and shoud be supported > by most FPGA CAD tools. Thanks for the reply. I guess I missed it until now. "Easiest" is a subjective term. I avoid all instantiations if I can to make the code more portable. Is there a way to use an initialization file with inferred RAM or ROM? In my case it actually will be RAM since the processor can update its own program. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74610
Eric, You must constrain your design before the P&R tools try to meet timing. In the Xilinx tools I add a line like:- NET "CLOCK" PERIOD = 10ns; or something like that. Read the Xilinx constraints guide. Cheers, Syms. "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhlle8euqq.fsf@ruckus.brouhaha.com... > I'm using WebPACK 6.3.01i. The synthesis report tells me the > minimum clock period is about 17 ns. > > How do I get the same kind of static timing info after place and route? > The P&R report shows max clock delay, net skew, pin delay, etc., but > I don't see min period or max frequency. The async delay report says > that the max delay is about 6.6 ns; am I supposed to infer a minimum > clock period from that? > > Thanks, > EricArticle: 74611
"Tom Seim" <soar2morrow@yahoo.com> wrote in message news:6c71b322.0410142059.6ff45611@posting.google.com... > Austin Lesea <austin@xilinx.com> wrote in message >> No amount of bypass caps will fix a bad pcb. > > This is a very curious statement. Bypass caps provide virtually all of > the high frequency current-they get recharged by power supply. > Granted, you need low impedance to recharge the caps before they are > used again, but the power supply is not supplying the fast edge > currents. ..but if your PCB puts too much inductance between the caps and the FPGA, this 'bad' PCB won't be fixed by merely adding more badly routed and positioned bypassing. Cheers, Syms.Article: 74612
more to the point.. none of the prices on web sites are realistic FPGA prices are strictly volume .. only accept a quote from a supplier. Although Arrow and Avnet prices aren't to unrealistic... but again... check the volume. Simon "Zimmer" <zihu882@yahoo.com> wrote in message news:65a3fa49.0410140701.4dd39773@posting.google.com... > What you say is: CPLD is not good/cost-efficient for simple solution. > > "Simon Peacock" <nowhere@to.be.found> wrote in message news:<416e1e2a@news.actrix.gen.nz>... > > that's as good as you can get.. unless you buy 1/2 a million > > > > "Zimmer" <zihu882@yahoo.com> wrote in message > > news:65a3fa49.0410131936.2bdeb565@posting.google.com... > > > Hi Everyone, > > > > > > Can anybody let me know where to buy the EPM1270 TQFP CPLD in a cheap > > > price? I've checked altera.com, the online wholesale price is $4.25/pc > > > for 500K units. But the distributor here would charge me over $24 for 10 > > > pc. (ebay.com is not a good site for the stable supply) > > > > > > Any advice appreciated! > > > > > > -ZimmerArticle: 74613
>I don't understand. You can get a *free* copy of the Modelsim simulator >that will work with Xilinx tools. I thought that came with the >Foundation tools, but maybe not. It does come with the free webpack >package. I really have no idea how you can expect to get an FPGA >working in a reasonable time without a simulator. Even if yo have no >money, you can't afford to do without a simulator. :) OK, I'll play devil's advocate. Why is simulation so critical? Why don't software people simulate their code? What's the difference between software and hardware that makes simulation so important/good for hardware? What's the turn around time to make a minor patch to a FPGA design and download the new bits and do the testing in real time? I'm not trying to say that simulation is a bad idea, just trying to understand what makes it so appropriate for the FPGA world where the NRE of a trial is time rather than the cost of a mask set. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 74614
I wrote: > I'm using WebPACK 6.3.01i. The synthesis report tells me the minimum > clock period is about 17 ns. [...] How do I get the same kind of > static timing info after place and route? "Symon" <symon_brewer@hotmail.com> writes: > You must constrain your design before the P&R tools try to meet timing. In > the Xilinx tools I add a line like:- > NET "CLOCK" PERIOD = 10ns; > or something like that. Read the Xilinx constraints guide. Thanks, I'll give that a try. It seems somewhat surprising that they don't report the clock period without an explicit constraint; Cypress WARP does.Article: 74615
Symon wrote: > > "Tom Seim" <soar2morrow@yahoo.com> wrote in message > news:6c71b322.0410142059.6ff45611@posting.google.com... > > Austin Lesea <austin@xilinx.com> wrote in message > >> No amount of bypass caps will fix a bad pcb. > > > > This is a very curious statement. Bypass caps provide virtually all of > > the high frequency current-they get recharged by power supply. > > Granted, you need low impedance to recharge the caps before they are > > used again, but the power supply is not supplying the fast edge > > currents. > ..but if your PCB puts too much inductance between the caps and the FPGA, > this 'bad' PCB won't be fixed by merely adding more badly routed and > positioned bypassing. I think he was addressing the comments about keeping the PSU near the chips. I have *never* heard anyone recommend that PSU placement would affect the need for good PCB design. The range of frequencies that PSU selection or placement would affect is way below the range of freqencies that would be affected by PCB layout. I don't think anyone here is talking about putting ceramic decoupling caps an inch from the chip pins. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74616
Hal Murray wrote: > > >I don't understand. You can get a *free* copy of the Modelsim simulator > >that will work with Xilinx tools. I thought that came with the > >Foundation tools, but maybe not. It does come with the free webpack > >package. I really have no idea how you can expect to get an FPGA > >working in a reasonable time without a simulator. Even if yo have no > >money, you can't afford to do without a simulator. :) > > OK, I'll play devil's advocate. Why is simulation so critical? > > Why don't software people simulate their code? What's the difference > between software and hardware that makes simulation so important/good > for hardware? > > What's the turn around time to make a minor patch to a FPGA design > and download the new bits and do the testing in real time? > > I'm not trying to say that simulation is a bad idea, just trying > to understand what makes it so appropriate for the FPGA world > where the NRE of a trial is time rather than the cost of a mask set. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. Ok, if you test a new design in a chip and it doesn't work, what do you do then? In a simulation you look at the internal signals to figure out what you did wrong. On the bench you would need to recompile your design to bring different signals out to a test point until you track down the issue. My original point was not that it is essential to use a simulator for *every* issue of a design (although I do), but that the OP was not using one *at all*! Have you ever designed an FPGA without simulating??? If you have, I bet it was before I was working with FPGAs, most likely on the Xilinx 2k devices... ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74617
On Fri, 15 Oct 2004 00:48:38 -0500, hmurray@suespammers.org (Hal Murray) wrote: >Why don't software people simulate their code? What's the difference >between software and hardware that makes simulation so important/good >for hardware? > depends on how you define simulation but i think actually software people do simulate their code. as far as i am concerned, the debugger is analoguous to simulator in software world and just downloading is similar to running the program and looking at the output. when you run the program under the debugger, you get to see all the internal state in interesting ways (waveforms or register values etc). also simulation happens usually with rtl as opposed to gate-level. one wants to see the intended behaviour before the synthesizer messes with it. of course there are times when you have to look at the gates but similar to assembly only debugging, it is much more difficult to do as opposed to source level debugging. with rtl simulations, you see all the internal registers/wires as they are named by the designer which may not be available after synthesis/p&r. >I'm not trying to say that simulation is a bad idea, just trying >to understand what makes it so appropriate for the FPGA world >where the NRE of a trial is time rather than the cost of a mask set. the issue is observability and controllability. of course if you have the ability to dump all the internal nodes of the fpga, look at the with a waveform viewer, suspend the execution, apply different values to pins etc. you may not need simulation but that requires a pretty darn good logic analyzer, internal dump support, a good pattern generator and still leaves you with out rtl level access. imo rtl simulation is still the best way to weed out the initial stage of bugs from your design.Article: 74618
Eric Smith wrote: > > I wrote: > > I'm using WebPACK 6.3.01i. The synthesis report tells me the minimum > > clock period is about 17 ns. [...] How do I get the same kind of > > static timing info after place and route? > > "Symon" <symon_brewer@hotmail.com> writes: > > You must constrain your design before the P&R tools try to meet timing. In > > the Xilinx tools I add a line like:- > > NET "CLOCK" PERIOD = 10ns; > > or something like that. Read the Xilinx constraints guide. > > Thanks, I'll give that a try. It seems somewhat surprising that they > don't report the clock period without an explicit constraint; Cypress > WARP does. I am not aware that they *don't* report a max clock speed, but it is very unusual to care about clock speed if you don't spec a requirement. If you don't use a speed constraint, the tool assumes you don't care about the speed and just does a route without any optimization. Isn't that obvious? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74619
Hi Paul, thank you for your help. What kind of logic element are you thinking of when you talk of wire function? The phase relationship between the internal clock and the external clocks do not matter so that would be no problem ... Rgds André > could, for example, take your c1 clock and feed it to two parallel logic > elements, which then take identical routes to two I/Os. One logic element > does nothing (implements a wire function :-)), the other implements an > invert function. If you place this LAB adjacent to the horizontal I/O that > you want to bring the two signals out of, then you should get pretty > similar, short routes from the LEs to the I/Os. > > Do you need a known phase relationship between the internal clock and the > external clocks? > > Paul Leventis > Altera Corp.Article: 74620
Hi Andre, > What kind of logic element are you thinking of when you talk of > wire function? Actually, you don't need LEs at all. Just feed the output of the PLL and the negation of it directly to two I/O pins. The negation will be performed in the I/O interface. Be sure to place them in the same row/column on the same side to minimize skew. If you do so, the only difference in delay will be due to slightly different delays through the inverting and non-inverting paths of the I/O programmable invert. Oh yeah -- you should also make sure you use I/Os that have the same functionality. Any I/O that has dual-purpose will have slightly higher pin cap and thus slightly greater delay. For example, in a 1C12 I used two I/Os in fourth row on the left side, and Quartus tells me I get 2.037 ns of Tco to each (from the PLL -> pin). thepll mypll( // instantiates a PLL I made with the megafunction wizard .inclk0(in_clock), .c0(internal_clock) ); assign out_clock = internal_clock; assign out_clock_bar = !internal_clock; In the event that you did want to use two LEs (as I suggested originally for some bone-headed reason), you can explicitly force Quartus to do so by instantiating an LCELL buffer. This example gives me something in the range of 2.7 ns of Tco. Not that the Tco matters. thepll mypll( .inclk0(in_clock), .c0(internal_clock) ); lcell lcell1( .in(internal_clock), .out(out_clock) ); lcell lcell2( .in(!internal_clock), .out(out_clock_bar) ); You will also need to constrain these two LCELLs to be in the same lab near the I/Os you are driving. Hopefully I didn't get too much of this wrong; I do not use Quartus much myself. This example and the add/sub Cyclone question were my first two verilog designs :-) Paul Leventis Altera Corp.Article: 74621
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:416EE08B.443D61B5@yahoo.com... > I have not been able to > confirm that the Altium board is usable without the Altium software > (demo version has a 30 day license only). There are JTAG ports on the > board, but the use a connector for the PC parallel port. I also don't > understand why there are *two* of them, soft and hard. I remember to read it somewhere in the Altium site that says that the boards WORK without Altium software. Also, by looking at the schematics you can see that in the Altera's version, they say the interface is compatible with ByteBlaster and for the Xilinx version it has been written to be compatible with ISE. I could not find any Cyclone EP1C12 or Spartan 3 XC3S400 prototype board with more than just an FPGA on it under (I mean, with some RAM, connectors, programmer interface, ...) under $200 and it seems that the Altium's offering has a great price. The only thing that I find missing in this board is the lack of a AD/DA on board. It would be very nice if they could fit a fast AD/DA in the same board and keep the same price ;)Article: 74622
I'd appreciate if someone could answer a few questions below: If you reply by email, REMOVE "SPAMNOMORE" in capital letters repeated in my address twice (edit address manually)!! We ordered "Xilinx Virtex-Pro II" development kit, your answers will NOT change buying decisions - it’s already here, we need to know: 1. Is it possible to put either Linux or Nucleus RTOS into this chip memory, to my knowledge your chip includes two PowerPC's and we intend to use it as a host? Note we need to know if either OS can be loaded, not both, we will experiment with Linux and then Nucleus RTOS (Nucleus RTOS is Realtime Operating System from AcceleratedTechnology/MentorGraphics Corporation, for Xilinx FPGA's embedded design). 2. If yes, when Linux or Nucleus RTOS is loaded, will we get communications stack and drivers for IEEE 802.11 in ad-hoc mode (this as any EE Engineer knows is a wireless LAN standard)? 3. If yes, then we'll purchase a standard IEEE 802.11 card, can this card be plugged into your development kit port? From what I gathered from my professor, he intends to plug this card into your "serial port", but seems strange to me. 4. Maybe you can suggest additional Xilinx products to use in our IEEE 802.11 wireless communications project (ad-hoc mode)? VirtexPro II development kit is already here and I was asked to research the above information to start design. Thanks for your time.Article: 74623
In article <YMMbd.14902$o55.4512@newssvr31.news.prodigy.com>, Mark Levitski wrote: > We ordered "Xilinx Virtex-Pro II" development kit, your answers will NOT Which development kit exactly? There are quite a bit of them: http://www.xilinx.com/publications/matrix/devboard_color.pdf > change buying decisions - it’s already here, we need to know: > 1. Is it possible to put either Linux or Nucleus RTOS into this chip memory, > to my knowledge your chip includes two PowerPC's and we intend to use it as Into the _FPGA_ chip memory--no, I don't think it has enough memory (just a few hundred of kilobytes). But the development board likely has some memory that can be used from the FPGA, typically 64 or 128 megabytes, and this is sufficient for running Linux of the PowerPC. I don't have the hardware yet (planning to get it), but I know that there are Linux distributions that run on the FPGA, for example TimeSys Linux which should run on Amirix development boards out of the box. I don't know how much work would it be to port the Linux to run on some other development kit, but in theory it is possible. On Nucleus RTOS I know nothing of, sorry. I was told (on this list, IIRC) that the Xilinx EDK comes with a minimal realtime kernel that also runs on the FPGA. Of the rest of your questions I know little about, sorry.Article: 74624
I started a new project with an EDF file (generated from synplicity pro), when i then translate, map and read the log file in ISE 6.2, it says my design has an equivalent gate count of 0?! It says basically that at my top level the clock is sourceless - this makes sense because i dont have a pin constraints file, but when I arbitrarily assigned a pin to the clock to see if that would sort it out, it doesn't. I also added "-u" to other command line options to try stop it from optimizing away my logic - again this didn't work. The odd thing is when i synthesize (with synplicity) and export (edf) the lower levels files and hierarchy, everything in ISE translates and maps fine - examining the generated log files for the individual leaf cells and lower level hierarchy shows ball park correct figures for equivalent gate counts Any thoughts/help would be very much appreciated -- tricanwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion Forum
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z