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Just a small reaction on the MAXII family. I tried very recently the Quartus 4.1 Web Edition software with some VHDL sources originally targeted at Xilinx XC95288XL CPLD's. The software appears to me as more demanding in terms of thinking than the ISE Webpack, that, I think, takes you more "by the hand" if you do not want to bother too much about all possible synthesis and fitter options. In general, the software "look" seems more attractive than the Xilinx (but this is of course strictly my personal opinion). The VHDL designs I tried were immediately synthesized and fit into a EPM1270 chip (also tried the EPM570), with no adaptation (only standard VHDL used). The LE/macrocell expected ratio (Altera says typical around 1.2) may be significantly exceeded, but the ratio is obviously dependent on the type of logic to fit (the MAXII are in fact "special" FPGA's, and comparison with CPLD is a bit shaky). I think designs with wide decoders will need a higher ratio, but I have also reached ratios as low as 1.1. with logics requiring plenty of registers and counters. OK for that. So,I really consider the possibility to move from Xilinx to Altera, at least as far as the CPLD's are concerned for now, especially considering the amount of LE's available in for instance the TQ144 package (I am sometimes short of resources with the already expensive XC95288XL or CoolRunner II top of the line CPLD). I am however still a bit cautious about the "cheap" character of the MAXII CPLD's. I see a number of interrogations on the Web asking for "places to buy cheap MAXII devices". For instance, EBV (a large European distributor) offers samples of the MAX1270T144C5 at around 26 euros. I have seen 24 dollars elsewhere in the world. But, on the other hand, EBV Belgian Branch message is that the prices per 100 could be as low as 12-14 euros (add 20% for dollars) and the prices of the future MAX570T144C5 as low as 8 euros. Does it sound reasonable ? "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<deqdne-eK8syPe3cRVn-qQ@rogers.com>... > Hi Vax, > > First, I should point out that Altera's mature MAX 7000 family is likely > sufficient and widely available. The MAX 7000S is a 5.0V device with up to > 256 macrocells. The MAX 7000AE is a 3.3V device with up to 512 macrocells. > Both are available in a wide array of cheap, easy-to-use packages. > > The new low-cost Max II family from Altera also meets many of your > requirements. Max II is 3.3V compatible (both power rail voltage and I/O > voltage). The EPM570 device offers 570 LEs, or roughly 440 macrocells. It > is supported by the free Quartus II Web Edition software, available from our > web site. There are three packages: a 100-pin TQFP (with 76 user I/Os), a > 144-pin TQFP (with 116 user I/Os), and a 256-pin FBGA (with 160 user I/Os). > > The downside is that you can't buy the EPM570 today -- only the EPM1270 is > available. But it is shipping in a pin-compatible 144-pin TQFP, so you > could prototype with it and plug in a EPM570 in early 2005 when it is > available. I don't know the unit prices of any of our chips so I can't help > you out there. > > If we get the Web Edition software from www.altera.com, you can try out all > of our CPLD families to see how they do for density & performance. Your > VHDL should work (provided it is generic) in any of our devices. > > > BTW, is it easy to move a CPLD design (VHDL) to FPGA? It has mostly adders > > (5 MHz or lower) and state machines (20MHz). Thanks. If so, would you also > > let me know what FPGA family to look at, with those requirements applied? > > Max II's core fabric is more like an FPGA -- it uses LUT-based Logic > Elements (LEs) instead of AND-OR macrocells. It also features a segmented, > island-style routing architecture instead of the global fabrics found in > older CPLD families. This family is perfect for you needs. > > Generic VHDL should run push-button on Max II, or any other CPLD/FPGA > product from pretty much any vendor. Just change the target device & push > compile! And the speed targets you mention are slow by modern FPGA/CPLD > standards, so they sound doable. > > Good luck, > > Paul Leventis > Altera Corp.Article: 74751
Brad,
I tend not to pass the state of a statemachine
to other blocks. I tend to do the following
steps:
1) Draw block diagram for statemachine and
datapath/resource blocks the statemachine
controls.
2) Draw bubble diagram (on paper) for statemachine.
3) Factor out any additional resources out of the
statemachine (such as incrementers) and put
them in separate processes or separate components.
4) Code all datapath and resource blocks
5) Fix bubble diagram as when you code the datapath
it is typical that you need something different than
in your original plan.
6) Code statemachine from bubble diagram.
Keep in mind that every designer probably has their
own method, but this ought to get you started.
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Help!
>
> I have a state machine on my top level for an SRAM controller. The states
> are sram_state_read, sram_state_write, sram_state_idle, and
> sram_state_reset. Presently the design is flat with no components. I want to
> put the SRAM paths in a component by itself. Since the SRAM state machine
> may influence other parts of the design, I want to have a separate component
> for it, or leave it in the top level. Now it seems to me that one should be
> able to pass these states down to to the SRAM paths' component using the
> type that I decleare on the top level. However I have been unable to find
> the syntax for doing this. I suppose I could "hard code" the states into
> known patterns of 1s and 0s and pass the the info into the component using
> std_logic_vector but this seems counter to high level language philosophy.
> Can anybody help?
>
> Thanks,
> Brad Smallridge
> b r a d @ a i v i s i o n. c o m
>
>
>
Article: 74752Hi I am working with Xilinx Virtex II FPGA. There is a soft core MAC and daughter card PHY. I am not using any kind of Stack. I am trying to implement Ethernet to Ethernet. I am able to send packet on the wire from the MAC through they PHY and I am able receive these packets back also through the PHY and MAC. I am able to do this loopback through writing bogus source MAC address and my own MAC address as the destination address. The MAC does NOT overwrite source address (option is not selected). Now I have created an arp entry in the table for my board MAC. ex. arp -s 192.168.1.0 00-00-01-02-03-04. I can verify the entry its there. Now when I Ping my board from pc the packet is never received. Any help will greatly appreciated. I been working on this for couple of days. thanks. TONYArticle: 74753
On 18 Oct 2004 07:47:27 -0700, whizkid@gamebox.net (whizkid) wrote: >HI friends, > I want to assign a random value either +5 or -5 to a port . How do i >do that? >I tried $random function but it allows to assgin values between -5 and >+5 or 0 to 5 . But what i want is exactly +5 or else -5. Anyone know >how to do it .. you can say reg r; r = $random; if (r) out = 5; else out = -5; hopefully the LSB of $random is as random as the rest :-)Article: 74754
"Tails" <tails_naf@yahoo.com> wrote in message news:987636ca.0410171546.15d5b86b@posting.google.com... > So Antti, > Can you answer the burning question: > Does a Spartan-3 Nios-II beat a > cyclone Microblaze in performance/area? > How do the two compare? > > This is really interesting work, and a great demonstration of the real > differences between the architectures I think (i.e. putting a core > specifically designed and optimized for one, into the other) Ok, I think I can answer the burning question :) answer is: There is no significant differences at all ! ---------------------------------------- MicroBlaze, NIOS-II and also OR1K look very similar as of ISA neither MicroBlaze or NIOS ISA is optimized or targetted for some specific FPGA fabric. Sure MicroBlaze implementation is optimized for Xilinx primitives and NIOS for Altera primitives but that goes only for the implementation not for the CPU architecture per se. Same for NIOS-I its ISA is not in any optimized for ACEX and it would be working quite nicely in Cyclone too. But Altera has dropped NIOS-I. The differences come from the SoC builder and Bus architecture, differences in bus mastering, IP cores used etc, not from the CPU architecture. NIOS has simultaneous multimastering in some cases this could be a benefit, but only if really used properly. Both MicroBlaze and NIOS being 32 bit CPU's are "memory hogs" smallest reasonable amount of code/data memory is 32KB (assuming thats the only memory available). With some care its possible to write real applications (like full OTG DRD Stack) that fit to 32KB, however in most cases external memory is required for code storage. So the speed of EMIF and caches are very important to speed up the execution from external memory. Both MicroBlaze and NIOS are not very good in terms of interrupt latency unfortunatly :( at least when using default interrupt handler in C - hand coded assembly int handler could have smaller latency but could impose other problems. NIOS bus peripherals are little easier to create then MicroBlaze OPB peripherals. Both NIOS Custom Instruction and MicroBlaze FSL are "cool" solutions. NIOS uCLinux is WAY easier to get started then MicroBlaze uCLinux thanks to the full integration of the config and integration into Eclipse workbench, as EDK6.3 is also Eclipse based it would be possible todo the same for MicroBlaze uClinux config and build. hm.. I guess my answer was not a yes/no answer at all. Well there really is not any big differences - only matter of taste what FPGA what tools one chooses. AnttiArticle: 74755
Depends heavily on the design. Xilinx packs tighter for certain
arithmetic because of the structure of the LUT and carry chain: Altera's
carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one
for sum one for carry so it limits the number of inputs per bit. Stratix
adds a little bit of extra logic to the LE to allow implementation of an
adder subtractor without going to two levels of logic, and there is a way
to load data bypassing the adder which provides single level solutions for
those specific (and fairly common) cases. Xilinx will also allow you to
turn the LE into a 16 element shift register, which can be very handy not
only for shift register delays, but also for reloadable LUTs, which are
useful for things like adaptive DA filters. Altera has more options for
the memory structure, which in many cases makes it more efficient for
certain types of designs requiring memory. My point is both vendor's
offerings have some strong points, and which one is best depends heavily
on your application.
Guitarman wrote:
> Hello All,
>
> I've been designing with Xilinx FPGAs for a while so I'm used to the
> "Slice" concept. I'm looking at Altera's Max II as a nice possible
> solution for a design.
>
> I took my VHDL code and it synthesized to 40 Slices in a Spartan III.
> Then I took the same code and sythesized it for a Max II (using
> Quartus II now) and it was 71 LE's.
>
> I realize a blanket statement 71 LE's (approx. =) 40 Slices, is totaly
> dependant on how the code is sysnthesized.
>
> But is a approximate 1 Slice = 2 LE's a pretty close all around
> estimate.
>
> Thanks
> Eric
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74756
General,
There are also I/O clocks in V4 I don't believe anyone has mentioned, which
are specifically for source synchronous transfer, and come in on one of the
I/O pins for that bank. IIRC, there are 8 I/Os plus clock per bank and the
I/O clock can source CLBs in the adjacent banks or up to 24 I/O. That should
provided plenty of clock resources for any combination of inputs with separate
clocks. The I/O logic also has dynamically programmable delay with 64 ps
granularity, so you can adjust the delays on each pin either statically or
dynamically (with a state machine in your logic).
General Schvantzkoph wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74757What do you mean with > Both MicroBlaze and NIOS are not very good in terms of interrupt latency > unfortunatly :( at least when using default interrupt handler in C - hand > coded assembly int handler could have smaller latency but could impose other > problems. Could impose other problems?? I've written an interrupt handler that reënables the interrupts and is done fully in assmebler. Depending on the state of the Icache I reach 2 - 4µs. No one seems to reënable interrupts anymore (according to the altera documentation), but it can be done thay say. But when I change the predefined niosII system from standard to the full featured one (with data cache). My system isn't stable anymore. "Antti Lukats" <antti@case2000.com> wrote in message news:ckvs1e$ntu$00$1@news.t-online.com... > "Tails" <tails_naf@yahoo.com> wrote in message > news:987636ca.0410171546.15d5b86b@posting.google.com... > > So Antti, > > Can you answer the burning question: > > Does a Spartan-3 Nios-II beat a > > cyclone Microblaze in performance/area? > > How do the two compare? > > > > This is really interesting work, and a great demonstration of the real > > differences between the architectures I think (i.e. putting a core > > specifically designed and optimized for one, into the other) > > Ok, I think I can answer the burning question :) answer is: > > There is no significant differences at all ! > ---------------------------------------- > > MicroBlaze, NIOS-II and also OR1K look very similar as of ISA > > neither MicroBlaze or NIOS ISA is optimized or targetted for some specific > FPGA fabric. > > Sure MicroBlaze implementation is optimized for Xilinx primitives and NIOS > for Altera primitives but that goes only for the implementation not for the > CPU architecture per se. Same for NIOS-I its ISA is not in any optimized for > ACEX and it would be working quite nicely in Cyclone too. But Altera has > dropped NIOS-I. > > The differences come from the SoC builder and Bus architecture, differences > in bus mastering, IP cores used etc, not from the CPU architecture. > > NIOS has simultaneous multimastering in some cases this could be a benefit, > but only if really used properly. > > Both MicroBlaze and NIOS being 32 bit CPU's are "memory hogs" smallest > reasonable amount of code/data memory is 32KB (assuming thats the only > memory available). With some care its possible to write real applications > (like full OTG DRD Stack) that fit to 32KB, however in most cases external > memory is required for code storage. So the speed of EMIF and caches are > very important to speed up the execution from external memory. > > > NIOS bus peripherals are little easier to create then MicroBlaze OPB > peripherals. > > Both NIOS Custom Instruction and MicroBlaze FSL are "cool" solutions. > > NIOS uCLinux is WAY easier to get started then MicroBlaze uCLinux thanks to > the full integration of the config and integration into Eclipse workbench, > as EDK6.3 is also Eclipse based it would be possible todo the same for > MicroBlaze uClinux config and build. > > hm.. I guess my answer was not a yes/no answer at all. Well there really is > not any big differences - only matter of taste what FPGA what tools one > chooses. > > Antti > > > > > > > > > > >Article: 74758
I thought V4 is AES?
Austin Lesea wrote:
> Triple 56 bit key DES, battery bcked key RAM, just like V2 and V2P. It
> is the fourth generation/technology part to have this core. Even though
> single and double key DES is no longer considered secure (by the federal
> gov't), triple DES with three differing keys is still considered safe
> for the time being. Next generation will require AES (in two years).
> >
> > Regards,
> > Igor Bizjak
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74759If you only need two output values you really want a single bit random function which returns 0 or 1. Then use that bit to select -5 or +5 something like: reg rval; integer seed; integer port; forever begin seed = 1; rval = $random (seed); port = rval ? +5 : -5; . . . end whizkid@gamebox.net (whizkid) wrote in message news:<edfc084c.0410180647.4b8159a1@posting.google.com>... > HI friends, > I want to assign a random value either +5 or -5 to a port . How do i > do that? > I tried $random function but it allows to assgin values between -5 and > +5 or 0 to 5 . But what i want is exactly +5 or else -5. Anyone know > how to do it .. > > thanks > whizkidArticle: 74760
Ray, I was wrong. Missed a bit or two. AES 256 bit keys in V4. Austin Ray Andraka wrote: > I thought V4 is AES? > > Austin Lesea wrote: > > >>Triple 56 bit key DES, battery bcked key RAM, just like V2 and V2P. It >>is the fourth generation/technology part to have this core. Even though >>single and double key DES is no longer considered secure (by the federal >>gov't), triple DES with three differing keys is still considered safe >>for the time being. Next generation will require AES (in two years). >> >>>Regards, >>>Igor Bizjak >>> >>> > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 74761
Timing. You might be looking at the accumulated sum one clock to early
or late.
Prasunp wrote:
> Hello:
>
> I am building a add-shift multiplier in Quartus and i seem to end up
> having a product that is multiplied by two or in other words is
> shifted one place. I look at my wiring and it seems right. What
> could i have messed up?
>
> Thank You
> Prasun
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74762Ray Andraka wrote: > Depends heavily on the design. Xilinx packs tighter for certain > arithmetic because of the structure of the LUT and carry chain: Altera's > carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one > for sum one for carry so it limits the number of inputs per bit. (snip) I still miss the XC4000 series where the carry chain was separate from the LUTs, for convenient implementation of saturating adders and MAX(a,b) functions by feeding the carry out or overflow back to an LUT input. -- glenArticle: 74763
In article <3e74ebc0.0410180819.403f5960@posting.google.com>, Tony K <bayshore_23@yahoo.com> wrote: >board MAC. ex. arp -s 192.168.1.0 00-00-01-02-03-04. I can verify the Is that the exact ip address? The default netmask for that would make it illegal. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 74764
So I have a page listing my virtex2 primitives and constraints: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html Where would I find a similar page for Altera's best? -- Prepend a 'b' to email me. Thanks.Article: 74765
whizkid@gamebox.net (whizkid) wrote in message news:<edfc084c.0410180647.4b8159a1@posting.google.com>... > HI friends, > I want to assign a random value either +5 or -5 to a port . How do i > do that? > I tried $random function but it allows to assgin values between -5 and > +5 or 0 to 5 . But what i want is exactly +5 or else -5. Anyone know > how to do it .. > > thanks > whizkid my_int = ($random%2*10)-5; -- SystemVerilog DPI tutorial on Project VeriPage: http://www.project-veripage.com/dpi_tutorial_1.php For subscribing to Project VeriPage mailing list: <URL: http://www.project-veripage.com/list/?p=subscribe&id=1>Article: 74766
fastgreen2000@yahoo.com (FGreen) wrote in message news:<d31579b8.0410180557.66d566da@posting.google.com>... > "Vikram" <knvikram@gmail.com> wrote in message news:<1098092745.293017.255220@f14g2000cwb.googlegroups.com>... > > FGreen wrote: > > > Hello, I'm seeing something very fundamentally wrong with my > > > simulation > > > in my testbench simulation. > > > > > > All inputs to the DUT look fine, but on the other side of input > > > buffers (IBUF & IBUFG), all signals are 'Z'. I instantiate the i/o > > > buffers as I always have done and never had this issue with other > > > simulators (nc-verilog, vcs). Nothing special about the signals - > > > they are straight inputs. > > > > > > I assume it's something about Modelsim (I'm rather new to this > > > simulator). What am I forgetting to do? > > > > > > Thanks. > > > > Can you give some more details, like: what are the models you are using > > for IBUF and IBUFG, whether it is RTL/Post-synthesis/Post-PAR > > simulation. And finally whether it is VHDL or Verilog ! > > > > Vikram > > Oh, sorry. > > I'm using verilog and it is an RTL simulation. I had compiled the > primitives by : compxlib -s mti_pe -f all -l all -o > C:\modeltech_xxx\xilinx_libs. > > I'm using unisim - I assume that's what you mean by 'models'? > > My search turned up a similar thread, but it didn't offer any solution > or replies. Typically when simulating with Xilinx primitives, I'll just add the primitive library files into my modelsim project as needed. In your case, I would add IBUF.v and IBUFG.v, then compile my whole project and start simulating. I've never had much luck pointing or creating libraries with ModelSim. Hope this helps, JeremyArticle: 74767
>And yet I would like to know whether the PLL does generate >the clocks correctly (PLL inclock:30MHz outclocks: c0 48MHz >c1 : 90MHz, e0: 90MHz (external use) > >Because of the fine package and the used board layers >it is almost impossible to measure the clocks externally with an oszilloscope. > >So the question is how to make the clocks visible with >the SignalTap Analyzer. I'm assuming there is some pin on your FPGA that you can get a scope on. How about patching your design to connect a FF to that pin and toggle the FF. That will give you a square wave that is half the frequency of your clock. That's not good enough if you need to verify duty cycle and/or jitter in your real design, but it should give you a quick sanity check. When doing the board layout, I always try to bring out a few spare pins to test points. Just for hacks like this. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 74768
Yeah, me too.
glen herrmannsfeldt wrote:
> Ray Andraka wrote:
>
> > Depends heavily on the design. Xilinx packs tighter for certain
> > arithmetic because of the structure of the LUT and carry chain: Altera's
> > carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one
> > for sum one for carry so it limits the number of inputs per bit.
>
> (snip)
>
> I still miss the XC4000 series where the carry chain was separate
> from the LUTs, for convenient implementation of saturating adders
> and MAX(a,b) functions by feeding the carry out or overflow
> back to an LUT input.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74769rickman <spamgoeshere4@yahoo.com> writes: > I don't understand your point. If you don't tell the tool what an > acceptable clock period is, then how is the tool supposed to know the > difference between a nanosecond and a fortnight? Tools are not people, > they can't reason. I don't expect it to reason. I just expect it to tell me the result. > Besides, how would *I* know what you find an > acceptable clock period if you don't tell me? I still see systems that > are clocked well below 10 MHz. I never said that 10 MHz was an unacceptable outcome. That has nothing to do with whether the tool should provide me with the result of a static timing analysis.Article: 74770
rickman <spamgoeshere4@yahoo.com> writes: > Who said the tool does not give you the results? I belive at least one > post here said that info *was* available. It was available only after I provided an explicit constraint. It was not obvious that this was what was required to get static timing analysis. If the tools are going to have a test in them somewhere along the lines of "if the user didn't specify a constraint, skip the static timing analysis", then they could at least output a message to that effect to the log.Article: 74771
"Jaime Andrés Aranguren Cardona" <jaac@nospam.sanjaac.com> writes: > I guess it would fit into an Spartan-3 XC3S200, right? I'd like to test it > with this FPGA. How can we do that? (I see that there are synthesized > netlists on Niktech's website). Why bother? There are comparable cores available that fit in an XC3S200, and for which you get HDL source code, not just a netlist. I completely fail to understand what MANIK brings to the party.Article: 74772
> IIRC the book "VHDL for Logic Synthesis" by Rushton has a good section > on writing VHDL testbenches, talks about file IO and so on. > > My preferred approach, when possible/sensible, is to write fairly > generic VHDL testbenches that read the stimulus and expected response > data from text files, and then drives the unit-under-test from that > data. This lets you use other tools to generate the input and output > datasets. I've used this to verify implementations of image processing > algorithms - prototype the algorithm in matlab, design the hardware, > then drive both the matlab and VHDL models with the same input data > files, comparing the results. This sounds like a powerful way to really check the video processing. What kind of video processing are you doing? And what do the VHDL models look like?Article: 74773
Hi Brad,
Brad Smallridge wrote:
> This sounds like a powerful way to really check the video processing.
> What kind of video processing are you doing? And what do the VHDL
> models look like?
I'm sure it could be more powerful, but it met my needs. I'm not doing
a lot of video/image work now, this is from a few years ago when I was
investigating some real-time remote sensing / image processing algorithms.
I've attached a sample test bench, maybe it will be useful in showing
you the overall structure and file IO. It's not particularly
sophisticated, but will give the general idea..
Regards,
John
-- Vhdl test bench created from schematic conv_eng.sch - Wed May 22 11:00:13 2002
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE UNISIM.Vcomponents.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.conv_types.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS
COMPONENT conv_eng
PORT( clk : IN STD_LOGIC;
d_strobe : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
reset : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
oen : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL d_strobe : STD_LOGIC;
SIGNAL data_in : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
SIGNAL data_out : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL oen : STD_LOGIC;
signal completed : std_logic;
constant T_clk : time := 50 ns;
constant T_su : time := 5 ns;
BEGIN
UUT: conv_eng PORT MAP(
clk => clk,
d_strobe => d_strobe,
data_in => data_in,
reset => reset,
data_out => data_out,
oen => oen
);
stimulus : PROCESS
variable pix_cnt : integer := 0;
variable pix_val : std_logic_vector(7 downto 0);
variable clk_cnt : integer := 0;
variable l_in : line;
file infile : text open read_mode is "image.txt";
procedure clock_cycle(signal clk : out std_logic) is
begin
wait for T_su;
clk <= '1';
wait for T_clk;
clk <= '0';
wait for T_clk-T_su;
end procedure;
BEGIN
-- reset everything for a few clock cycles
completed <= '0';
d_strobe <= '0';
reset <= '1';
clock_cycle(clk);
reset<= '0';
clock_cycle(clk);
-- run an image through the filter
for row in 0 to rows-1 loop
for col in 0 to cols-1 loop
-- check for end of file
assert not endfile(infile)
report "Premature end of file!"
severity failure;
readline(infile,l_in);
hread(l_in,pix_val);
data_in <= pix_val;
d_strobe <= '1';
clock_cycle(clk);
d_strobe <= '0';
for clk_cnt in 0 to 12 loop
clock_cycle(clk);
end loop;
end loop;
end loop;
-- drain the pipeline
data_in <= (others => '0');
for drain in 0 to cols loop
d_strobe <= '1';
clock_cycle(clk);
d_strobe <= '0';
for clk_cnt in 0 to 12 loop
clock_cycle(clk);
end loop;
end loop;
completed <= '1';
wait;
END PROCESS;
response:process
variable l_out : line;
file outfile : text open write_mode is "output.txt";
begin
wait on oen until oen'event and oen='1';
if(completed='1') then
wait;
elsif(oen'event and oen='1') then
hwrite(l_out,data_out);
writeline(outfile,l_out);
end if;
end process;
END;
Article: 74774Kenneth Land wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:41732E6A.B03165E7@yahoo.com... > > I know the NIOS-1 was designed to run in the ACEX parts as well as the > > Cyclone and others. Altera did not designed NIOS-II for the ACEX > > parts, I also don't think it comes in a 16 bit version. I have a need > > for a small, fast MCU. I have been designing my own to use with the > > Forth language. But the software side is a bit of work. The Altera > > site mentions some pretty high speeds for NIOS-1, but when you research > > it the speed doesn't even reach 40 MHz in the ACEX parts. I wondered if > > the alternate version runs any faster. > > > > I think all of these soft CPUs are a bit larger than what I would like > > to see. So for now, I'll stick with what I have. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > I tested the NiosI to 140MHz in my custom 4-layer Cyclone board. (w/ SDRAM > to 120MHz) > I'm running my NiosII at 75MHz right now, but Quartus says I'm good to at > least 100MHz. > > The gcc/gdb/Insight tool chain, particulary for NiosII in Legacy Mode, are > quite easy and good. > I haven't been able to get much out of the new Eclipse based IDE, but a new > release is here, and another more major one in Nov/Dec. > > NiosII can be had for <700LE's. The JTAG debug module is another 300-400 > LE's but is extremely powerful, and can easily be removed for production. > > I'm curious how much smaller you can go for a functional processor with a > real tool chain? The 700 LE number is in a Cyclone, not an ACEX part. I don't think Altera gives out NIOS-II code, so I don't think you can put it in an ACEX part. I'm also not sure what the NIOX core is, but it appears to be non-public still. The info from Altera says the NIOS-I only runs <40 MHz in an ACEX part. My goal is to reach ~600 LEs and over 60 MHz in an ACEX part. One of the critical paths in the prior design was through a stack pointer which is an adder/subtracter (+-1) with a load. I believe in the Cyclone this is one LE per bit while it is two in the ACEX and it is hard to get the logic to map to an optimal path. I may have to instantiate if this is still in a critical path. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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