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Antti Lukats wrote: > > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > news:cjq34n$hc1$1@bunyip.cc.uq.edu.au... > > Hi, > > > > whatisasics wrote: > > > Antti Lukats wrote: > > > > > >> http://uclinux.openchip.org/forum/viewtopic.php?t=4 > > >> > > >> here is proof :) > > >> > [snip] > > Indeed - has anyone reverse engineered NIOS yet? ;-) > > > > Regards, > > > > John > > Hi John, here you go! > > NIOS-1 GPL2 licensing > http://www.eecg.toronto.edu/~plavec/utnios.html > > NIOS-II verilog also exists, but it will not be GPL ;) I see that you have a benchmark to download. Is there any clock speed info on your design? I would be interested in how fast it can run in an ACEX EP1K part. How many LEs is it? Does it include the 16 bit version? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74726
Ben Jackson <ben@ben.com> wrote: : In article <41701FEE.E5673855@yahoo.com>, rickman <john@bluepal.net> wrote: : >Ben Jackson wrote: : >> If I remember right, I think the best combination of 5V tolerant and : >> cheap is XC9500XL. Straight XC9500 has a price premium now, and XV is : >> not 5V tolerant. : > : >I don't have full pricing in front of me, but the newest CPLD part from : >Xilinx that has 5 volt tolerance is the XCR3xxxXL family, : I guess the original poster wanted "5V TTL compatible". The XC9500XL : family will take Vccio = 5V and drive 5V out. The XCR3xxxXL will accept : 5V in but Vccio = Vcc = 3.3V. XC95XL takes only 3.3 Volt VCCIO, but is 5 Volt tolerant at the input -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 74727
NIOX features
- NI*S II ISA Compatible
- no pipeline
- no i/d cache
- barrel shift implemented
- interrupts implemented
- mul/div emulated by sw trap
synthesis results for Virtex-2
=========================================
Logic Utilization:
Number of Slice Flip Flops: 69 out of 10,240 1%
Number of 4 input LUTs: 1,138 out of 10,240 11%
Logic Distribution:
Number of occupied Slices: 736 out of 5,120 14%
Number of Slices containing only related logic: 736 out of 736
100%
Total Number 4 input LUTs: 1,427 out of 10,240 13%
Number used as logic: 1,138
Number used as a route-thru: 33
Number used for Dual Port RAMs: 256
(Two LUTs used per Dual Port RAM)
Antti
PS no need to ask any more "when do we see NI*S in Xilinx FPGA's" :)
Article: 74728So Antti, Can you answer the burning question: Does a Spartan-3 Nios-II beat a cyclone Microblaze in performance/area? How do the two compare? This is really interesting work, and a great demonstration of the real differences between the architectures I think (i.e. putting a core specifically designed and optimized for one, into the other) "Antti Lukats" <antti@case2000.com> wrote in message news:<cktokl$q7l$01$1@news.t-online.com>... > NIOX features > - NI*S II ISA Compatible > - no pipeline > - no i/d cache > - barrel shift implemented > - interrupts implemented > - mul/div emulated by sw trap > > synthesis results for Virtex-2 > ========================================= > Logic Utilization: > Number of Slice Flip Flops: 69 out of 10,240 1% > Number of 4 input LUTs: 1,138 out of 10,240 11% > Logic Distribution: > Number of occupied Slices: 736 out of 5,120 14% > Number of Slices containing only related logic: 736 out of 736 > 100% > Total Number 4 input LUTs: 1,427 out of 10,240 13% > Number used as logic: 1,138 > Number used as a route-thru: 33 > Number used for Dual Port RAMs: 256 > (Two LUTs used per Dual Port RAM) > > Antti > PS no need to ask any more "when do we see NI*S in Xilinx FPGA's" :)Article: 74729
In article <ckt766$2gi4$1@mail.cn99.com>, NoThisRAT <nothisrat@yahoo.com> wrote: >and the the value of BAR0 is "00000000h" The lower bits of the BAR are what tell the BIOS that it is active and should be used. You must set them properly. >Must I implementation the normal read/write >to make BAR0 get an address? No, the BIOS won't write there. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 74730
Antti Lukats wrote: > > the design clamis to be 1:1 drop in replacement for Altera NIOS and it looks > that is not 100% clean room implementation, so I guess the GPL license is > actual invalid because of that. > > The NIOS-1 GPL uses altera memprims, and I havent yet checked it with any > synthesis tools. > > The NIOS-II, thats different, its completly clean-room design, uses no > vendor primitives at all. some statistic are in my latest post about the > NIOX core ;) no FPGA tests yet with NIOX (NI*S II compatible) cpu yet. with > no optimization the NIOX looks like 60MHz+ in slow Virtex devices. I know the NIOS-1 was designed to run in the ACEX parts as well as the Cyclone and others. Altera did not designed NIOS-II for the ACEX parts, I also don't think it comes in a 16 bit version. I have a need for a small, fast MCU. I have been designing my own to use with the Forth language. But the software side is a bit of work. The Altera site mentions some pretty high speeds for NIOS-1, but when you research it the speed doesn't even reach 40 MHz in the ACEX parts. I wondered if the alternate version runs any faster. I think all of these soft CPUs are a bit larger than what I would like to see. So for now, I'll stick with what I have. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74731
Uwe Bonnes wrote: > > Ben Jackson <ben@ben.com> wrote: > : In article <41701FEE.E5673855@yahoo.com>, rickman <john@bluepal.net> wrote: > : >Ben Jackson wrote: > : >> If I remember right, I think the best combination of 5V tolerant and > : >> cheap is XC9500XL. Straight XC9500 has a price premium now, and XV is > : >> not 5V tolerant. > : > > : >I don't have full pricing in front of me, but the newest CPLD part from > : >Xilinx that has 5 volt tolerance is the XCR3xxxXL family, > > : I guess the original poster wanted "5V TTL compatible". The XC9500XL > : family will take Vccio = 5V and drive 5V out. The XCR3xxxXL will accept > : 5V in but Vccio = Vcc = 3.3V. > > XC95XL takes only 3.3 Volt VCCIO, but is 5 Volt tolerant at the input Yes, 5 volt TTL only requires the output to rise up to 2.4 volts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74732
There is no Fmax reported when I instantiated a DSP48 with internal input and output registers turned on. Anyone have any ideas, why this happened? Thanks.Article: 74733
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:cjq34n$hc1$1@bunyip.cc.uq.edu.au... > Hi, > > whatisasics wrote: > > Antti Lukats wrote: > > > >> http://uclinux.openchip.org/forum/viewtopic.php?t=4 > >> > >> here is proof :) > >> [snip] > Indeed - has anyone reverse engineered NIOS yet? ;-) > > Regards, > > John Hi John, here you go! NIOS-1 GPL2 licensing http://www.eecg.toronto.edu/~plavec/utnios.html NIOS-II verilog also exists, but it will not be GPL ;) AnttiArticle: 74734
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4172C4C1.7EB97771@yahoo.com... [snip] > > NIOS-1 GPL2 licensing > > http://www.eecg.toronto.edu/~plavec/utnios.html > > > > NIOS-II verilog also exists, but it will not be GPL ;) > > I see that you have a benchmark to download. Is there any clock speed > info on your design? I would be interested in how fast it can run in an > ACEX EP1K part. How many LEs is it? Does it include the 16 bit > version? Hi Rick, the NIOS-GPL includes CPU C-benchmarks, not FPGA benchmarking or statistics there the NIOS-1 is seems to be a university project - I simply just found it - haha just enter "NIOS verilog source" into google and that the 3rd hit! the design clamis to be 1:1 drop in replacement for Altera NIOS and it looks that is not 100% clean room implementation, so I guess the GPL license is actual invalid because of that. The NIOS-1 GPL uses altera memprims, and I havent yet checked it with any synthesis tools. The NIOS-II, thats different, its completly clean-room design, uses no vendor primitives at all. some statistic are in my latest post about the NIOX core ;) no FPGA tests yet with NIOX (NI*S II compatible) cpu yet. with no optimization the NIOX looks like 60MHz+ in slow Virtex devices. AnttiArticle: 74735
Hello, I'm seeing something very fundamentally wrong with my simulation in my testbench simulation. All inputs to the DUT look fine, but on the other side of input buffers (IBUF & IBUFG), all signals are 'Z'. I instantiate the i/o buffers as I always have done and never had this issue with other simulators (nc-verilog, vcs). Nothing special about the signals - they are straight inputs. I assume it's something about Modelsim (I'm rather new to this simulator). What am I forgetting to do? Thanks.Article: 74736
rickman wrote: > Antti Lukats wrote: > >>the design clamis to be 1:1 drop in replacement for Altera NIOS and it looks >>that is not 100% clean room implementation, so I guess the GPL license is >>actual invalid because of that. >> >>The NIOS-1 GPL uses altera memprims, and I havent yet checked it with any >>synthesis tools. >> >>The NIOS-II, thats different, its completly clean-room design, uses no >>vendor primitives at all. some statistic are in my latest post about the >>NIOX core ;) no FPGA tests yet with NIOX (NI*S II compatible) cpu yet. with >>no optimization the NIOX looks like 60MHz+ in slow Virtex devices. > > > I know the NIOS-1 was designed to run in the ACEX parts as well as the > Cyclone and others. Altera did not designed NIOS-II for the ACEX > parts, I also don't think it comes in a 16 bit version. No, but they do show 3 versions, claiming <600 <1,300 <1,800 LEs I could not find a size for the JTAG Debug module, as I doubt they include that in these numbers ? > I have a need for a small, fast MCU. I have been designing my own to use with the > Forth language. Interesting, and sounds usefull. Do you have Size/Speed indications ? Could you take the 600LE NIOS and use the <= 256 user opcode support, for better Forth support ? > But the software side is a bit of work. The Altera > site mentions some pretty high speeds for NIOS-1, but when you research > it the speed doesn't even reach 40 MHz in the ACEX parts. I wondered if > the alternate version runs any faster. > > I think all of these soft CPUs are a bit larger than what I would like > to see. So for now, I'll stick with what I have. Part of this is 'creeping featurism', as well as a general industry trend to skip 16 bits, plus the design is easier if the data size matches the PC size. 24 bits is supported in some DSPs, tho probably does not map into the Blocks seen in most FPGAs. Maybe an 18 bit Opcode and PC would be a better FPGA medium-core ? Would top out at ~4MBit code store, and a soft CPU optimised to run from a serial memory would be an interesting direction. -jgArticle: 74737
Chris wrote: > >> Chipscope Pro(tm) sure beats using a logic analyzer >=20 >=20 >=20 >=20 > Maybe I'll try this out, it looks like it might be worthwhile. >=20 It sure is worthwhile. I have a system which needs approx. 100 hours to=20 simulate 500 us in ModelSim. Doing the same thing in Chipscope takes 500 = us and gives me the essence of the results. Yes, I'm currently using the = free version of ModelSim XE, but Hey! I don't say that simulations are bad things either, but for some systems = it is just not feasable in a greater scale. During those 100 hours I=20 manage to do quite a few system implementation / Chipscope verification=20 iterations. Also, you can evaluate the full version of Chipscope for 60 days for=20 free. Should be enough time to get familiar with it... --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Research engineer, embedded systems Totalf=F6rsvarets forskningsinstitut Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 74738
>http://www.niktech.com > >Hardware Features > > .. >Software Development Tools >· GNU Assembler, Linker (binutils) >· GCC (C Compiler) >· GDB (Debugger) and Instruction Set Simulator >· Standalone C-Library (RedHat newlib) >· Modified version of DietLibc The GCC - link seems to be broken ... -- 42Bastian Do not email to bastian42@yahoo.com, it's a spam-only account :-) Use <same-name>@epost.de instead !Article: 74739
Hi @ all, I am trying to use the Quartus SignalTap Analyzer. Maybe someone can help me with my problem: In the current state of my design test I have programmed my device. The receiving logic does not run yet because there is no incoming data traffic yet so that no IDLE-->Low transition is recognized. (Start of packet). And yet I would like to know whether the PLL does generate the clocks correctly (PLL inclock:30MHz outclocks: c0 48MHz c1 : 90MHz, e0: 90MHz (external use) Because of the fine package and the used board layers it is almost impossible to measure the clocks externally with an oszilloscope. So the question is how to make the clocks visible with the SignalTap Analyzer. As I read in the application note it is said that clocks cannot be monitored. But I cannot imagine that such a basic condition for a synchronous design cannot be captured. What possibilities do I have ? Thank you for your help. Kind regards AndréArticle: 74740
ALuPin a écrit: [...] > So the question is how to make the clocks visible with > the SignalTap Analyzer. > As I read in the application note it is said that clocks > cannot be monitored. > > But I cannot imagine that such a basic condition for a synchronous > design cannot be captured. Hello The simple problem is that SignalTap uses on of these clocks to sample the data it monitors. You can't use a clock to sample itself, it stands to reason. The only way you can get around this is to generate a higher frequency clock to monitor your clocks but you may encounter performance problems because this clock will be quite fast. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 74741
FGreen wrote: > Hello, I'm seeing something very fundamentally wrong with my > simulation > in my testbench simulation. > > All inputs to the DUT look fine, but on the other side of input > buffers (IBUF & IBUFG), all signals are 'Z'. I instantiate the i/o > buffers as I always have done and never had this issue with other > simulators (nc-verilog, vcs). Nothing special about the signals - > they are straight inputs. > > I assume it's something about Modelsim (I'm rather new to this > simulator). What am I forgetting to do? > > Thanks. Can you give some more details, like: what are the models you are using for IBUF and IBUFG, whether it is RTL/Post-synthesis/Post-PAR simulation. And finally whether it is VHDL or Verilog ! VikramArticle: 74742
<Philippe Thomas> wrote in message news:<41729934$0$24889$afc38c87@news.optusnet.com.au>... > Do you know any reference design for 10M sample/sec 12-16bit resolution ADC > board with 4-16Ksample buffer? > AND/OR > A commercial board ADC board with above mentioned specs and with PC104+ PCI > or PC104 ISA or USB interface ? Not PC104 but high speed USB2.0 and 64Ms 12 Bit: http://comsec.com/wiki?UniversalSoftwareRadioPeripheral Kolja SulimmaArticle: 74743
"Walter Gallegos" <walter@chasque.apc.org> wrote in message news:10n2h60q87tig87@news.supernews.com... > The answare is > > 1 slice into a Spartan 3 > 16 LE into a MAX-II > > Can you compare this architectures as 1 Slice = 2 LE's ? > I agree that there some areas that you can't simply compare the two architectures. For example, I had an old design with an Altera 10K series that used a fully async RAM block. Now, move it to a Spartan 3 architecture and you see that you should use the whole chip just to make that block of async RAM! However, it is perfectly understandable that a user might need to compare different available options and to do this, he/she would need to have rough estimates to compare a Xilinx device to that of Altera. For example, recently I had this interesting offer for a an FPGA prototype board with the same price of $99 for an Altern EP1C12 or a Xilinx XC3S400. I would like to use a prototype board for very different designs so I had to compare between the two chips. As I program in VHDL and use synthesize tools, I don't really care for any specific architecture (unless something like your example or my example above happens) and the thing that matters in cases like that is you only look for the BIGGER FPGA. To do it, you need to compare and to compare you can only use rough estimates. Personally, I find the simple equation of 1 Slice = 2 LE a very good rough estimate and for many designs it gives you a good answer. You have a very specific design and need a very good answer? Fire your synthesize tool and see how much resources you'd really need!Article: 74744
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:41732E6A.B03165E7@yahoo.com... > I know the NIOS-1 was designed to run in the ACEX parts as well as the > Cyclone and others. Altera did not designed NIOS-II for the ACEX > parts, I also don't think it comes in a 16 bit version. I have a need > for a small, fast MCU. I have been designing my own to use with the > Forth language. But the software side is a bit of work. The Altera > site mentions some pretty high speeds for NIOS-1, but when you research > it the speed doesn't even reach 40 MHz in the ACEX parts. I wondered if > the alternate version runs any faster. > > I think all of these soft CPUs are a bit larger than what I would like > to see. So for now, I'll stick with what I have. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX I tested the NiosI to 140MHz in my custom 4-layer Cyclone board. (w/ SDRAM to 120MHz) I'm running my NiosII at 75MHz right now, but Quartus says I'm good to at least 100MHz. The gcc/gdb/Insight tool chain, particulary for NiosII in Legacy Mode, are quite easy and good. I haven't been able to get much out of the new Eclipse based IDE, but a new release is here, and another more major one in Nov/Dec. NiosII can be had for <700LE's. The JTAG debug module is another 300-400 LE's but is extremely powerful, and can easily be removed for production. I'm curious how much smaller you can go for a functional processor with a real tool chain? KenArticle: 74745
"Antti Lukats" <antti@case2000.com> wrote in message news:ckvs1e$ntu$00$1@news.t-online.com... > "Tails" <tails_naf@yahoo.com> wrote in message > news:987636ca.0410171546.15d5b86b@posting.google.com... > > So Antti, > > Can you answer the burning question: > > Does a Spartan-3 Nios-II beat a > > cyclone Microblaze in performance/area? > > How do the two compare? > > > > This is really interesting work, and a great demonstration of the real > > differences between the architectures I think (i.e. putting a core > > specifically designed and optimized for one, into the other) > > Ok, I think I can answer the burning question :) answer is: > > There is no significant differences at all ! > ---------------------------------------- > > MicroBlaze, NIOS-II and also OR1K look very similar as of ISA > > neither MicroBlaze or NIOS ISA is optimized or targetted for some specific > FPGA fabric. > > Sure MicroBlaze implementation is optimized for Xilinx primitives and NIOS > for Altera primitives but that goes only for the implementation not for the > CPU architecture per se. Same for NIOS-I its ISA is not in any optimized for > ACEX and it would be working quite nicely in Cyclone too. But Altera has > dropped NIOS-I. > > The differences come from the SoC builder and Bus architecture, differences > in bus mastering, IP cores used etc, not from the CPU architecture. > > NIOS has simultaneous multimastering in some cases this could be a benefit, > but only if really used properly. > This is very nice and easy to do. I have a design using 2 NiosI/II's that divides the load and really increases performance. Nice to have as an easy option. > Both MicroBlaze and NIOS being 32 bit CPU's are "memory hogs" smallest > reasonable amount of code/data memory is 32KB (assuming thats the only > memory available). With some care its possible to write real applications > (like full OTG DRD Stack) that fit to 32KB, however in most cases external > memory is required for code storage. So the speed of EMIF and caches are > very important to speed up the execution from external memory. > This may be true if you go the new HAL route, but I got my USB stack with fairly functional firmware into a 12KB onchip ram. (I used only standard C, linking etc.) > Both MicroBlaze and NIOS are not very good in terms of interrupt latency > unfortunatly :( at least when using default interrupt handler in C - hand > coded assembly int handler could have smaller latency but could impose other > problems. > In my system NiosI varies from 3uS-11uS, but the NiosII is a rock solid 8uS. (NiosII varies by only +/- a few clocks each time) Not sure how good these numbers are compared to others. > NIOS bus peripherals are little easier to create then MicroBlaze OPB > peripherals. > > Both NIOS Custom Instruction and MicroBlaze FSL are "cool" solutions. > > NIOS uCLinux is WAY easier to get started then MicroBlaze uCLinux thanks to > the full integration of the config and integration into Eclipse workbench, > as EDK6.3 is also Eclipse based it would be possible todo the same for > MicroBlaze uClinux config and build. > > hm.. I guess my answer was not a yes/no answer at all. Well there really is > not any big differences - only matter of taste what FPGA what tools one > chooses. > > Antti Antti, maybe we should run the test suite from the UT Nios project on all these systems. That might be useful? Ken > > > > > > > > > > >Article: 74746
"Antti Lukats" <antti@case2000.com> wrote in message news:<ckrbh1$kn7$04$1@news.t-online.com>... > > Netlists, Documentation and Development tools can be downloaded from > > http://www.niktech.com. > > 1) are you going to release the HDL sources? Similarly to you Antti, are you going to be releasing the HDL source for NIOX? Cheers, JonArticle: 74747
"Vikram" <knvikram@gmail.com> wrote in message news:<1098092745.293017.255220@f14g2000cwb.googlegroups.com>... > FGreen wrote: > > Hello, I'm seeing something very fundamentally wrong with my > > simulation > > in my testbench simulation. > > > > All inputs to the DUT look fine, but on the other side of input > > buffers (IBUF & IBUFG), all signals are 'Z'. I instantiate the i/o > > buffers as I always have done and never had this issue with other > > simulators (nc-verilog, vcs). Nothing special about the signals - > > they are straight inputs. > > > > I assume it's something about Modelsim (I'm rather new to this > > simulator). What am I forgetting to do? > > > > Thanks. > > Can you give some more details, like: what are the models you are using > for IBUF and IBUFG, whether it is RTL/Post-synthesis/Post-PAR > simulation. And finally whether it is VHDL or Verilog ! > > Vikram Oh, sorry. I'm using verilog and it is an RTL simulation. I had compiled the primitives by : compxlib -s mti_pe -f all -l all -o C:\modeltech_xxx\xilinx_libs. I'm using unisim - I assume that's what you mean by 'models'? My search turned up a similar thread, but it didn't offer any solution or replies.Article: 74748
>> The GCC - link seems to be broken ... Thanks a for reporting this problem; It is fixed now. http://www.niktech.com/manik-elf-toolchain.tar.gz >> are you going to release the HDL sources? We currently have no plans of releasing the HDL sources. We do have plans to add more open source Cores to the package. >> are you planning to port uClinux for MANIK? Yes we have plans of porting Operating Systems to the processor; uC/OS and uClinux seem to be good choices for a CPU like MANIK. Sandeep -- ----------------------------------------------------------------- http://www.niktech.com Specializing in FPGA based Processors -----------------------------------------------------------------Article: 74749
HI friends, I want to assign a random value either +5 or -5 to a port . How do i do that? I tried $random function but it allows to assgin values between -5 and +5 or 0 to 5 . But what i want is exactly +5 or else -5. Anyone know how to do it .. thanks whizkid
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