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Hello all I have designed a board with an XC3S400 and an XCF02S. I can configure both devices through the JTAG interface but master mode configuration doesn't work. I have a 3,3V compliant interface because I need 3,3V pins on all I/O banks. - M0-M2 pins are grounded - There is a 100 ohms resistor between Prog_b and /CF & pull-up - CCLK runs OK (2,5V) - D0 toggles between 1,5 & 3V ! - Done remains low I have all pull-ups on Done (470), Prog & Init (4,7k) Any help is welcome -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 74426
What is the difference between GLKP and the GLKS? I am trying to figure out if i have enough global clock resources for the clocks. Right now I have about 7 clocks coming into the GLKP pins. When i instantiate a bufg, does it matter if its a bufg for GLKS or GLKP? Is there something to take into consideration between P or S or can i act like all of these are global buffers giving me 16 buffers in total? Any help would be appreciatd thanks.Article: 74427
Hi I am a graduate student and would like to implement the SATA I Host Controller Link and Transport layers in an FPGA for my Project. I am just starting on the RTL coding but would like to plan ahead for the verification of my RTL design. Can anyone guide me towards how I could write a testbench to verify my design and how doable is it. Are there any freely available Simulation testbenches for SATA I in which I can plug in my RTL code for verification. Let me know if there is a more apprpriate forum to address this question. Thanks. VarnaviArticle: 74428
yyy wrote: > anyone have problems instantiating the verilog simprims (x_inv or > x_lut2, etc) in the phy_8_lvds before? Even though I have the > simprim library compiled in my Modelsim libraries, when I simulate > it complains that he can't find the crummy simprims. Thanks. Compiling the libraries is the first step, but you also need to link the libraries so they're visible to the simulator. You should have lines like this in your modelsim.ini file: SIMPRIMS_VER = c:\modeltech_5.8d\xilinx_libs\simprims_ver XILINXCORELIB = c:\modeltech_5.8d\xilinx_libs\XilinxCoreLib The paths point to the compiled Xilinx libraries. You can add these lines yourself or use the Modelsim "Import Library" wizard (File -> Import -> Library). RJArticle: 74429
"Nicolas Matringe" <nicolasmatringe001@numeri-cable.fr> wrote in message news:416AA011.5050205@numeri-cable.fr... > - D0 toggles between 1,5 & 3V ! Well, that's what's wrong. D0 needs to toggle between 0 and 3.3V. Do you have a short between D0 and an adjacent pad? Cheers, Syms.Article: 74430
"Hal Murray" <hmurray@suespammers.org> wrote in message news:DADF029988C14CBB1A0FC9A9C75CAAE6@in.webx.sUN8CHnE... > The idea is to kill the tap-changing jitter in trade for timing > wander as temperature or Vcc changes while still getting most > of the timing fixup from the DLL calibration step. > Hi Hal, You can sort of do this by stopping the CLKIN, but there are limits for how long. Check CAF passim. You can probably stop it long enough to do some experiments! Unfortunately, I don't think this is gonna work very well. Noise on Vccaux will affect the delay elements in the DCM, and your frequency resolution/accuracy is going to be crap if you can only have one tap selection. Cheers, Syms.Article: 74431
Hi Marc, I'm getting to the point where I'm gonna give up on the GCLK inputs. I'm gonna just use ordinary IOBs and use a DCM to fix up the source synchronous phase. The problem is the positioning of the GCLK balls on the package makes routing without through vias difficult (I use microvia boards). At 622 MHz, the inductance of the through vias is starting to hurt the SI. V. interesting point about the single ended clock. I always source terminate those, take them in on ordinary IOs, and retime them to a master clock. Too much pain in the past! Cheers, Syms. "Marc Randolph" <mrand@my-deja.com> wrote in message news:4JOdna9_pM_87ffcRVn-tg@comcast.com... > Howdy Symon, > > We are using the internal _DT resistors on a V2P7 for receiving a > LVDS clock that is slightly over 600 MHz, as well as the source > synchronous data that goes along with it. It technically works (we > never have bit errors over all operating conditions), but using a > differential probe at the vias immediately below the inputs pins show > that there isn't much margin - the signal quality looks pretty poor. > > A more serious problem that we had was with a 600+ MHz GCLK input. What > we believe we discovered was that a nearby GCLK input with a single > ended 3.3V 66 MHz clock was affecting its signal quality enough that > we'd sometimes miss clocks. The 66 MHz clock looked good (no excessive > overshoot or other noise on it). Lowering the frequency to 311 MHz, > with no change to routing, fixed the problem. > > Have fun, > > MarcArticle: 74432
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<ckd6rb$c62$1@bunyip.cc.uq.edu.au>... > > Peter Ryser wrote: > > >> What's the easiest way to partition one 128 MB dram into two 64 MB > >> sections with each section control by one of the ppc in the VP20? > > > > if you do not have any specific requirements (like "either one of the > > two processors must see its part of the memory at address zero") it is > > straight forward: > > > > 1) hook up both PPC to the same PLB together with the PLB SDRAM controller > > 2) write seperate linker scripts for each of the two processors. The > > first processor uses the memory in [0,64[ and the second one uses [64,128[. > > Nice solution - what will the caches do in this configuration? > Duplicate / thrash? Get incoherent? The caches for the two processors are fully independent and located within the individual PPC cores. So the behavior of them will be completely independent. You are correct, the instruction caches will duplicate, and the data caches will risk incoherency if one is not careful. The PPC architecture offers for a great deal of cache control from software, so with careful planning these issues can be dealt with. We just wrapped up a 2VP20 design utilizing both processors, where minimizing PLB cycles was of the utmost importance. In the software, we had a number of different types of data that we were dealing with: 70% random byte reads, with data accesses almost always near one of the last 320 bytes accessed 20% sequential byte writes, never needing to reaccess this data again 10% sequential word reads, never needing to access this data again <<1% word read/writes of status/flags/etc. Though we only have 128MB of SDRAM in our system, we have the controller decoding 256MB of PLB address. The Caches are configurable on 128MB boundaries, so mapping the SDRAM in this manner allows us (without using the TLB) to have both cached and non-cached access to the SDRAM. Using virtual memory through the TLB, is a slightly more complex alternative. The 70% class of data is simply read from cached memory. The 20% class of data is written to cached memory set to write-back mode. The first write to a new cache line is going to result in a miss. As we will be overwriting the entire line in memory, this read is unnecessary. To avoid this read, a new cache line is allocatted and set to zero, with the DCBZ intruction. As we no longer need the data once it has been written, at the time of allocatting a new cache line, the previous line is flushed, so the cache doesn't get wasted on this data. The 10% class of data can reasonably be handled in two ways, either by doing a read-multiple-word of size 32 bytes from non-cacheable memory, or by doing single reads from cacheable memory. As our data structure repeats on 12 byte boundaries it was easier to write the software using cached memory. By flushing each cacheline in this data stream when the last word is read, it made more of the cache available for the first class of data. As a trade off between cache performance, and code speed, the flushing in our application was only done every four cache lines. The 1% class of data was read/written from uncached memory. Using cacheable memory for this would have decreased overall performance. The point of this post, as to a software engineer all of this is in the rather obvious category, is that the PPC processor blocks are a very powerful piece of hardware, especially if one thinks carefully about the way in which the cache can be utilized. The optimization described more than doubled the speed at which the software would run, over simply treating all data as cacheable, in write back mode. The application I described, uses one PPC core and about 260 instructions (about 1/16 of the I-side cache) to take VGA resolution images, dewarp and downsample them to QVGA using a warp table compressed to 3 bits per ouput pixel, running at about 160 frames per second. The alternative was to use about 500 slices and 8 block rams, which would have required us to bump up to the next larger FPGA. From the Lego oriented perspective that we have come to look at FPGAs, the PPC core is really just a big cache with a PLB interface, and a complex state machine. From an engineering cost perspective, the software and hardware solution took about the same two weeks to implement and test. But... this was only because the engineer that did the implementation, an experienced FPGA designer, was forced by me (his evil boss) to write his first assembly code since his introductory computer architecture class in college. If he were to do something similar, now past the learning curve on both the assembly code, and implementing PLB masters in VHDL, the software would take about half as long as the hardware. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 74433
On Mon, 11 Oct 2004 19:35:37 -0700, Antti Lukats wrote: > "Varnavi" <sh_a_12@yahoo.com> wrote in message > news:a17d05bc.0410110754.713898b0@posting.google.com... >> Hi >> >> I am a graduate student and would like to implement the SATA I Host >> Controller Link and Transport layers in an FPGA for my Project. I am >> just starting on the RTL coding but would like to plan ahead for the >> verification of my RTL design. Can anyone guide me towards how I could >> write a testbench to verify my design and how doable is it. Are there >> any freely available Simulation testbenches for SATA I in which I can >> plug in my RTL code for verification. Let me know if there is a more >> apprpriate forum to address this question. Thanks. >> >> Varnavi > > 1) there is virtually nothing free for SATA > > are you doing it only as theoretical testbench or do you plan to verify it > in real FPGA design? > > There are NO SATA PHY IC's that can be purchased without major headache. > > And at least V2Pro/V4 RocketIO is not directly fully compliant with SATA > physical layer, so in case of FPGA verification what do you plan to use? > > Antti Are the SerDes in SATA significantly different from PCI Express and InfiniBand?, both of which work fine with RocketIO. SATA is a lower clock rate than PCI Express and InfiniBand but I would have thought the logic levels would have been the same.Article: 74434
Thomas Womack <twomack@chiark.greenend.org.uk> wrote in message news:<JTc*E4Awq@news.chiark.greenend.org.uk>... > I'm trying to simulate some Verilog to run on my XPort card. The card > plugs into a Gameboy, so any configuration of its FPGA has to include > a couple of provided blocks for interfacing to the Gameboy's bus. > > So the program begins `include "primary.v" Why are you including a verilog source in a verilog source? That's like including a C source in another C source. Simply add primary.v to your modelsim project. -aArticle: 74435
Hi, I have three clocks connected to input/output pins (not global clock buffers), and then inside the fpga i have a 3 input multiplexer to select between the three clock signals. I then route the output of the three input multiplexer to a bufg component. I was wondering if this is a valid way to globally route the clock, or if someone has a better idea. ANy help would be appreciated greatly THank you, JonathanArticle: 74436
sruthi <sruthi.teja@rediffmail.com> wrote in message news:<ee893ae.-1@webx.sUN8CHnE>... > I would like to implement Cache memory in to > FPGA / CPLD. I would like to use LRU replacement policy for that. > SO could any one suggest me whiich cache placement policy is best suited > for that, whether the fully associative or 2- way set assosiative. > > Is it possible to implement LRU fully assosiative > cache in to any FPGA or CPLD device family. Using LRU for 2 way only means 1 bit toggle per set line, but 4 way requires 4.3.2 states more trouble than its worth. Given all the states involved, it is indeed possible but the simpler schemes will give almost as good a result. Intel used a 3b (1,1,1) toggle hierarchy with almost as good a result called pseudo LRU for 1 of their 4way designs. If you are starting out in cache design in FPGA you should probably do a direct mapped (1 way) with random replacement. From there on onwards, it gets more complex for each extra feature. Fully associative cache is really out of the question for both FPGA & ASIC as the assoc row decode adds dearly to access times. But the various 2,4,8 way mapped schemes work almost as well. I have a Cache book by Jim Handy which goes from very light reading to quite deep once it gets into the more interesting issues but it never addresses the special issues regarding FPGA design, being written for TTL to ASIC readers. There is a way to get fully associative without requiring complex fast HW but it involves a more SW like approach ie hashing addresses into a somewhat empty table. The access time will be a faster cycle * some factor between 1-inf with an avg that can be close to 1.5 cycles for a 50% full ram. You trade 1 problem for varying acceess times and must keep memory table atleast 30% empty. This has been used for Inverse Page Table MMUs by IBM too. I am using it too since varying cycles don't bother me much. In more complex typical cache designs for multiple cpus trying to maintain cache coherancy, they already must get into varying timings depending on snoop, bus interference as well. regards johnjakson_usa_comArticle: 74437
I did not mention this in the previous post. This error seems to be
coming only if I try to contrain the routing to non-rectangular
regions.
E.g.:
Following UCF works fine:
INST "u1" AREA_GROUP=g1;
AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X11Y7;
AREA_GROUP g1 MODE=RECONFIG;
AREA_GROUP g1 PLACE=CLOSED;
But following does not:
INST "u1" AREA_GROUP=g1;
AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3;
AREA_GROUP g1 MODE=RECONFIG;
AREA_GROUP g1 PLACE=CLOSED;
Does this mean that I cannot constrain the routing to a region
composed of multiple rectangles like above? Or am I making some
mistake in the UCF?
I appreciate your reading this post.
Thanks,
Aman
aman_78in@yahoo.com (Aman Gayasen) wrote in message news:<ebfee7f.0410101337.661eba79@posting.google.com>...
> Hi,
>
> I am trying to place and route my design to a specific portion of the
> FPGA
> by using the Xilinx modular design flow, coupled with AREA_GROUP
> constraints.
> But the par for a module gives the following error message for some
> (not all) region constraints.
>
> FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute
> route area
> extrema. Process will terminate. To resolve this error, please
> consult the
> Answers Database and other online resources at
> http://support.xilinx.com. If
> you need further assistance, please open a Webcase by clicking on
> the
> "WebCase" link at http://support.xilinx.com
>
> I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is:
>
> INST "u1" AREA_GROUP=g1;
> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3;
> AREA_GROUP g1 MODE=RECONFIG;
> AREA_GROUP g1 PLACE=CLOSED;
>
>
> Could not find any help in the answers database at Xilinx.
> Can someone please help me?
>
> Thanks in anticipation.
> Aman
Article: 74438On Mon, 11 Oct 2004 12:25:55 -0700, Aman Gayasen wrote: > I did not mention this in the previous post. This error seems to be > coming only if I try to contrain the routing to non-rectangular > regions. > E.g.: > Following UCF works fine: > INST "u1" AREA_GROUP=g1; > AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X11Y7; > AREA_GROUP g1 MODE=RECONFIG; > AREA_GROUP g1 PLACE=CLOSED; > > > But following does not: > INST "u1" AREA_GROUP=g1; > AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3; > AREA_GROUP g1 MODE=RECONFIG; > AREA_GROUP g1 PLACE=CLOSED; > > Does this mean that I cannot constrain the routing to a region > composed of multiple rectangles like above? Or am I making some > mistake in the UCF? > > I appreciate your reading this post. > Thanks, > Aman > > aman_78in@yahoo.com (Aman Gayasen) wrote in message news:<ebfee7f.0410101337.661eba79@posting.google.com>... >> Hi, >> >> I am trying to place and route my design to a specific portion of the >> FPGA >> by using the Xilinx modular design flow, coupled with AREA_GROUP >> constraints. >> But the par for a module gives the following error message for some >> (not all) region constraints. >> >> FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute >> route area >> extrema. Process will terminate. To resolve this error, please >> consult the >> Answers Database and other online resources at >> http://support.xilinx.com. If >> you need further assistance, please open a Webcase by clicking on >> the >> "WebCase" link at http://support.xilinx.com >> >> I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is: >> >> INST "u1" AREA_GROUP=g1; >> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3; >> AREA_GROUP g1 MODE=RECONFIG; >> AREA_GROUP g1 PLACE=CLOSED; >> >> >> Could not find any help in the answers database at Xilinx. >> Can someone please help me? >> >> Thanks in anticipation. >> Aman Have you asked Xilinx? Open a webcase and they'll give you the answer. I'd guess that they probably are limited to rectangles, it would be pretty hard to handle other shapes.Article: 74439
Hi Gary,
I waited for you ... I had the following questions in my mind...
1. Why active high reset? The general procedure is to use active low
reset. Did you look @ spartran 3 data sheet to find out wether it has
active low reset f/f's or active high reset f/f's?
2. Is reset asynchronous? It is better to have it.
3. Do you wish to change N dynamically, over time?
o If yes, should N be sampled and used?
o If yes, then when should it be sampled.
o If no, then sometimes the trigger output 'll not become inactive
high.
4. Do you wish to change X dynamically, over time?
The logic is quite complex to implement. If X is static over time
(never changes any time), then the circuit gets reduced to a mod X counter.
5. Is the maximum speed with which A+/A-/B+/B- can change is 7.8 MHz?
6. What 'll be the dynamics of the enable signal ? Can it change any time ?
o If yes, can it change when the trigger is active (low)?
o If yes, what should happen to the trigger output?
o If no, what is the valid interval when it can make a change ?
7. What is the maximum speed of the clock?
Since the quadrature inputs can change @ 7.8 MHz, the sampling clock
should atleast be 7.8 * 2 = 15.6 MHz. Is the speed supported in spartran 3?
8. Can you visualise the circuit you want? If yes, can you just capture
it on a piece of paper and scan & send it to me?
9. You've mentioned that the counter is 24 bits wide. Is there any
specific reason for that?
10. You've not mentioned on what condition does the counter increment /
decrement.
Thanks & Regards,
Naren.
Narendran Kumaraguru Nathan wrote:
> Hi Gary,
> I am working in TooMuch Semiconductor solutions www.toomuchsemi.com.
> This is a startup (2 months old) and focuses on providing EDA &
> Verification solutions. We have experianced engineers in Design and
> Verification.
> We can help you do this, and we don't expect anything in return. The
> work doesn't include any risk/responsiblity from our part.
> We'll do this design and post it in the groups itself.
> Thanks & Regards,
> Naren.
>
> garyswindell@hotmail.com (G Swindell) wrote in message news:<4ae002c2.0410101308.1ff35942@posting.google.com>...
>
>>I need to accomplish the following using the Spartan-3 Starter Kit.
>>This is a small part of my overall project and I don't have time to do
>>it.
>>
>>Inputs-
>>
>>5V differential quadrature (A+ A- B+ B-) signal
>>Enable (active high)
>>Counter Reset (active high)
>>
>>Output-
>>
>>Trigger Pulse (active low)
>>
>>
>>Specifics-
>>
>>I need a trigger pulse that is n clocks wide (n should be changeable
>>in code- pulse length will need to range between 10us and 500us)
>>whenever the quadrature counter (24 bit) increments/decrements by x
>>counts (x should be changeable in code and will range from around 15
>>to 200). Quadrature input max speed is 7.8mhz. The trigger pulse
>>should only be output when the enable signal is active (the counter
>>can run all the time).
>>
>>I am not asking for free help, I just need a complete solution and I
>>will pay for it ;)
>>
>>Thanks,
>>
>>Gary
Article: 74440Jonathan, the issue could be the asynchronous (?) selection of the clocks. I would assume that you can easily generate glitches, and no circuitry likes uncontrolled glitches on the global clock lines. Virtex global buffers include a mux that can be used to select between two inputs with glich-free operation guaranteed. Peter Alfke > From: Jonathan <> > Organization: (none) > Newsgroups: comp.arch.fpga > Date: Mon, 11 Oct 2004 11:40:12 -0700 > Subject: multiplexing clocks > > Hi, > > I have three clocks connected to input/output pins (not global clock buffers), > and then inside the fpga i have a 3 input multiplexer to select between the > three clock signals. I then route the output of the three input multiplexer to > a bufg component. I was wondering if this is a valid way to globally route the > clock, or if someone has a better idea. ANy help would be appreciated greatly > > THank you, > > JonathanArticle: 74441
You cannot reduce leakage current by changing the bitstream. Peter Alfke > From: "bh" <spam_not@nosuch.com> > Organization: Optimum Online > Newsgroups: comp.arch.fpga > Date: Sun, 10 Oct 2004 21:01:31 GMT > Subject: Temperature considerations of inactive logic blocks > > I was curious if there is much difference in leakage current > or other heat-effecting conditions between FPGA logic blocks > that are programmed and those that are idle. > > Presumably, logic that is switching is generating heat. > However, is there an optimal programming state for > inactive gates in order to reduce heat? > > In particular, if I have 8 ARINC-429 channels in my > FPGA, but the current configuration of the system only > uses 2 of them, would it be beneficial (from a heat point > of view) to have a different bitstream that only has > 2 ARINC-429 channels? > > -bh > >Article: 74442
Comments, If you are using the DLL only (CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV), then the output is a delayed version of the input. If you want to stop the DCM from moving its taps, there is the "FREEZE_DLL" pin on the test primitive which when asserted just stops all tap updates. If this is something you think would be useful, contact your local FAE for assistance. Before you do, the tap value is ~22 ps in V2P, and ~15 ps in V4, so stopping all tap movement will be a really difficult thing to even detect that you have done (as the rest of the jitter tends to mask the tap jitter completely). Not being able to track temeprature then becomes the major source of error. Tap movement is not the source of anyone's problems. If you are using the DFS part of the DCM (the CLKFX output), then stopping the tap movement will result in no clock out at all. Stopping the input will also stop the output (until RESET is asserted again). The question of frequency accuracy is not applicable: a delay line can not change the incoming frequency, so frequency in = frequency out. The CLKFX synthesis is hard sync'ed every concurrence, so it, too, is exact as far as frequency goes. Austin Symon wrote: > "Hal Murray" <hmurray@suespammers.org> wrote in message > news:DADF029988C14CBB1A0FC9A9C75CAAE6@in.webx.sUN8CHnE... > >>The idea is to kill the tap-changing jitter in trade for timing >>wander as temperature or Vcc changes while still getting most >>of the timing fixup from the DLL calibration step. >> > > Hi Hal, > You can sort of do this by stopping the CLKIN, but there are limits for how > long. Check CAF passim. You can probably stop it long enough to do some > experiments! Unfortunately, I don't think this is gonna work very well. > Noise on Vccaux will affect the delay elements in the DCM, and your > frequency resolution/accuracy is going to be crap if you can only have one > tap selection. > Cheers, Syms. > >Article: 74443
Jonathan, It's important to read the manual (eg. UG012) on this one. To switch clocks the 'clock to be switched away from' should be toggling, or in the correct state depending on the type of BUFGMUX selected. There is also a set up time issue, so the select input shouldn't be asynchronous to the output clock. Remember, metastability is as unavoidable as death and taxes! Best, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:BD90370B.95F8%peter@xilinx.com... > Jonathan, the issue could be the asynchronous (?) selection of the clocks. I > would assume that you can easily generate glitches, and no circuitry likes > uncontrolled glitches on the global clock lines. > Virtex global buffers include a mux that can be used to select between two > inputs with glich-free operation guaranteed. > > Peter Alfke > > > From: Jonathan <> > > Organization: (none) > > Newsgroups: comp.arch.fpga > > Date: Mon, 11 Oct 2004 11:40:12 -0700 > > Subject: multiplexing clocks > > > > Hi, > > > > I have three clocks connected to input/output pins (not global clock buffers), > > and then inside the fpga i have a 3 input multiplexer to select between the > > three clock signals. I then route the output of the three input multiplexer to > > a bufg component. I was wondering if this is a valid way to globally route the > > clock, or if someone has a better idea. ANy help would be appreciated greatly > > > > THank you, > > > > Jonathan >Article: 74444
> If you are starting out in cache design in FPGA you should probably do > a direct mapped (1 way) with random replacement. From there on > onwards, it gets more complex for each extra feature. > What do you mean with random replacement in a direct mapped cache? With direct mapped you don't have a decision which block gets replaced. The block is determined by the address. That's one reason why direct mapped is simpler and a suitable choice for FPGAs. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74445
Peter Alfke wrote: > You cannot reduce leakage current by changing the bitstream. > Peter Alfke You mean Static leakage, in current Xilinx FPGAs ? It is not a bad idea, to have as well as Clock Enables and clock distribution management, a similar thing with Core Power ? Other fields do this already to mitigate the power hits of the finer processes, and it would cost a little die area. It would not surprise me to see this on future parts. Then, the P&R software could have two more targets : Minimum Clocked Power, and minimum Static Power :) > > >>From: "bh" <spam_not@nosuch.com> >>Organization: Optimum Online >>Newsgroups: comp.arch.fpga >>Date: Sun, 10 Oct 2004 21:01:31 GMT >>Subject: Temperature considerations of inactive logic blocks >> >>I was curious if there is much difference in leakage current >>or other heat-effecting conditions between FPGA logic blocks >>that are programmed and those that are idle. >> >>Presumably, logic that is switching is generating heat. >>However, is there an optimal programming state for >>inactive gates in order to reduce heat? >> >>In particular, if I have 8 ARINC-429 channels in my >>FPGA, but the current configuration of the system only >>uses 2 of them, would it be beneficial (from a heat point >>of view) to have a different bitstream that only has >>2 ARINC-429 channels? To answer this specific question, you should create two valid designs, and measure them. Depending on where the inactive channel CLOCKs are gated, (and even the physical placements) you could expect to find a power saving. -jgArticle: 74446
> http://xup.msu.edu have several interesting links. Try also > www.eece.unm.edu/xup for some tutorials on ISE, EDK and other tools. > > www.digilentinc.com they make the spartan3 starter kit for xilinx and > have other boards and addon modules including usb, ethernet etc > www.fpga4fun.com have a few boards for sale and good tutorials. > http://www.burched.biz/ sells boards > as do www.xess.com > http://www.fpga-games.com > http://www.seng.de/dlk_database.html Thanks for all the great links and info everybody! I really appreciate it. If you have any more, feel free to share =-) -ExtrariusArticle: 74447
Here is what I m trying to implement....in Xilinx 6.2.3 ISE with Modelsim SE. Everything works fine except when I try a post place and route simulation in Modelsim. I get a warning: # WARNING[1]: generictbw.timesim_vhw(49): No default binding for component: "gen_and_for_loop". (Generic "n" is not on the entity) and the waveforms dont come up.I looked at the source of the .vhw file that HDL bencher created based on the testbench waveform.Looked pretty ok. Whats wrong? Any ideas? library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity gen_and_for_loop is generic (n : integer := 2); port(in_and: in std_logic_vector((n-1) downto 0); y:out std_logic); end entity gen_and_for_loop; architecture behavioral of gen_and_for_loop is begin and_gate: process (in_and) is variable bit_and: std_logic; begin bit_and := '1'; for i in 0 to (n-1) loop bit_and := bit_and and in_and(i); end loop; y <= bit_and; end process and_gate; end architecture behavioral;Article: 74448
Back this summer Altera hosted a conference to promote using their device for DSP and Image Processing. One of the companies that came was BARCO. They license cores for JPEG/MPEG compression. DerekArticle: 74449
Yes, I have seen this. THe problem is im trying to select between three clocks. I am using a virtex II. I have 8 GLKP, and I am already using 7 of those global clock pins, leaving me only one left for the output of my three input mux. Is there such an item they have that has a three input bufgmux, or what would be a better solution to this?
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