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Try downloading our free demo of HOTMan and the HOTMan API. Look at the jtag example. We use compression on the bit stream and then put the bit file in a static array that can be compiled into a C program. There is a network component that let's you configurure over a network. Currently it runs under Windows, Solaris and Linux. The API is very portable (it compiles with gcc) we can do custom ports or you can buy the open source kit. Steve Casselman Virtual Computer Corporation www.vcc.com "Marcel" <marcelgl@hatespam.xs4all.nl> wrote in message news:3d10c058$0$3877$e4fe514c@dreader4.news.xs4all.nl... > Via Impact I know, but I don`t know if Impact alteres the bitfile before > sending. I know that jtag has much more overhead, but I`m stuck with the > hardware design now, so no way to change to slave serial mode :-( > > > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:aeqc95$9568o$2@ID-84877.news.dfncis.de... > > "Marcel" <marcelgl@hatespam.xs4all.nl> schrieb im Newsbeitrag > > news:3d10aa88$0$52042$e4fe514c@dreader3.news.xs4all.nl... > > > Did somebody managed to load a xilinx .bit fiel for spartan-2 devices > via > > > the jtag port. > > > > Sure, via the JTAG-progammer (now called IMPACT) > > > > > Xilinx has the xsvf file format, but the supplied file to load this > > contains > > > a lot of overhead and uses too much RAM for small embedded systems, so I > > > want to just to put the tap in the config state and shift the bit file > in. > > > > Do you really want to load the FPGA via JTAG? For this purpose, Serial > Slave > > mode is MUCH more appropriate. You only need to clock in the data > > sequentially and you are done. If you try to configure a FPGA via JTAG, > you > > need to process the JTAG protocoll, which has much overhead. > > > > > But after comparing the bitfile with a generated svf file it seems that > > the > > > data in the svf file is different. > > > > Sure, these are very different files. > > > > -- > > MfG > > Falk > > > > > > > > > >Article: 44426
This is not right. It's not a zero sum game. For all you know this guy could have created jobs by coming up with good ideas. Everyone is an immigrant or the offspring one. Steve "Spam Hater" <spam_hater_7@email.com> wrote in message news:3d101eab.4925791@64.164.98.7... > > Notice to potential employers: > > You will be displacing a US citizen who is qualified, and willing to > work for that salary. > > Make sure that you put a statement to that effect on the H1-B transfer > application. > > Nothing personal Farhad. I have a family to feed. > > > > On 17 Jun 2002 21:18:46 -0700, farhad@everdream.com (Farhad Abdolian) > wrote: > > >Hi, > >I am currntly on H1-B visa, and since my current employer has decided > >to close our office, I am looking for a new job, and a company to take > >over my H1-B visa while my green card application goes through (my > >wife is American). > > >Article: 44427
DAVID WRIGHT wrote: > Any experience/opinions on ATMEL CPLD development? > > After struggling with CYPRESS and XILINIX, it looks like my present choice > is ATMEL. I am trying to work thru one of their local representatives. He > seems to be OK. > > From my recent experiences I like the Atmel parts but their tools have to be improved. I dropped Atmel and switched to Xilinx and finished my design in a fraction of the time I wasted fighting with the Atmel tools. What problems did you have with the Xilinx and Cypress parts/tools? - TroyArticle: 44428
Troy Schultz wrote: > > DAVID WRIGHT wrote: > > Any experience/opinions on ATMEL CPLD development? > > > > After struggling with CYPRESS and XILINIX, it looks like my present choice > > is ATMEL. I am trying to work thru one of their local representatives. He > > seems to be OK. > > > From my recent experiences I like the Atmel parts but their tools have > to be improved. I dropped Atmel and switched to Xilinx and finished my > design in a fraction of the time I wasted fighting with the Atmel tools. > > What problems did you have with the Xilinx and Cypress parts/tools? Tool chains are like editors : everyone has their own ideas :) Here, we dislike the 'big green button' approach, and I have Atmel tools set up under a Programmers Editor Environment, with a flow very like ASM/HLL. This is very fast, gives Source/Reports in multiple windows, and allows a familiar editor. The install footprint for this is small, < 2MB zipped. Language: Depends which end of the scale you work at. We like to start at 16V8 and go up to ATF1508, and VHDL flows are not ideal for this, especially as resource gets tight. My preference is for a language that gives more direct silicon mapping & control, is faster, and can create test vectors. Test vectors are often overlooked in CPLD designs, but call me old fashioned - I like to have the silicon in the design loop ( learned from uC development ) it make a great reality check for the preceeding SW stages. For this, CUPL is very good - it has some wrinkles, but no 'brick walls'. Good reports are also VERY important, and the ATF fitters now have good map summaries, that show spare resource. ( You do need to 'approach from below'.) -jgArticle: 44429
Had problems getting WARP and tech support on Cypress. Had to return it. XILINIX needed about $2K to upgrade with time-based license. Only doing about one 500 gate design a year. So I am trying ATMEL. "Troy Schultz" <tschultz@canada.com> wrote in message news:3D10D98C.9080609@canada.com... > DAVID WRIGHT wrote: > > Any experience/opinions on ATMEL CPLD development? > > > > After struggling with CYPRESS and XILINIX, it looks like my present choice > > is ATMEL. I am trying to work thru one of their local representatives. He > > seems to be OK. > > > > > > From my recent experiences I like the Atmel parts but their tools have > to be improved. I dropped Atmel and switched to Xilinx and finished my > design in a fraction of the time I wasted fighting with the Atmel tools. > > What problems did you have with the Xilinx and Cypress parts/tools? > > - Troy > >Article: 44430
DAVID WRIGHT <dwright@srtorque.com> wrote: : Had problems getting WARP and tech support on Cypress. Had to return it. : XILINIX needed about $2K to upgrade with time-based license. Only doing : about one 500 gate design a year. So I am trying ATMEL. The free Xilinx Webpack should get you going. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 44431
Falk Brunner <Falk.Brunner@gmx.de> wrote: : "Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> schrieb im Newsbeitrag : news:aeqcr7$19b5$1@agate.berkeley.edu... :> In article <aeqc93$9568o$1@ID-84877.news.dfncis.de>, :> Falk Brunner <Falk.Brunner@gmx.de> wrote: :> >www.opencores.org :> :> B'ah, at least MY response would have forced him to do a little :> work on his class project. :) : ;-) Right. : But if he really thinks he will win by copy & paste, he will soon realize : (at least when he hit the ground of a real job) that he had better done it : himself. : So he will (sadly) end up in marketing ;-)) Even so I disliked the way he asked for help, maybe he is willing to learn. Let's see. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 44432
The free webpack will handle all the Xilinx CPLDs and if you want to hanlde FPGAs and want some of the added tools then the ISE Base-X which lists for US$695 can be had for US$99 if you speak with your local FAE and attend a free 1 day seminar on beginning VHDL. - Troy DAVID WRIGHT wrote: > Had problems getting WARP and tech support on Cypress. Had to return it. > XILINIX needed about $2K to upgrade with time-based license. Only doing > about one 500 gate design a year. So I am trying ATMEL. > > "Troy Schultz" <tschultz@canada.com> wrote in message > news:3D10D98C.9080609@canada.com... > >>DAVID WRIGHT wrote: >> >>>Any experience/opinions on ATMEL CPLD development? >>> >>>After struggling with CYPRESS and XILINIX, it looks like my present >> > choice > >>>is ATMEL. I am trying to work thru one of their local representatives. >> > He > >>>seems to be OK. >>> >>> >> >> From my recent experiences I like the Atmel parts but their tools have >>to be improved. I dropped Atmel and switched to Xilinx and finished my >>design in a fraction of the time I wasted fighting with the Atmel tools. >> >>What problems did you have with the Xilinx and Cypress parts/tools? >> >>- Troy >> >> > > >Article: 44433
I'm trying to put a placement statement in the UCF file to put a critical flip flop near a pin. The only way I know how to do this is like so: INST my_bel_name LOC = CLB_R17C17; where my_bel_name is the bel where the source of my_net is. The bel name may or may not have anything to do with the net name (as far as I can tell). So, knowing the net name, and being able to find the CLB in FPGA Editor, how do I find the bel name? (once I know the bel name I can find the CLB by searching for a bel in FPGA Express, but that doesn't help much) Thanks DanArticle: 44434
Mr. Spam_Hater, Don't worry about the subject, the normal procedure for INS is what you exactly described here, so there is no risk I will take the job from a person with my qualification who can do my job for the same sallary or even more. No one can get a H1-B visa unless the company puts an ad for the job and prooves that there are no local candidates for that job, before INS even concider the case. And do not worry, I don't take it personally, I am used to this kind of behavior, /Farhad spam_hater_7@email.com (Spam Hater) wrote in message news:<3d101eab.4925791@64.164.98.7>... > Notice to potential employers: > > You will be displacing a US citizen who is qualified, and willing to > work for that salary. > > Make sure that you put a statement to that effect on the H1-B transfer > application. > > Nothing personal Farhad. I have a family to feed. > > > > On 17 Jun 2002 21:18:46 -0700, farhad@everdream.com (Farhad Abdolian) > wrote: > > >Hi, > >I am currntly on H1-B visa, and since my current employer has decided > >to close our office, I am looking for a new job, and a company to take > >over my H1-B visa while my green card application goes through (my > >wife is American). > >Article: 44435
Hi, I can't use the programmer of Max-plus II on windows XP. I am using the ByteBlaster(MV) cable, but the programmer always said-- programming hardware not installed. but I can use it very well under windows98 that was install in the same Notebook. Is there anyone have the same experience.Article: 44436
> > >The other issue I have is with the use of 1206 caps for bypassing. Size > >is one parameter that does affect impedance at high frequencies, unlike > >capacitance. So why use a 1 uF cap in a 1206 package with a low SRF > >when a 0.1 uF cap in an 0603 package will work better at all frequencies > >above the SRF? I don't think the freqs much below SRF are important for > >these caps. If your clocks are above 40 MHz, for example, then your > >switching noise will start at 80 MHz and go well up beyond 500 MHz. The > >lower frequency noise by contrast is small and will be dealt with by the > >bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > >the band of interest is covered. > > > >Am I missing something? > There is another issue also. Smaller packages, 0603 versus 1206 for instance, most likely will need a ceramic dielectric with a higher dielectric constant. NPO dielectric has the best RF characteristics of commonly used ceramic dielectrics. X7R is worse and Z5U is terrible. Try to get the highest capacitance with the highest quality of dielectric. That means, given two capacitors one in 1206 but NPO and the other in 0603 but X7R or Z5U, go with the NPO in the larger package. To confirm this, look at the curves of loss versus frequency of the ceramic dielectrics in the manufacturers data sheets sometime. CharlesArticle: 44437
No, could you please tell me how to do that in VHDL? To be specific, I require the following. I have two dual port blockRAMs one used for external writing(external to FPGA) and internal reading. The other is used for External reading and internal writing (i.e. assume that one BlockRAM is used as a read memory space and the other as a write memory space). Now I want data-in of first BlockRAM and data-out of second blockRAM to connect to system data bus. And address buses of both BlockRAMs to be connected to system address bus (all through tri-state IO buffers as you suggested). Also external control signals of the FPGA(read,write,chip select,read/write clock) should be interfaced to the corresponding signals in both the BlockRAMs. Thanx in advance, Nagaraj CS rickman <spamgoeshere4@yahoo.com> wrote in message news:<3D109052.9B08CF60@yahoo.com>... > Block ram is not intended to be the same as a RAM chip. There is no tri > state buffer on the output. If you want to connect it to a bus, you > need to add the tri state buffer or use a mux. > > Do you know how to do that in an HDL?Article: 44438
No. My license for 1.5 does not expire. Supposidly. IIRC, 2.x has an annual license. Wish I recalled wrong, as I would like to upgrade. I never upgraded because I was told that I could NOT get a permanent license for versions >= 2.x I was told that the Synplicity folks were forcing them to do that. On Sun, 16 Jun 2002 16:38:30 -0500, Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > > >Spam Hater wrote: >> >> Now that they "own" the synthesizer again, hopefully they'll go back >> to the perpetual license. >> >> I'm stuck at 1.5i because my design environment can't tolerate a >> license that expires once a year. (Long story; don't ask.) >> > > > Can Foundation 1.5 or 2.1i run without a FLEXlm license? > > > >Kevin Brace (In general, don't respond to me directly, and respond >within the newsgroup.)Article: 44439
> Europian boards cost 2X more for less fns. I don't want to argue with you, but as one of the european vendors, I have to make a point here. When comparing prices, you should take the peripherals into account. When doing so, you will find out that the european boards that have been mentioned in this thread are pretty competitive (as of 2002-jun-19: 1EUR=0.9561USD). However, you have to make up your mind, what kind of peripherals you need, and what these peripherals are worth to you. Don't try to save the last penny here, as adding peripherals to a board later on will usually create more headaches (and is more expensive), than having it all on a single PCB. Best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic GmbH Brendel 20 D - 32257 Buende Tel.: +49 (0) 5223 4939755 Fax.: +49 (0) 5223 48945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 44440
Spam Hater wrote:
>
> No.
>
> My license for 1.5 does not expire. Supposidly.
>
> IIRC, 2.x has an annual license. Wish I recalled wrong, as I would
> like to upgrade.
>
> I never upgraded because I was told that I could NOT get a permanent
> license for versions >= 2.x I was told that the Synplicity folks were
> forcing them to do that.
>
Isn't the firm you are talking about Synopsys instead of
Synplicity which used to supply a Xilinx specific version of FPGA
Express to Xilinx?
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44441Hi, My first Xilinx effort: When using ISE4.2 how does one generate a VHDL netlist that uses the UNISIMS libraries? Going through the MAP process always seems to generate a netlist using SIMPRIM. Also, using the SIMPRIM netlist I can compile & simulate (Modelsim PE), but almost all internal gate level signals simulate to "X". Functional VHDL simulation works perfectly. XST compiles perfectly and the mapper report seems to reflect the correct status of the design.What am I missing here when using the structural netlist? Anthony.Article: 44442
Unfortunately, the only other faster P3's we have are dual 800 MHz, which are assigned to the CAD/EDA group. Nicholas Weaver mentioned the Athlons. We bought a K7 1000 PC with 1GB PC133 about two years ago. A coworker ran a similar version of the design on that PC and his P3 650. I believe he said the time was 1:30 on the P3 and 1:15 on the K7. I haven't kept track of CPU's as much as I should, since I'm so busy, so I don't know what the differences are between the K7 with the latest Athlons. I wish I had had the time to look at the Athlons. According to NT's task manager, neither his runs nor my runs have reached 1GB yet, approx 750 MB. Xilinx recommends 2GB memory for the XC2V6000. The FPGA resources are intentionally kept as minimal as possible, which is about 25% slice utilization. (The design is parallel processing flow through the FPGA.) We expect at least 65% utilization at the end of integration Also, my unofficial guestimate of the execution time, is that it will go up at least by the square as the utilization doubles. It went up quite noticably from <10% to 25% utilization. I'm sure part of this depends on the design and how hard the tools have to work during par. Mark rickman wrote: > I am looking at a new machine as well. I would like to get an idea of > what a faster P3 would do in your tests. Any chance you can run your > PAR on a faster P3 or even a laptop? I believe they had P3s running at > 1.3 GHz before they released the P4. It would be very instructive to > see how that compares to the current P4s. > > Mark wrote: > > > > Hello, > > > > From a single recent very unofficial PC performance comparison .... > > > > Target: Virtex II XC2V6000 > > Xilinx: ngdbuild, map, par, trce using Design Manager. 4.1i, sp3 > > > > PC A: 650 MHz Pentium III, 1GB PC100 > > Execution time: ~1 hr: 30 min (+/- 5 min) > > > > PC B: 2.4 GHz Pentium IV, 2 GB PC2100 > > Execution time: 40 min > > > > Caveate: This is only one comparison of a single run on each computer. > > Most of the time (A: 1hr, 11 min B: 35 min) was spent in par, where the CPU > > utilization was 100%, according to NT 4.0, sp6 task manager. par execution > > time ratio: 71/35 ~= 2.03. Memory speed ratio: 266/100 ~= 2.66. CPU speed > > ratio: 2400/650 ~= 3.69. Although CPU utilization was 100%, the execution time > > ratio seems to imply that memory bandwidth was the limiting factor. But, the > > CPU was not <100%, so it's unclear why the execution time was not shorter. > > (IOW, I don't know what else the CPU was doing.) Screen saver, virus scanner, > > email, etc. were off. > > > > I've heard several times that FPGA tools are CPU intensive, but I think that > > machine specification should consider factors in addition to CPU speed, e.g., > > memory bandwidth, size of memory (to hold database), and M/B/chipset. We also > > considered a dual-CPU M/B. Unfortunately, no tools, that we have, can take > > advantage of multiprocessor PCs. A multiprocessor PC, in our case, would allow > > us to do synthesis/simulation, while the Xilinx tools are running. (I've tried > > to script the flow, but cannot since we're using ChipScope.) > > > > I believe that Xilinx on Linux needs Wine (from Xilinx installation notes), > > which I "heard" elsewhere ends up being slightly slower than native code. For > > front-end tools, we use the Mentor tools, which I believe have been ported to > > Linux, but, I haven't tried any, yet.... (I've been hoping ISD Mag will do > > another "annual" comparison.) Microsoft and Linux seem close as fas as speed, > > but, Linux seems to be ahead wrt stability. > > > > I haven't used Altera since the Flex 10K and MaxPlusII, so I don't have any > > experience with the latest Altera FPGAs. I also have no experience with the > > Xeon CPUs. > > > > Hope this helps, > > Mark > > > > mac teh knife wrote: > > > > > We have started development using the new fpgas. We are evaluating the > > > virtex 2 and stratix devices. > > > What I'm finding out is my 2 year old machine ain't got what it takes to > > > crunch the files that can fill up > > > these multi million gate chips. I was wondering if anybody would care to > > > share with us the machine (PC) > > > they are using. Also has anybody evaluated linux vs window performance as > > > far as fpga applications are concerned. > > > > > > I'm looking at a P4 2.4ghz / 2 gig ram and 533 mhz front bus. I'm also > > > looking at a Xeon 2.4 g with 400 mhz > > > front bus. Does anybody know if there is a performance difference between > > > these two type of processors? > > > > > > Mac the knife is of course not my real name, I'm just so tired of spam that > > > posting to use net generates. > > > > > > thanks > > > Jerry > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44443
Hi I am working with an Altera Excalibur Nios development board version 1.1. Is it possible to configure the PLD (20K200) with more than 1 Nios cpu? What I would like to do is configure 1 cpu to be a master and the others as slaves. The master will then control the processess executed on the slaves etc. Ideally the slaves will not have to make use of external SRAM of FLASH. Is this concept possible and how can it be implemented? If not, have you any suggestions on what other route to consider? Thanks RyanArticle: 44444
Hi there is an example to download of 2 nios on a chip (excalibur kit) at this address: http://cnfm.cnfm.fr/ALTERA/ExcaliburN/Arbitrage.zip it 's on a french site, http://cnfm.cnfm.fr/ALTERA/Excalibur.htm, it's for examples and update for the ALTERA french university program. So it's in french, but i think it's understandable for english people. Excuse my english, i'm a french student. "Ryan" <ryans@cat.co.za> a écrit dans le message news: 3d12031a.0@obiwan.eastcoast.co.za... > Hi > > I am working with an Altera Excalibur Nios development board version 1.1. Is > it possible to configure the PLD (20K200) with more than 1 Nios cpu? What I > would like to do is configure 1 cpu to be a master and the others as slaves. > The master will then control the processess executed on the slaves etc. > Ideally the slaves will not have to make use of external SRAM of FLASH. Is > this concept possible and how can it be implemented? If not, have you any > suggestions on what other route to consider? > > Thanks > Ryan > >Article: 44445
None of the ATA specs that I can find (ATA6 or ATA4) even specify the maximum input or output voltage except to say that the minimum is still TTL levels (2.4V out high and 0.5V out low, 2.0V in high and 0.8V in low. "Ray Andraka" <ray@andraka.com> wrote in message news:3D1074DE.32670CFE@andraka.com... > I am pretty sure the ATA-5 still uses 5v, although it may limit the signal excursions > to 3.3v. The cable requirements are for the higher modes (don't remember which one it > starts on). Basically, there is a length restriction and it requires every other > conductor to be a ground. If you are using strictly a UDMA100 drive, you can design > to that interface, but if you need backwards compatibility you need to be able to > accept 5v signalling. > > I think getting an IBIS model for the interface is the stuff of fairy tales. There > are too many variations between manufacturers and installations, although if it is a > strictly UDMA100 installation it will be a lot more consistent. > > Rick Filipkiewicz wrote: > > > Ray Andraka wrote: > > > > > > I think that for IDE drives supporting UDMA100 (ATA mode 5) the IO supply and > > signalling are supposed to be 3.3V and there are some heavy requirements on the > > cable & connector for modes > 2. Any IBIS modelling might have to take the ribbon > > cable into account if the disk is not being directly mounted on the PCB with a > > right-angled socket. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44446
If you pipeline it, you can get a faster shifter in the fabric.
After considering the input and output pipeline registers needed for
the multiplier to operate at speed, you already have have the logic
needed for an in-the-fabric barrel shift, and with the in-the-fabric
version you have more placement freedom. If you want to use the
embedded multipliers, you can use more than one by overlapping
inputs similar to the way you would extend a conventional barrel
shift. You could correct for the sign,but I think it would be less
painful to extend the extra bit in logic rather than correcting the
sign.
Jacky Renaux wrote:
> I have a 18 bits barrel shifter to design , it is speed oriented
> I will use a virtexII multiplier to shift the datas
>
> The 18x18 option is signed which means only 17x17 can be done
>
> Does anybody has an idea to built up a 18 bits barrel shifter
> with a 17+sign bits multiplier ?
>
> thanks
>
>
> --
> Use our news server 'news.foorum.com' from anywhere.
> More details at: http://nnrpinfo.go.foorum.com/
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44447Hi, I'm starting with FPGA. I've just downloaded Xilinx WebPack and I'm going through the tutorials. Everything seems to work fine as far as I can tell. My question is: [how] can I view the results of the synthesis? I would expect to see a schematics made up from LUTs and FFs or a boolean expression for each FF or something of that sort. I want to try several different variations of the same design and see how it affects the result. Just like I do with assembler output produced by a C compiler. Am I missing something obvious here or is it too much to ask? Thanks, DmitriArticle: 44448
This is a multi-part message in MIME format. --------------0CF1106F80FFC83AE8D10E6E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Dmitri, Unfortunately the current version of XST does not have a schematic viewer. This will only be available in the next major software release (sometime later this year). Regards, Stephan Dmitri Katchalov wrote: > Hi, > > I'm starting with FPGA. I've just downloaded Xilinx WebPack > and I'm going through the tutorials. Everything seems to work > fine as far as I can tell. > > My question is: [how] can I view the results of the synthesis? > I would expect to see a schematics made up from LUTs and FFs > or a boolean expression for each FF or something of that sort. > > I want to try several different variations of the same design > and see how it affects the result. Just like I do with assembler > output produced by a C compiler. > > Am I missing something obvious here or is it too much to ask? > > Thanks, > DmitriArticle: 44449
Dmitri Katchalov wrote: > > Hi, > > I'm starting with FPGA. I've just downloaded Xilinx WebPack > and I'm going through the tutorials. Everything seems to work > fine as far as I can tell. > > My question is: [how] can I view the results of the synthesis? > I would expect to see a schematics made up from LUTs and FFs > or a boolean expression for each FF or something of that sort. > > I want to try several different variations of the same design > and see how it affects the result. Just like I do with assembler > output produced by a C compiler. > > Am I missing something obvious here or is it too much to ask? > > Thanks, > Dmitri The free tools don't have any block-schematic viewers, and looking at equations isn't very useful for anything other than very small designs. It would be best to study the floorplanner viewer where you can see and move all the logic primitives. Also, download the free modelsim which allows you to single-step thru vhdl and see all the signals.
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