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Hi, I have a architecture which contains memory and interconnections matrices embedded in them. Actually i have written C programs to generate these signals and the values for these signals are stored in files. So basically for different applications i have different files, So what i would like to do is , somehow figure out a way to build a controller which reprograms the configuration memory to accomodate the new files and release the old file from the system. But before that i am not able to find a way how to import these text files to the FPGA configuration memory. Actually i tried to synthesize the text files as part of VHDL program , but my synthesizer gave me a warning, that text files are not included in synthesis and i found later from the manual that this is not possible. For test purposes, i would like to atleast use two text files in the memory and when i want to reconfigure the architecture to the new applications, i would be able to the new text file and load the values for the interconnections matrices from the text file. I would have to keep loading them until the applications is completed. I think i have explained what i am trying to do . Can you please give me some insight whether it would be possible to do this at all. Actually i have tried to search the net for these kind of information and i am unable to get the information for the last 2 weeks. Thanks, Ram. Phil James-Roxby <phil.james-roxby@xilinx.com> wrote in message news:<3D613234.3C0BBD34@xilinx.com>... > Ramakrishnan wrote: > > > > Hi, > > Can someone tell me whether it is possible to dynamically > > reconfigure the contents of the memory in FPGA ,without connecting to > > a external PROM or a host computer ?. > > > > Thanks, > > > > Ram. > > You will have to be more specific than that. Do you mean the embedded > BlockRAM and Distributed RAM, or the configuration memory. The answer > for both is yes, but they are very different solutions. > Phil > -- > -------------------------------------------------------------- > __ > / /\/ Dr Phil James-Roxby Direct Dial: 720.652.3767 > \ \ Sr. Staff Software Engineer Fax : 720.652.3599 > / / Reconfigurable Logic Group > \_\/\ Xilinx Labs @ Longmont,CO Phil.James-Roxby@xilinx.com > > --------------------------------------------------------------Article: 46126
> As you know, Phillips hold the patent of I2C bus. But I also found somewhere > said many of these patents had expired. However I still wondered if I design > an I2C interface on my FPGA/CPLD chip and use this chip only in my system, > do I have to buy their license? The designed FPGA/CPLD chip itself will not > be a commercial product but this system will be. Hi David, This is MY take on this, and if you have any concerns, I suggest you contact Phillips about this. I believe when you buy a chip that has an "interface" that you have to interface to, you implicitly have the right to interface to it, period, and no additional license is needed. Again, simply MY opinion. AustinArticle: 46127
Hi, For the design with input and output only, I collect input of design to output of test generater and vice versa. However, when the design have INOUT port, How can i collect this to test generate mode? Thanks you. RealaArticle: 46128
Hi, I write a verilog code (design) , test generator and test bench in seperate file. I can compile for debugging. However, if I want to check the logic of internal node of the design. How can i do? make the internal node as a output? Thanks you. RealaArticle: 46129
Here are a few thing you may want to try.
1) Turn off Delayed Transaction if possible. You should be able to do
that through BIOS setup.
2) If the SCSI chip is supplied as a PCI card (Not an on-board PCI
device.), put that SCSI card into another system that you know your PCI
card works without it.
3) Figure out who designed the chipset (Northbridge), and if it is
designed by Compaq (Compaq used to design their own chipset.), tell your
customers (i.e., I suppose that's going to be Insight Electronics
Spartan-II PCI Development Kit customers . . .) that the PCI card
doesn't work with that particular chipset. You should be able to figure
out the chipset manufacturer by opening up the computer.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46130
Hi all,
Thanks for your reply and comments.
Surely, there is few words regarding this topic though "register" and
"flip-flop" words appears in a great frequency.
In my opinion, "register" is a bit-addressed memory element which might
be impemented as a latch or a flip-flop -- this kind of bit-independent
device.
Could you agree to me?
Daryl
Article: 46131Daryl wrote: > > Hi all, > Thanks for your reply and comments. > Surely, there is few words regarding this topic though "register" and > "flip-flop" words appears in a great frequency. > In my opinion, "register" is a bit-addressed memory element which might > be impemented as a latch or a flip-flop -- this kind of bit-independent > device. > Could you agree to me? I would not spend too much time worrying about this :) For an example of real data usage, take the Philips 74AHC374 data : It states "74AHC374; 74AHCT374 Octal D-type flip-flop;" then " 8-bit positive, edge-triggered register" then: " The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications." then : OPERATING MODES INPUTS INTERNAL FLIP-FLOPS OUTPUTS Load and read register (etc) Load register and disable outputs Q0 to Q7 : 3-state flip-flop outputs -jgArticle: 46132
Hello, I am a beginner in CPLD and have a difficulty in reading CPLD datasheet. (Altera's MAX3000 CPLD). It describes the hardware architecture of CPLD. Macrocells, Logic array block, Expander product terms, Programmable interconnect array... They are unfamiliar to me so it is hard to read the datasheet. Is there a good documentation or book which discusses more basic concepts about CPLD hardware architecture? Thanks in advance... :-)Article: 46133
Hi Ram,
I'll have a stab at this one. As far as I'm aware, you can't "import a
text file" into FPGA memory without a rgeat deal of external circuitry
etc, communications interfaces and so on. I think what you want to do
is to include the contents of your text file at synthesis time, so the
data is embedded in the resulting bitstream.
It sounds like you're doing some kind of signal routing. So, do you
want one bitstream that has a particular interconnection table, and
another bitstream with a different table, and be able to switch between
the two (by reconfiguring)? Or, would you like to place several
interconnection tables in one design (bitstream), and switch between
them in logic?
Either way, instead of including text files in your VHDL, you might want
to consider using constant arrays. They get synthesised as ROMs (and
possibly RAM with the write ports unconnected?).
For a constant array, use something like this:
entity my_design
port
(some_input : std_logic_vector(3 downto 0));
...
end my_design;
architecture ...
subtype connection_entry is std_logic_vector(3 downto 0); -- for
example
type connection_table is array(0 to 7) of connection_entry;
constant table1 : connection_table := ("0001","0010","0101" ...);
begin
some_output <= table1(to_integer(some_input));
end
I hope you get the idea.
In this way, you could have multiple connection tables in your design,
the choice of which is decided in real time, eg:
architecture ...
constant table1 : ...
constant table2 : ...
constant table3 : ...
-- and so on
begin
output <= table1(to_integer(some_input)) when selection="000" else
table2(to_integer(some_input)) when selection="001" else
... -- and so on
end
Alternatively, you could simply have a different design (bitstream) for
each connection table.
To automatically generate these things you can write a simple code
generator in a high level language (even VHDL!).
Reply in the newsgroup if you'd like some more info.
Hope this is helpful,
Rgds,
John
Article: 46134"Austin Franklin" <austin@da98rkroom.com> writes: > This is MY take on this, and if you have any concerns, I suggest you contact > Phillips about this. > > I believe when you buy a chip that has an "interface" that you have to > interface to, you implicitly have the right to interface to it, period, and > no additional license is needed. Again, simply MY opinion. So you would say that if I buy a chipset from Via that implements the Intel P4 front side bus interface, and a Foobarco J37 processor that implements the same bus, that I can build them into my product (with no Intel P4), and implicitly receive a license from Via and Foobarco to use the Intel P4 front side bus?Article: 46135
JinSoo Kim wrote: > > Hello, > > I am a beginner in CPLD and have a difficulty in reading CPLD datasheet. > (Altera's MAX3000 CPLD). > It describes the hardware architecture of CPLD. > Macrocells, Logic array block, Expander product terms, Programmable > interconnect array... > They are unfamiliar to me so it is hard to read the datasheet. > Is there a good documentation or book which discusses more basic concepts > about CPLD hardware architecture? > > Thanks in advance... :-) Hi, I think http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm could be a useful site for You. Search for Programmable ASICs in chapters 4-8. Regards, Veli-MattiArticle: 46136
Thanks for the info, Ray. Adrian Ray Andraka <ray@andraka.com> wrote in message news:3D61AD73.3B9018CE@andraka.com... > Polyphase filtering is basically using parallel filter banks, with only some of > the samples getting processed by each "branch". For example, for a filter with > 3 branches, each filter is using every third sample, but the filters are offset > by a sample, essentially using different phases of the signal for each. > Polyphase filtering is used whe you have sample rate changes. an up or down > sample by an integer ratio is the easiest. > > In the case of a decimation, you mathematically would do a low pass filter, > followed by discarding the samples between every Nth sample. As it turns out, > there is no need to do the computations for those discarded samples, and that is > what polyphase is all about. If you work the filter backwards eliminating the > dropped samples from the math, you'll see that you wind up with N filter banks, > each of which is fead by a different 'phase' of the input and whose outputs are > summed. Each bank is working at the decimated sample rate instead of the input > sample rate, so while you still have the same number of taps, the computation > rate is lower. Polyphase is not all that useful with high decimation ratios. > > Is your average an integrate and dump, or is it a moving average. Both provide > a filter with a frequency response equal to the sunc function (sinx/x), however > the integrate and dump is also decimated at the output by the number of samples > in the average. The moving average is not inherently decimated. Provided this > filter shape is satisfactory, You'd be best off sticking with the average. For > a moving average, or even a decimation by some factor other than N, you can use > a CIC (Hogenaur) filter, which is essentially an integrator, decimation and comb > (difference) filter. It is basically a hardware implementation of a recursive > moving average filter. While the CIC's response is not spectacular, it does > provide an efficient means for filtering with very high decimation ratios, and > unlike the integrate and dump several stages can be cascaded to steepen the > filter response. Normally, this will be used in conjuction with a small FIR > clean-up filter to take out the droop and to put most of the sidelobe energy > into the stopband. > > Noddy wrote: > > > I'm using FIR filters in Spartan IIs (200) for radio astronomical > > applications. Right now I have two 40 tap LP filters per FPGA (cut-off > > approximately 0.125) running at 32MHz. The input is a 4 bit quadrature > > signal, with post detection integration after the filters of the order of > > 2^14 samples. This long integration is neccessary in order to obtain the > > signal which is about 6 orders of magnitude less than the noise. > > > > Now, my question is this: would there be any advantage in switching to a > > polyphase filtering technique? I don't know much about it...I see it usually > > involves some decimation and interpolation, although I am not keen to start > > throwing away samples as every sample helps to increase the SNR by averaging > > out the noise. > > > > Thanks > > > > Adrian > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 46137
I don't have much time at the moment to start designing, so is there by any chance a Core generated module from Xilinx which I can drop into my design which will allow me to provide the multiple sets of filter coefficients? I'm using Foundation 3.3 Thanks Adrian Ray Andraka <ray@andraka.com> wrote in message news:3D61AD73.3B9018CE@andraka.com... > Polyphase filtering is basically using parallel filter banks, with only some of > the samples getting processed by each "branch". For example, for a filter with > 3 branches, each filter is using every third sample, but the filters are offset > by a sample, essentially using different phases of the signal for each. > Polyphase filtering is used whe you have sample rate changes. an up or down > sample by an integer ratio is the easiest. > > In the case of a decimation, you mathematically would do a low pass filter, > followed by discarding the samples between every Nth sample. As it turns out, > there is no need to do the computations for those discarded samples, and that is > what polyphase is all about. If you work the filter backwards eliminating the > dropped samples from the math, you'll see that you wind up with N filter banks, > each of which is fead by a different 'phase' of the input and whose outputs are > summed. Each bank is working at the decimated sample rate instead of the input > sample rate, so while you still have the same number of taps, the computation > rate is lower. Polyphase is not all that useful with high decimation ratios. > > Is your average an integrate and dump, or is it a moving average. Both provide > a filter with a frequency response equal to the sunc function (sinx/x), however > the integrate and dump is also decimated at the output by the number of samples > in the average. The moving average is not inherently decimated. Provided this > filter shape is satisfactory, You'd be best off sticking with the average. For > a moving average, or even a decimation by some factor other than N, you can use > a CIC (Hogenaur) filter, which is essentially an integrator, decimation and comb > (difference) filter. It is basically a hardware implementation of a recursive > moving average filter. While the CIC's response is not spectacular, it does > provide an efficient means for filtering with very high decimation ratios, and > unlike the integrate and dump several stages can be cascaded to steepen the > filter response. Normally, this will be used in conjuction with a small FIR > clean-up filter to take out the droop and to put most of the sidelobe energy > into the stopband. > > Noddy wrote: > > > I'm using FIR filters in Spartan IIs (200) for radio astronomical > > applications. Right now I have two 40 tap LP filters per FPGA (cut-off > > approximately 0.125) running at 32MHz. The input is a 4 bit quadrature > > signal, with post detection integration after the filters of the order of > > 2^14 samples. This long integration is neccessary in order to obtain the > > signal which is about 6 orders of magnitude less than the noise. > > > > Now, my question is this: would there be any advantage in switching to a > > polyphase filtering technique? I don't know much about it...I see it usually > > involves some decimation and interpolation, although I am not keen to start > > throwing away samples as every sample helps to increase the SNR by averaging > > out the noise. > > > > Thanks > > > > Adrian > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 46138
lng wrote: > What kind of simulation did you run? timing, functional? Functional > Have you tried to use the "gate point simulation.." , it may work!!! > No Thanks! Patrik -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 46139
JinSoo Kim wrote: > > Hello, > > I am a beginner in CPLD and have a difficulty in reading CPLD datasheet. > (Altera's MAX3000 CPLD). > It describes the hardware architecture of CPLD. > Macrocells, Logic array block, Expander product terms, Programmable > interconnect array... > They are unfamiliar to me so it is hard to read the datasheet. > Is there a good documentation or book which discusses more basic concepts > about CPLD hardware architecture? > > Thanks in advance... :-) It's something of a trend to make PLDs 'black boxes'. A good place to start is with SPLDs, like the ATF16V8BQL data. This shows Product terms, macrocells, (registered & Combinatorial) and is small enough to 'see' every logic cross point. If you also have the tools 'alive' as you learn, you can get information from the report files, to a detail level not in the data sheets. eg Atmel's CUPL .DOC file, has optimised equations, Product term -> Macrocell Mappings, and also fuse info (SPLD) Further up the complexity scale, the CPLD Fitter report files ( .FIT or .RPT ) have the equations, and mapping information. As an example, here is a snippet from an ATF1502.FIT file : ( likely to need un-wrap ) DCERP Field = Summary of Allocations. ||||| |||||_Preset [p,-] == p = PT preset, - No Preset. |||| ||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset. ||| |||___Clock Enable [e,-] == e = Product Term, - always enabled, - none. || ||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock. | |_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff. For input only = INPUT. MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT output_slew MC1 4 OE5 DB0 C---- bAD0 Lg-g- -- -- 4 slow MC2 5 PT Pa2 C---- oePa2 Dge-- NA -- 5 slow MC3 6 PT Pa1 C---- oePa1 Dge-- NA -- 5 slow MC28 28 OE5 DB7 C---- bAD2 Lg-g- FbFWrPcU -- 5 slow From this, you can see the PinNodeName, the Buried NodeName, possible foldback nodename, and the Output enable mapping, plus the Product terms used ( out of 5/MCell ), and the DCERP tags show which global lines are routed to the MC controls of Clock, Clock Enable, Preset, Reset. This design has been packed to have two, or three (MC28), nodes/names per macrocell ( A good analogy is the MAP file produced by a microcontroller linker. ) 'Programmable Interconnect Array', and their ilk, are sparse crosspoint arrays, with no logic, but that reduce the total fuse count in the devices, ( and so lower the prices ), but that introduce a FanIn ceiling to bump into... HTH -jgArticle: 46140
Ray Andraka wrote: > Try setting the TimingChecksOn generic to false. I've had troubles in the > past when that is in the (default) on state interfacing with RTL designs. I tried that with the same result. > Also, you may be bringing the clock high at the same time you are bringing > the WE to inactive at the very beginning of your sim. Try starting with the > clock low. I think that the simulation model is incorrect. It is not true dual port and the behaviour is wrong. I've got this from xilinx support: ----------- I have just found the following internal solution. Keywords: unisim, functional, simulation, RAMB4_Sm_Sn, RAMB16_Sm_Sn Urgency: Standard Description: When performing a functional (behavioral) simulation on a RAMB16_S9_S9 the following error message may be seen after issuing the vsim (load design) command: # ** Warning: Invalid ADDRESS: XXXXXXXXXXX. Memory contents will be set to 'X'. The simulation procedes but as suggested by the warning, the memory contents are not initialised to correct values. The warning occured because only one of the clock inputs to the dual port RAM had passed through an IBUFG. The following workarounds will cure the problem: 1) Ensure that both clocks do NOT have an IBUFG directly instantiated in the code. IBUFGs will be inferred automatically if the default project options are set. OR 2) Ensure that both clocks have an IBUFG. ------------ Solution 2 solved my problem in the simple test code but not my real design. I have to investigate it further. Thanks! Patrik > > Patrik Eriksson wrote: > > >>When I simulates the following code this warning message is displayed at >>time 0ns. >> >># ** Warning: Invalid ADDRESS: XXXXXXXXXX. Memory contents will be set >>to 'X'. >># Time: 0 ps Iteration: 3 Instance: /theram >> >>This means that I can't simulate with correct INIT values!! >>All addresses and control signals are constant but the clock inputs are >>toggled. >> >>Have I done anything stupid? Is there an error in the simulation model? >>This code is a debug version of my real design just to track the >>simulation error. >> >>I thought that if WEx is de-asserted nothing should happen to the memory >>contents whatever the other signals looks like. >> >>/Patrik Eriksson >>----------- >> >>library ieee; >> use ieee.std_logic_1164.all; >> use ieee.std_logic_unsigned.all; >> >> -- synthesis translate_off >> library unisim; >> -- synthesis translate_on >> >> entity bram_tb is >> >> end entity bram_tb; >> >> architecture sim of bram_tb is >> >> component BUFG >> port ( >> I : in std_logic; >> O : out std_logic); >> end component; >> >> component IBUFGDS_LVPECL_33 >> port ( >> O : out std_ulogic; >> I : in std_ulogic; >> IB : in std_ulogic); >> end component; >> >> component DCM >> -- synthesis translate_off >> generic ( >> DLL_FREQUENCY_MODE : string := "LOW"; >> CLKOUT_PHASE_SHIFT : string := "NONE"; >> PHASE_SHIFT : integer := 0; >> CLKFX_MULTIPLY : integer := 4; >> CLKDV_DIVIDE : real := 2.0 >> ); >> -- synthesis translate_on >> port ( >> CLKIN : in std_logic; >> CLKFB : in std_logic; >> DSSEN : in std_logic; >> PSINCDEC : in std_logic; >> PSEN : in std_logic; >> PSCLK : in std_logic; >> RST : in std_logic; >> CLK0 : out std_logic; >> CLK90 : out std_logic; >> CLK180 : out std_logic; >> CLK270 : out std_logic; >> CLK2X : out std_logic; >> CLK2X180 : out std_logic; >> CLKDV : out std_logic; >> CLKFX : out std_logic; >> CLKFX180 : out std_logic; >> LOCKED : out std_logic; >> PSDONE : out std_logic; >> STATUS : out std_logic_vector(7 downto 0) >> ); >> end component; >> >> component RAMB16_S9_S9 >> -- synthesis translate_off >> generic ( >> WRITE_MODE_A : string; >> WRITE_MODE_B : string; >> INITP_00, INITP_01, INITP_02, INITP_03, >> INITP_04, INITP_05, INITP_06, INITP_07, >> INIT_00, INIT_01, INIT_02, INIT_03, >> INIT_04, INIT_05, INIT_06, INIT_07, >> INIT_08, INIT_09, INIT_0A, INIT_0B, >> INIT_0C, INIT_0D, INIT_0E, INIT_0F, >> INIT_10, INIT_11, INIT_12, INIT_13, >> INIT_14, INIT_15, INIT_16, INIT_17, >> INIT_18, INIT_19, INIT_1A, INIT_1B, >> INIT_1C, INIT_1D, INIT_1E, INIT_1F, >> INIT_20, INIT_21, INIT_22, INIT_23, >> INIT_24, INIT_25, INIT_26, INIT_27, >> INIT_28, INIT_29, INIT_2A, INIT_2B, >> INIT_2C, INIT_2D, INIT_2E, INIT_2F, >> INIT_30, INIT_31, INIT_32, INIT_33, >> INIT_34, INIT_35, INIT_36, INIT_37, >> INIT_38, INIT_39, INIT_3A, INIT_3B, >> INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector := >> X"0000000000000000000000000000000000000000000000000000000000000000" >> ); >> -- synthesis translate_on >> >> port ( >> DIA : in std_logic_vector(7 downto 0); >> DIPA : in std_logic_vector(0 downto 0); >> DIB : in std_logic_vector(7 downto 0); >> DIPB : in std_logic_vector(0 downto 0); >> ENA : in std_ulogic; >> ENB : in std_ulogic; >> WEA : in std_ulogic; >> WEB : in std_ulogic; >> SSRA : in std_ulogic; >> SSRB : in std_ulogic; >> CLKA : in std_ulogic; >> CLKB : in std_ulogic; >> ADDRA : in std_logic_vector(10 downto 0); >> ADDRB : in std_logic_vector(10 downto 0); >> DOA : out std_logic_vector(7 downto 0); >> DOPA : out std_logic_vector(0 downto 0); >> DOB : out std_logic_vector(7 downto 0); >> DOPB : out std_logic_vector(0 downto 0) >> ); >> >> end component; >> >> constant INITP : bit_vector := >>X"1041000100001400010000100040100001400010004100041000100004000104"; >> constant INIT : bit_vector := >>X"1001000100001000010000100000100001000010000100001000100001000100"; >> >> signal clk_p, clk_n, clk, rst : std_logic; >> signal clk_ibufg, clk_bufg : std_logic; >> >> begin -- architecture sim >> >> INBUF: IBUFGDS_LVPECL_33 >> port map ( >> O = clk_ibufg, >> I = clk_p, >> IB = clk_n); >> >> GLOBALBUFFER: BUFG >> port map ( >> I = clk_ibufg, >> O = clk_bufg); >> >> clk <= clk_bufg; >> >> THERAM: RAMB16_S9_S9 >> generic map ( >> WRITE_MODE_A = "WRITE_FIRST", >> WRITE_MODE_B = "READ_FIRST", >> INITP_00 = INITP, >> INITP_01 = INITP, >> INITP_02 = INITP, >> INITP_03 = INITP, >> INITP_04 = INITP, >> INITP_05 = INITP, >> INITP_06 = INITP, >> INITP_07 = INITP, >> INIT_00 = INIT, >> INIT_01 = INIT, >> INIT_02 = INIT, >> INIT_03 = INIT, >> INIT_04 = INIT, >> INIT_05 = INIT, >> INIT_06 = INIT, >> INIT_07 = INIT, >> INIT_08 = INIT, >> INIT_09 = INIT, >> INIT_0A = INIT, >> INIT_0B = INIT, >> INIT_0C = INIT, >> INIT_0D = INIT, >> INIT_0E = INIT, >> INIT_0F = INIT, >> INIT_10 = INIT, >> INIT_11 = INIT, >> INIT_12 = INIT, >> INIT_13 = INIT, >> INIT_14 = INIT, >> INIT_15 = INIT, >> INIT_16 = INIT, >> INIT_17 = INIT, >> INIT_18 = INIT, >> INIT_19 = INIT, >> INIT_1A = INIT, >> INIT_1B = INIT, >> INIT_1C = INIT, >> INIT_1D = INIT, >> INIT_1E = INIT, >> INIT_1F = INIT, >> INIT_20 = INIT, >> INIT_21 = INIT, >> INIT_22 = INIT, >> INIT_23 = INIT, >> INIT_24 = INIT, >> INIT_25 = INIT, >> INIT_26 = INIT, >> INIT_27 = INIT, >> INIT_28 = INIT, >> INIT_29 = INIT, >> INIT_2A = INIT, >> INIT_2B = INIT, >> INIT_2C = INIT, >> INIT_2D = INIT, >> INIT_2E = INIT, >> INIT_2F = INIT, >> INIT_30 = INIT, >> INIT_31 = INIT, >> INIT_32 = INIT, >> INIT_33 = INIT, >> INIT_34 = INIT, >> INIT_35 = INIT, >> INIT_36 = INIT, >> INIT_37 = INIT, >> INIT_38 = INIT, >> INIT_39 = INIT, >> INIT_3A = INIT, >> INIT_3B = INIT, >> INIT_3C = INIT, >> INIT_3D = INIT, >> INIT_3E = INIT, >> INIT_3F = INIT) >> port map ( >> DIA = "00000000", >> DIPA = "0", >> DIB = "00000000", >> DIPB = "0", >> ENA = '1', >> ENB = '1', >> WEA = '0', >> WEB = '0', >> SSRA = '0', >> SSRB = '0', >> CLKA = clk_p, >> CLKB = clk, >> ADDRA = "00000000000", >> ADDRB = "00000000000", >> DOA = open, >> DOPA = open, >> DOB = open, >> DOPB = open); >> >> -- CLK process >> process >> begin >> clk_p <= '0'; >> clk_n <= '1'; >> loop >> wait for (10 ns); >> clk_p <= not clk_p; >> clk_n <= not clk_n; >> end loop; >> end process; >> >> MAIN: process >> begin -- process MAIN >> >> rst <= '1'; >> wait for 10 ns; >> rst <= '0'; >> >> wait; >> >> end process MAIN; >> end architecture sim; >> >>-- >>Patrik Eriksson | patrik.eriksson@netinsight.net >>Net Insight AB | phone: +46 8 685 04 89 >>Västberga Allé 9 | fax: +46 8 685 04 20 >>SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > > -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 46141
Hi, could somebody explain me if should I worry about deasserting GSR signal or not. In my understanding initial values (after power-up) of FF are defined by the configuration stream. When configuration phase is finished DONE goes high (floating), GSR and GTS are released. Since GSR is released all FFs start to be clocked. Is there any concern that releasing GSR happens asynchronously to CLK (main system clock). Can it cause any problem, for instance if at the D input of FF is logical '1', but GSR forces the FF to '0' state. Should I protect the design against problems after power-up? I am actually working with SpartanXL, but I think that the issue can be with other families too. thank you RobertArticle: 46142
Hi all, I have designed a simple frequency divider, existing mainly of 15 flip-flops. Ambit BuildGates is my synthesis tool. I am getting the following results when my target technology is a 300k gate-array technology from LSI: Worst path delay: 1.73 ns Cell Area: 279 And these are the results when using a standard-cell 0.35 um technology: Worst path delay: 1.92 ns Cell Area: 13,304 Why is there such a huge discrepancy between the cell areas? I expected the standard-cell to be faster. My explanation for the faster gate-array implementation: it takes only the gate delay into account not any wiring. Am I right? Does the worst path delay only exist of the combinational part? (the tool only highlights the combinational logic) Cheers, HenningArticle: 46143
Not completely sure what you are asking but it sounds like you are asking how to control your INOUT port between reading/writing in which case a tri-state network with whatever enables you want should work...Article: 46144
Hi Tom For digital filter design on FPGA...try ONEoverT from www.tyder.com. The RTL VHDL module is supplied free until the end of September. The whole package works out quite cheap....about $500 although this maybe more than what you want to spend. There is a case study pdf document downloadable from their website, taking you through the implementation of FIR and IIR filters on FPGA. They also do other higher level dsp functions for FPGA/Asic. Good luck Many Tom Loftus wrote: > I am an experienced ASIC designer with a little bit of DSP coursework > and I would like to learn more about implementing DSP algorithms in hardware. > I think that implementing various hardware architectures in FPGA's > would be a useful learning exercise which could be done fairly quickly > and cheaply using my available PC resources at home and work. > > I have access to Verilog/VHDL simulation tools and am familiar with the available > Web baseline FPGA tools. The pieces I think I am missing are the visualization > and verification portion of the development: > > Visualization - I want to be able to take input and output data streams in > both the time and frequency domain and graphically display them. > > Verification - I need a baseline with which I can compare my hardware > implementation to verify it is working correctly. > > I know something like Matlab or Mathcad would probably do what I am looking > for, but they seem rather expensive. > > Can anyone offer other ideas? Does what I am planning sound reasonable? > > TomArticle: 46145
GSR release does have to be considered an asynchronous event. This is true even
if you have it driven from outside and release it there synchronous to the clock
if you clock is reasonably fast because the propagation time on that net is
quite slow. That said, on most designs you don't have a bunch of things all
happening on release of GSR. On the critical stuff use a synchronous reset that
is delayed off the GSR and then let that kick everything off. If you do your
design right, most of it shuld be sitting idle after GSR is released until it
recieves some other internal or external stimulus.
RobertS wrote:
> Hi,
>
> could somebody explain me if should I worry about deasserting GSR signal or
> not. In my understanding initial values (after power-up) of FF are defined
> by the configuration stream. When configuration phase is finished DONE goes
> high (floating), GSR and GTS are released. Since GSR is released all FFs
> start to be clocked. Is there any concern that releasing GSR happens
> asynchronously to CLK (main system clock). Can it cause any problem, for
> instance if at the D input of FF is logical '1', but GSR forces the FF to
> '0' state. Should I protect the design against problems after power-up?
>
> I am actually working with SpartanXL, but I think that the issue can be with
> other families too.
>
> thank you
>
> Robert
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46146Hi there, I used to use this trick : 1. Run implememtation to pass the "translate" stage to obtain the NGD file, besure your circuit is not sourceless or loadless 2. Run "check point gate simulation", you will see all init values.Article: 46147
Hi Tom,
I have been trying something similar and have found using a
numerically competent and flexible programming language to be a real help
for DSP-FPGA work. I guess it's a question of if you want to spend time
or money...
: Visualization - I want to be able to take input and output data streams in
: both the time and frequency domain and graphically display them.
The main question is do you want to do the above in real time, or are you
planning to capture and then analise the data?
If it's the later, you might find the Python programming language to be
usefull:
1) It's Free
2) Interactive console (just like the BASICs of old...)
3) Lots of bolt on modules for array handling, data processing and
visualisation etc. etc. There are some very powerfull visualisation
modules out there.
5) Can use existing C, Fortran etc code.
5) Cross platform.
: Verification - I need a baseline with which I can compare my hardware
: implementation to verify it is working correctly.
I use Python to prototype the mathmatical behaviour of a system,
coding the behaviour of individual blocks in Python, and linking them
together. Once I get the time to try them in hardware, the captured data
can be examined in the same environment. You would however need to
produce models for the various blocks you would use. For compicated
blocks that may or may not require some effort (depending what you can
find in existing libraries etc.) but will teach you more about how the
blocks work.
I have an in progress gui-schematic front end that I am writing in Python
that lets data processing blocks be connected and simulated graphically,
showing dataflow through a design. It's in its early days at the moment,
but is proving very usefull, and a shade cheaper than other options...
I am also hoping to spend some time on a simulator<>fpga link, allowing
individual blocks to be droped into an FPGA and channel simulation data
into/out of the blocks, allowing individual bits to be tested in hardware.
Might prove faster than VHDL sims in the end...
: I know something like Matlab or Mathcad would probably do what I am looking
: for, but they seem rather expensive.
Hope the above is of some intrest.
Chris Saunter
some links:
Python www.python.org
SciPy www.scipy.org <-- some visualisation, maths etc.
Article: 46148Hello!! I have a problem with the JAM STAPL Player Version 2.2. But first i summarize what i have done so far: I have ported the JAM STAPL Player to LINUX. That was not a big problem. Then i have added the ByteBlaster Support for LINUX, because after porting the player supported only the BitBlaster. And now i have the following problem: I have to program a JTAG-Chain with 3 devices. First and second device in the JTAG-Chain are two EPC2-devices and the third device is a EP20k300E. My JAM-File (im_V40.jam) only have to program the two EPC2-Devices, because the EP20k300E is forced with an extra Signal to reconfigure after the JAM-Player has finished his Job. Now when i start the JAM STAPL Player with the command line jam_player.out -v -p378 -aPROGRAM im_V40.jam the JAM Player first ERASE the devices then PROGRAM them and then VERIFY the content of the devices. In most cases the JAM Player will terminate normally with exit_code=0 "Success". BUT sometimes the JAM Player terminates after programming within the VERIFY-section with exit_code=11 "Device verify failure". Then i have started the JAM-Player with the command line jam_player.out -v -p378 -aPROGRAM -dDO_VERIFY=0 im_V40.jam to trace the error. With this line the JAM Player first ERASE the devices and the PROGRAM it. This procedure works all the time (Player exits with exit_code=0 "Success"). And then i verified the devices with the command line jam_player.out -v -p378 -aVERIFY im_V40.jam That results in a funny effect, because sometimes the JAM Player exits with exit_code=0"Success" (that means there was no error in programming the device) BUT sometimes the JAM Player exits with exit_code=11"Device verify failure". and now i'm confused because i don't have programmed the devices new in the meanwhile. When i program the devices with the MAX2PLUS Programmer under Windows with the same JAM-File it works all the time. So i think there is a bug in the JAM STAPL Player. Do you understand my problem? Have you an Idea what's going wrong with the player, or where i can look to trace the error? Because i need the JAM Player under LINUX and it is nessesary that it works ALL the time and not every now and then. I hope you can help me with this problem... have a nice day yours Schachinger Martin schachinger@decomsys.com VIENNA - AUSTRIAArticle: 46149
> > This is MY take on this, and if you have any concerns, I suggest you contact > > Phillips about this. > > > > I believe when you buy a chip that has an "interface" that you have to > > interface to, you implicitly have the right to interface to it, period, and > > no additional license is needed. Again, simply MY opinion. > > So you would say that if I buy a chipset from Via that implements the > Intel P4 front side bus interface, and a Foobarco J37 processor that > implements the same bus, that I can build them into my product (with no > Intel P4), and implicitly receive a license from Via and Foobarco to use > the Intel P4 front side bus? Eric, I am referring to I2C here, as I broached this subject some years ago when designing to interface to I2C peripherals. I do not know the details of, or even if there are any, patents dealing with the Intel P4 front side bus, so I can not say. I would say check with Via and Foobarco ;-) Austin
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