Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
>Another approach is to add multi-threading capabilities but I think that >multi-processing is better for FPGA than multi-threading. Why? If I understand what multi-threading means, the idea is to interleave alternate cycles of two execution streams in order to reduce the losses due to stalls. It looks like it "just" requires an extra address bit (odd/even cycle) to the register file and the same bit selects between pairs of special registers like the PC. Are you telling me that the ALU and instruction decoding is small enough so that I might just as well build two copies of the whole CPU? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48326
That's the one. NT lets you change the environment variables without rebooting,
in which case you go into the system folder in the control panel and change it.
Not sure if win98 does the same or not.
Noddy wrote:
> Just to double check, you are talking about the SET XILINX = {path} in my
> config.sys file? (I am running Windows 98 in case this makes any difference)
>
> adrian
>
> > You can do separate installs for 3.3 and 4.2 on the same machine. In
> order to
> > switch back and forth between them, you need to modify the XILINX
> environment
> > variable to point to the tools directory you are currently using. Other
> than
> > that, there is nothing special that needs to be done. IIRC, there was a
> new
> > xilinx registration number to enter when first installing 4.x, but that is
> a
> > one-time thing.
> >
> > I have both 3.3 and 4.2 installed on the same drive, different
> sub-directories
> > on my NT machine. To switch, I change just the directory name in the
> XILINX
> > environment variable, then I'm good to go. Can't use both at the same
> time
> > unless you are strictly command line, in which case you can use the set
> command
> > to do the enviroment locally.
> >
> > Noddy wrote:
> >
> > > Hi,
> > >
> > > I am presently designing for a Spartan II using Foundation 3.3 software.
> We
> > > have upgrades (still in their boxes) to Foundation 4.2 aswell as ISE
> 4.2. We
> > > need to upgrade the software sometime as I am going to be redesigning
> and
> > > modifying for a Spartan IIE.
> > >
> > > My question is the following: I was under the impression the ISE was
> really
> > > only useful if I was going to design for Virtex. Under this
> understanding,
> > > will probably want to install the software for Foundation 4.2. However,
> I
> > > still want to use Foundation 3.3 as I am still working on the design,
> and am
> > > worried about the design having problems in 4.2. So what I want to do is
> put
> > > Foundation 4.2 onto a separate hard drive, and plug into the same
> system.
> > > Will I have any registry issues? Is it possible to run two versions of
> the
> > > Xilinx Foundation software on the same machine? Do have to do the entire
> > > Xilinx licensing thing again when I install 4.2? Finally, should I
> rather be
> > > install ISE instead?
> > >
> > > Thanks
> > >
> > > Adrian
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48327>The 2V40, 2V80, and 2V250 are available in the CS144 package, or the fg256 >package. > >That is as small (and inexpensive) as it gets. Both packages do quite well with >regards to SI and EMC/EMI as they were designed from the bottom up to be good >performers. The real problem is how to build small quantities of boards using modern FPGAs, but do it inexpensively. There are several companies that will build 2 or 4 layer PCBs if you send them gerbers over the net. I haven't done it, but friends have and they were happy. Prices are such that I might be willing to do it for "just" a hobby project. The next step is to get things like BGAs mounted inexpensively. Are they any companies that specialize in this sort of thing? I haven't checked the details. The inexpensive PCBs do not support tiny lines/spacings. Are they good enough for FG256? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48328
>>Did you connect all 32 devices to the same clock? -Stan > >Yes, no reason why not if the signal edges are well controlled. This seems like an interesting SI exercise. How do you put 32 chips on a single net and have the signal clean enough to use as a clock? Is it something as simple as use a really low impeadance so the capacitave loading doesn't change things much? (and terminate the far end...) Driving from the middle cuts the problem in half. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48329
Hi,
Which synthesis tool do you use?
Some, like FPGA Express or XST, have the bad habit to change the names of
the signals.
Normally this 2 notations should work :
NET clk PERIOD = 50ns ;
NET clkgen1/clko PERIOD = 50ns ;
But check the names your tools gave to it.
For example FPGA Express love "N_" expression : it will rename your "CLK" in
"N_CLK".
Use FPGA Editor to check the names: follow your signal through the the
design and look at your instances like CLKBUF.
Fortunatetly, it does not change the names of the instances.
Arnaud
Signature MVD-------------------------------------------------------- Arnaud
DION Tel : +33 (0) 5 62 13 52 32 Fax : +33 (0) 5 61 06 72 60 E-mail :
arnaud.dion@mvd-fpga.com
www.mvd-fpga.com --------------------------------------------------------
"David R Brooks" <daveb@iinet.net.au> a écrit dans le message de news:
v8liqu8b8ttg1u9911b9brjm06etk210iq@4ax.com...
> Q: What is the proper notation to use in a Xilinx
> *.UCF file, to reference embedded nets?
>
> In the example below, the external signal CLKIN
> can have speed constraints set in the UCF thus:
> NET clkin PERIOD = 50ns ;
>
> How do I write such a constraint for the net CLK,
> which doesn't exit the design, existing only in
> the block TOP and those below?
> I have tried constructs such as:
> NET clkgen1/clko PERIOD = 50ns ;
> and
> NET top/clk PERIOD = 50ns ;
>
> Both of these being rejected by the tools.
>
>
> library ieee ;
> use ieee.std_logic_1164.all;
>
> entity TOP is port ( -- Dummy entity: no outputs
> CLKIN : in std_logic );
> end TOP ;
>
> library ieee ;
> use ieee.std_logic_1164.all;
>
> architecture struct of TOP is
> signal CLK : std_logic; -- The one I want to constrain
>
> component CLKGEN port ( -- Source of CLK
> CLKI : in std_logic;
> CLKO : out std_logic );
> end component;
>
> component DM port ( -- Dummy consumer of CLK
> CLK : in std_logic );
> end component;
>
> begin
> DM1 : DM port map (
> CLK => CLK );
>
> CLKGEN1 : CLKGEN port map (
> CLKI => CLKIN,
> CLKO => CLK );
> end struct;
>
> library ieee ;
> use ieee.std_logic_1164.all;
>
> entity CLKGEN is port(
> CLKI : in std_logic ;
> CLKO : out std_logic );
> end CLKGEN;
>
> library unisim;
> use unisim.all;
>
> architecture DUMMY of CLKGEN is
> component BUFG port (
> I : in std_logic;
> O : out std_logic );
> end component;
>
> begin
> CLKBUF : BUFG port map ( -- Global clock driver
> I => CLKI,
> O => CLKO );
> end DUMMY;
>
> -- TIA,
>
Article: 48330"Theron Hicks" <hicksthe@egr.msu.edu> writes: > The Virtex2 would be an awesome device for me if it met three criteria. > > 1. Available in a more traditional leaded package. > 2. More clock buffers readily accessable. Each DCM should have at least > 4 clock buffers available. (5 or 6 buffers could be shared between two DCMs > acceptably) > 3. Parts readily available for purchase in small quantities for > prototyping. > So... is there a market for someone to supply V-II devices mounted on a "bodge-board" with a high-density connector? (Can't fix number 2) though :-) Anyone else think this might be useful? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 48331
Falser Klaus wrote: > In article <3DAB51B2.607AC0B6@andraka.com>, ray@andraka.com says... > > You can do separate installs for 3.3 and 4.2 on the same machine. In order to > > switch back and forth between them, you need to modify the XILINX environment > > variable to point to the tools directory you are currently using. Other than > > that, there is nothing special that needs to be done. IIRC, there was a new > > xilinx registration number to enter when first installing 4.x, but that is a > > one-time thing. > > A fast way to switch between different installations is to use symbolic links. > You need to have W2K (or XP ??) and your disk must be formatted NTFS. > > Install one version in, say, c:\Xilinx33 and the other in c:\Xilinx42 > > Using the "Junction" utility from Sysinternals create a directory c:\Xilinx > pointing to either c:\Xilinx33 or c:\Xilinx42 > Win2K has finally gained symbolic links - sort of - amazing !! It looks, though, that this only applies to directories and not individual files - is this correct ?Article: 48332
Neil Franklin <neil@franklin.ch.remove> wrote: > nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > >> In article <6un0pgioiv.fsf@chonsp.franklin.ch>, >> Neil Franklin <neil@franklin.ch.remove> wrote: >> >> How many users (outside a small cadre of open source true-believers) >> >> really do? >> > >> >As the "small cadre" is already in the 100'000s, those outside are not >> >really that important. >> >> Is the cadre of open source true blieveres that high? > > Perhaps only 1-2 times 100'000, but it is astonishingly large. There > are a lot of people who have got fed up with closed source software. > Loads of then to recruit from. Distiguish Open Source Software and Open Source Hardware. There are infact bazillions of followers of the first kind, but this is usually just to get free beer. The group of OSH fans is small, very small, which is no surprise IMHO. Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)Article: 48333
Hi community, I have tried already several times to compare realistic Clock Speeds (MHz) for the whole Xilinx Families depending on the Technology. I found out that XC4000XL is 0.35µm; XC4000XV is 0.25µm; Virtex is 0.22µm; VirtexE is 0.18µm; Virtex2 is 0.15µm and Virtex2Pro is 0.13µm. What I need are realistic mappings and the resulting Clock Speed for all the families. I mapped a 32Bit adder to all the families and the result was a more or less linear increase of the frequency. XC4000XL=41.137MHz XC4000XV=66.742MHz Virtex=101.750MHz VirtexE=139.567MHz Virtex2=187.371MHz Virtex2Pro 3.211MHz 1. Is that possible??????????? 2. Is there a Benchmark? 3. Are there similar results in a chart anywhere in the web? 4. What are your experiences? 5. If it is correct, that the speed does not increase that much, what is the reason for that (in comparison to CPUs, which seems highly exponential)? Please help me, it is a part of my PHd!!!!!!! Heiko PS: Have a look on my www.RAPTOR2000.de page -- --------------------------------------------------------------- Dipl. Ing. H. Kalte | HEINZ NIXDORF INSTITUTE | Office: F1.213 System and Circuit Technology | Fon: +49 (0)5251 60-6459 Fürstenallee 11 | Fax: +49 (0)5251 60-6351 33102 Paderborn, Germany | --------------------------------------------------------------- mailto:kalte@hni.uni-paderborn.de http://wwwhni.uni-paderborn.de/sct/ --------------------------------------------------------------- Home of the RAPTOR Rapid Prototyping Systems http://www.RAPTOR2000.de/ ---------------------------------------------------------------Article: 48334
"Kolja Sulimma" <kolja@bnl.gov> wrote in message news:25c81abf.0210151403.1e436c4a@posting.google.com... > Did you address the problems that are described in this thread: > > http://groups.google.de/groups?hl=de&lr=&ie=UTF-8&selm=25c81abf.0210081329.e d45bc4%40posting.google.com > > The are also a couple of older threads on this topic. Thanks, Kolja. I remember that thread, now you've mentioned it. I just copied the Xilinx schematic, I'll bear it in mind if there are problems. The chips can be socketed, so different ones could be tried, and it would be easy to modify the PCB. I've never had any problems with the standard Xilinx Cable III, with my FPGA and CPLD hardware. Perhaps I should open it up, to check if it matches the schematic. Interestingly, the Altera ByteBlaster uses a 74HC244 buffer, does not use any capacitors or diodes and has 2K2 pull-ups on all inputs. I also made my own version of it as Altera charges a lot more for their adaptor than Xilinx. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48335
Prashant wrote: > > Hi, > > I have a design which requires about 100 Million mulitplies and about > 200 Million add/subtracts per second. I'm implementing my design in an > FPGA. Does anyone have an idea how compute intensive is this design, > if implemented in a DSP. I'm not sure how these operations would > compare against MFLOPS or MIPS that DSP data sheets refer to. I would > think my operations would be about 300 MIPS (mulitply + add). So a DSP > claiming 300 MIPs or more of performance should be able to deal with > this design. Am I right ? > DSPs can do several multiply and accumulates (macs) in a single cycle. For example, the company I work at will sell you a DSP that can do 16 macs each cycle, which is 4 billion macs a second @ 250 MHz. I think that would be more than adequate performance for your task. Cheers, JonB > Thanks, > PrashantArticle: 48336
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:uhefmesun.fsf@trw.com... > "Theron Hicks" <hicksthe@egr.msu.edu> writes: > > > The Virtex2 would be an awesome device for me if it met three criteria. > > > > 1. Available in a more traditional leaded package. > > 2. More clock buffers readily accessable. Each DCM should have at least > > 4 clock buffers available. (5 or 6 buffers could be shared between two DCMs > > acceptably) > > 3. Parts readily available for purchase in small quantities for > > prototyping. > > > > So... is there a market for someone to supply V-II devices mounted on > a "bodge-board" with a high-density connector? (Can't fix number 2) > though :-) > > Anyone else think this might be useful? > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conekt I would think that, even in a simple I/O design like I had proposed, the EMI/EMC and signal integrity problems would be horrid on that type of design. Some of the issues could be resolved with a place for an on board clock connector (SMA, SMB, MCX etc.). Perhaps two would be required to allow for diferential clock schemes.Article: 48337
Hi, I am working on a board that will have 3x XC2V6000 devices on it and have been investiagting configuration solutions. One of the requirements for the system is that during debug, we want to update the Block RAM contents. The design will not change only the BRAM contents. We have investiagated the DATA2BRAM utility from Xilinx and it appears to meet our requirements. It basically allows you to directly update the bitstream with new contents for the Block RAMs. No need to run par. No guide files etc.. It also seems very quick i.e. some tests have shown it takes about 3 seconds to update a xc2v6000 bitstream. The problems we are having are with the iMPACT software and the SystemACE MPM solutions. iMPACT software for SystemACE MPM ---------------------------------- The SystemACE MPM requires a specific type of programming file called .mpm. iMPACT can create it. However we have had many issues 1. it says that 3xc2v6000 bitstreams will not fit into the 64Mbit Flash. I estimate the the bitstreams require approx 65,000,000 bits. This should fit into the 64Mbit (67,108,864) device. 2. the tool is very slow! it takes about 6 minutes to read in the 3 bitstreams and create the MPM file. I regard this as slow, since the PROMGEN program can create 17 PROM files in 2 minutes. (each PROM is an 18v04). 3. i have investigated using the compression mode. The time to create a compressed MPM file is 16 minutes.!!!! I tried unix gzip for comparisson. It takes 2 seconds to compress the original .mpm file. Why is this so incredibly slow? SystemACE MPM ------------- We intended to use the Parallel Cable IV to program the SystemACE. The literature states that the Parallel Cable IV is 8x faster that Parallel Cable III. Our experience has shown that using Parallel Cable III and the Parallel Port you can acheive about 100-200 kbits/ second download rate. Based on this figure, it would take about 7-8 minutes to download the 64Mbits to the SystemAce. Using the Parallel Cable IV we had hopped to slash this to 1 minute or so. However after talking to Xilinx hotline, it appears that the SystemACE MPM chip is designed in such a way that it cannot handle the Parallel Cable IV rates. It is stuck at Parallel Cable III rates. This is incredibly annoying and disappinting. We had assumed that using the DATA2BRAM utility, togehter with SystemACE MPM, we would be able to update the design on the board in a few minutes. With all of the above issues, it turns out to be of the order of 15-25 minutes. PS we are using 5.1i SP1. We are now looking at putting 17 serial PROMs on the board. The PROMs should support the Parallel Cable IV download rate. The generation of the PROM file is a lot quicker than genraating the .mpm fileArticle: 48338
Hi, Sort of. The complete decoding and the ALU is around 10-13% of the design. The actual instruction decoding is less than 5%. Make it multithreading as I understand is to have more than 1 instructions streams in the pipeline. What is the benefit unless you double the pipeline and have two data pipelines? Almost nothing So with two threads in MicroBlaze, to double the pipeline is to double the size of MicroBlaze. You also have to double the instruction fetching data throughput in order to get the two streams busy. That would put a big burden on the bus infrastructure and external memory interface which suddenly has to double it's performance. The doubling of the pipeline and added control handling WILL also lower the maximum clock frequency of MicroBlaze. Compare this with two MicroBlaze which can have it's separate instruction fetching and both running at the maximum clock frequency. I would say that multiprocessing which is easier to do and with more performance a better choice. Say you suddenly would like to have 5 threads instead of 2. That is a major change of the multithreading MicroBlaze and almost impossible to get the instruction fetching to keep up. With multiprocessing, just add another 3 MicroBlazes and you're done. BUT there is always a catch and that is how you write programs for these systems. Göran Hal Murray wrote: > >Another approach is to add multi-threading capabilities but I think that > >multi-processing is better for FPGA than multi-threading. > > Why? > > If I understand what multi-threading means, the idea is to interleave > alternate cycles of two execution streams in order to reduce the > losses due to stalls. > > It looks like it "just" requires an extra address bit (odd/even cycle) > to the register file and the same bit selects between pairs of special > registers like the PC. > > Are you telling me that the ALU and instruction decoding is small enough > so that I might just as well build two copies of the whole CPU? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 48339
Hi,
I would like to know if I need any terminator technology for Altera`s
APEX 20KE I/O pins. I have read a lot about this feature for Stratix
devices, but nothing for APEX devices. I think that the terminator
technology will depend on the standard I/O used. For more information
I add that I'm using LVTTL for all the pins. HELP, please!
Thanks a lot,
Regards,
Itsaso.
Article: 48340Austin Lesea wrote: > > Theron, > > The 2V40, 2V80, and 2V250 are available in the CS144 package, or the fg256 > package. > > That is as small (and inexpensive) as it gets. Both packages do quite well with > regards to SI and EMC/EMI as they were designed from the bottom up to be good > performers. > > The reason why we abandoned the use of pq/hq packages (in planning Virtex II) is > that they provide no good ground plane, and even with the low IO count in these > smaller die, the ground bounce due to SSOs can be terrible (if the return path > ground inductance is as bad as it gets in the pq/hq lead frame packages). > > One could cut the SSO budget by half, and then use a pq/hq package, but it would > be for a very small market segment. There is a market vacuum for large scale fpgas in packages like pqfp144-240, designed for low power, 5V tolerance, and because they're low power, they should have slower edge rates. The edges should be deliberately slower or adjustable to avoid ground-bounce. You can do a *lot* of dsp with an fpga running at less than 50MHz. If there was such an fpga like this that could only do 50MHz, i'd still buy them. Last i looked, the atmel at40k looked interesting. Ah, but the tools weren't...easy to get or use. Open source?Article: 48341
"Itsaso Zuazua" <izuazua@ikerlan.es> schrieb im Newsbeitrag news:709383e9.0210160719.72bc0dfb@posting.google.com... > Hi, > > I would like to know if I need any terminator technology for Altera`s > APEX 20KE I/O pins. I have read a lot about this feature for Stratix > devices, but nothing for APEX devices. I think that the terminator > technology will depend on the standard I/O used. For more information > I add that I'm using LVTTL for all the pins. HELP, please! It all depends on how fast you signals are switching and how long the connections to the other ICs are. Fast switching doesnt always mean high frequency, fast switching means rise/fall time of you signals. In Xilinx devices, you can adjust the driver stength and speed to different levels (2,4,6..24 mA, Slow/fast). I dont know if this is possible in APEX20K.Then the lenght of the traces comes into play. If the lenght of the trace is greater than 1/6 of the propagation time of a rising/falling edge (whichever is faster), than you better go for termination. An example. Propagation speed on a trace is ~20cm/ns. So if you rise/fall times are 2ns (=40cm), so every trace longer than 40/6 = ~6.5 cm better gets some termination. -- MfG FalkArticle: 48342
In article <3DAD80F2.DC5AD4C4@Xilinx.com>, Goran Bilski <Goran.Bilski@Xilinx.com> wrote: >Hi, > >Sort of. > >The complete decoding and the ALU is around 10-13% of the design. >The actual instruction decoding is less than 5%. > >Make it multithreading as I understand is to have more than 1 instructions >streams in the pipeline. >What is the benefit unless you double the pipeline and have two data pipelines? >Almost nothing Uhh, you don't double the pipelines, you take the single pipeline, double up the registers IN them, and then move the regsters to rebalance all the pipeline stages, as now you have 2x the registers through any fedback loop, allowing you to up the clock frequncy alot. If you do this to every register in the core (and tweak the RF), a multithreaded design just sort of "dros out" automatically. You can even write a tool to do that automatically. What happens in the end is is you take adantage of the two threads to up the clock substantially. Each individual thread is now a little slower, but the throughput for the 2 threads is now substantiall higher. You use more pipelining and more power, and you may or may not end up thrashing the caches, but itdoes work. I can send you a paper submission and a thesis chapter draft on the subject if you want. >So with two threads in MicroBlaze, to double the pipeline is to >double the size of MicroBlaze. You also have to double the >instruction fetching data throughput in order to get the two streams >busy. That would put a big burden on the bus infrastructure and >external memory interface which suddenly has to double it's >performance. The doubling of the pipeline and added control handling >WILL also lower the maximum clock frequency of MicroBlaze. You don't need to double the exteral memory interface if you share the cache, this is especially true on workloads where the threads are related. The external memory interfare is now 2x the CLOCK, but you could slow it down from there and arbitrate beween the two streams of execution. You also probably want to make the feeding of interrupts a little different, so you can designate one thread as receiving the interrupts. >Say you suddenly would like to have 5 threads instead of 2. That is a major >change of the multithreading MicroBlaze and almost impossible to get the >instruction fetching to keep up. With multiprocessing, just add another 3 >MicroBlazes and you're done. What you do is you have a 1 thread and a 2 thread version (going beyond 2 threads seems to be less effective, maby 3 depending on the architecture). From the exterior, however, they still look normal. You can still tile that like any other core to create a multiprocessor machine. >BUT there is always a catch and that is how you write programs for these >systems. "one thread for I/O, one thread for processing" does come up in some cases. >Göran > >Hal Murray wrote: > >> >Another approach is to add multi-threading capabilities but I think that >> >multi-processing is better for FPGA than multi-threading. >> >> Why? >> >> If I understand what multi-threading means, the idea is to interleave >> alternate cycles of two execution streams in order to reduce the >> losses due to stalls. >> >> It looks like it "just" requires an extra address bit (odd/even cycle) >> to the register file and the same bit selects between pairs of special >> registers like the PC. >> >> Are you telling me that the ALU and instruction decoding is small enough >> so that I might just as well build two copies of the whole CPU? >> >> -- >> The suespammers.org mail server is located in California. So are all my >> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited >> commercial e-mail to my suespammers.org address or any of my other addresses. >> These are my opinions, not necessarily my employer's. I hate spam. > -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48343
On Wed, 16 Oct 2002 04:51:06 -0000, Hal Murray <hmurray@suespammers.org> wrote:
>
>I haven't checked the details. The inexpensive PCBs do not support
>tiny lines/spacings. Are they good enough for FG256?
I, too, have been scared off of BGA work because of assembly "issues".
The Virtex2 is attractive enough, I have started preparing myself for
that eventuality. The circuit board doesn't look like a problem for me.
Context: 6-mil line/6-mil space 4-layer board is the bare minimum for
working with a PQ208, and I have ended up going 6 or 8 layers to get
a little more routing and beefy grounding.
Almost all of the I/O pins in the Virtex2 FG256 are in the outer four
rows. To pull these signals out with 5-mil line/5-mil space layout,
you only need two routing layers. To properly get at the last four
or eight signal pads, you should add a third routing layer. Add one
or two ground planes, a V_core and/or a V_IO layer, and I would consider
six layers as the minimum, although some people would probably squeak
by successfully with four. If the design engineer and layout engineer
are not the same person, chances are designs would end up with eight
layers or too much noise, or both.
More detail on the PCB technology specs, that I hear is "easy" for a
modern fab shop: .062" thick boards, .012" drill size, .022" via size
(.005" ring). Finshed hole size about .008". You can just fit one
trace between vias spaced at 1mm pitch: .022" via + .005" space + .005"
line + .005" line = .037", compared to .03937" pitch. The pad layer
is a little easier, but not so open as to let you run double traces
between pads. I think the pad size is supposed to be .016" diameter.
- Larry
Article: 48344On Tue, 15 Oct 2002 14:02:26 -0700, Theron Hicks wrote: > Uwe, > I can route the package, I just can't assemble it. Changing the > number > of pins won't solve the problem. Furthermore, I don't buy that the EMC > problems are insurmountable. I regularly build ECL circuits at 1GHz in > standard SOIC packages. In fact, try to buy 100K ECL in anthing but > leaded packages be they gullwing or J-lead. The only available packages > are leaded, not BGA. For example the MC100EP32 is rated for 4 Gigahertz > toggle (divide by 2). It is only available in an 8 pin SOIC or 8 pin > TSSOP package. Check the http://www.onsemi.com web site Only the > reduced swing ECL (RSECL) parts go to BGA. Those are rated for 12 > GIGAHERTZ toggle. > Unless the problems are simply caused by the number of I/O pins then > I > am skeptical of the EMC issue. > ' Actually BGAs are not a lot harder to prototype with than PQ208s. I do 516 pin ones with nothing more than my trusty $59.00 Granger heat gun. The trick is to locate the BGA properly on the PCB. (and to mount the BGA first, before any other parts) I do the location with a frame made of 4 pieces of scrap pcb material surrounding the BGA package. These have about a business card worth of clearance on all sides so that when the solder balls melt, the surface tension can pull the BGA down and into perfect alignnment with the pads. Then I put a _LOT_ of rosin based flux on the pad area and proceed to heat the pcb from the back with the hot air gun. When the solder balls melt, you can see the BGA package sink down about 1/4 mm. After the card has cooled i wast out the rosin with IPA and then inspect the soldering. I have had 2 types of soldering failures with this system, both detectable by simple visual inspection: 1. Not enough heat/duration - this is apparent by looking at whether the balls are all uniformly flattened around the periphery. This is easily fixed by re-fluxing/reheating 2. misalignment - if the BGA was not aligned well with the pads, you will get solder balls that merge. This is easily detected by sighting along the edge of the BGA and making sure that you can see all the way through all of the gaps between balls in both directions The other thing that helps if having some spare BGAs and PCBs to practice with... > Just my opinionated opinion, > Theron Hicks > > "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message > news:aohn4s$olb$1@news.tu-darmstadt.de... >> emanuel stiebler <emu@ecubics.com> wrote: >> : Is there any chance we could see something like this ? I would love >> : to use the speed of the VirtexII on a cheaper PCB. >> >> : Am I the only one who is dreaming about this packaging ? >> >> The question came up before. One answer was, that EMC problems nearly >> prohibit use of leaded packages for devices fast and powerfull like the >> virtex. One proposal was to put out a BGA package with 1.27 mm pitch. 4 >> Layer PCB prototypes with 0.3mm drill, 0.15mm lines/spaces designrules >> are afordable and a 4 row BGA can be routed with these rules. >> >> Bye >> -- >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 48345
Hi, "Nicholas C. Weaver" wrote: > In article <3DAD80F2.DC5AD4C4@Xilinx.com>, > Goran Bilski <Goran.Bilski@Xilinx.com> wrote: > >Hi, > > > >Sort of. > > > >The complete decoding and the ALU is around 10-13% of the design. > >The actual instruction decoding is less than 5%. > > > >Make it multithreading as I understand is to have more than 1 instructions > >streams in the pipeline. > >What is the benefit unless you double the pipeline and have two data pipelines? > >Almost nothing > > Uhh, you don't double the pipelines, you take the single pipeline, > double up the registers IN them, and then move the regsters to > rebalance all the pipeline stages, as now you have 2x the registers > through any fedback loop, allowing you to up the clock frequncy alot. > > If you do this to every register in the core (and tweak the RF), a > multithreaded design just sort of "dros out" automatically. > > You can even write a tool to do that automatically. > > What happens in the end is is you take adantage of the two threads to > up the clock substantially. Each individual thread is now a little > slower, but the throughput for the 2 threads is now substantiall > higher. You use more pipelining and more power, and you may or may > not end up thrashing the caches, but itdoes work. > > I can send you a paper submission and a thesis chapter draft on the > subject if you want. > Please do. If you double all the registers in the data pipeline, hasn't you doubled the pipeline? Or is all functionality between the pipestages shared? > > >So with two threads in MicroBlaze, to double the pipeline is to > >double the size of MicroBlaze. You also have to double the > >instruction fetching data throughput in order to get the two streams > >busy. That would put a big burden on the bus infrastructure and > >external memory interface which suddenly has to double it's > >performance. The doubling of the pipeline and added control handling > >WILL also lower the maximum clock frequency of MicroBlaze. > > You don't need to double the exteral memory interface if you share the > cache, this is especially true on workloads where the threads are > related. The external memory interfare is now 2x the CLOCK, but you > could slow it down from there and arbitrate beween the two streams of > execution. > > You also probably want to make the feeding of interrupts a little > different, so you can designate one thread as receiving the > interrupts. > > >Say you suddenly would like to have 5 threads instead of 2. That is a major > >change of the multithreading MicroBlaze and almost impossible to get the > >instruction fetching to keep up. With multiprocessing, just add another 3 > >MicroBlazes and you're done. > > What you do is you have a 1 thread and a 2 thread version (going > beyond 2 threads seems to be less effective, maby 3 depending on the > architecture). From the exterior, however, they still look normal. > You can still tile that like any other core to create a multiprocessor > machine. > > >BUT there is always a catch and that is how you write programs for these > >systems. > > "one thread for I/O, one thread for processing" does come up in some > cases. > > >Göran > > > >Hal Murray wrote: > > > >> >Another approach is to add multi-threading capabilities but I think that > >> >multi-processing is better for FPGA than multi-threading. > >> > >> Why? > >> > >> If I understand what multi-threading means, the idea is to interleave > >> alternate cycles of two execution streams in order to reduce the > >> losses due to stalls. > >> > >> It looks like it "just" requires an extra address bit (odd/even cycle) > >> to the register file and the same bit selects between pairs of special > >> registers like the PC. > >> > >> Are you telling me that the ALU and instruction decoding is small enough > >> so that I might just as well build two copies of the whole CPU? > >> > >> -- > >> The suespammers.org mail server is located in California. So are all my > >> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > >> commercial e-mail to my suespammers.org address or any of my other addresses. > >> These are my opinions, not necessarily my employer's. I hate spam. > > > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48346
"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag news:aohrpg$qup$1@msunews.cl.msu.edu... > Uwe, > I can route the package, I just can't assemble it. Changing the number So you need to upgrade you assembly technology. You can get BGAs assembled by professional companys, or do it youself, using some advanced assembly tools. Even a amateur can do this. At least one in this world ;-)) http://wwwbode.cs.tum.edu/~acher/bga/index.html -- MfG FalkArticle: 48347
Hi Dave,
That sounds very interesting, have you tried it using ICARUS? I
would like to do so, would you kindly send me (or send me a link) the
source code so that I can start playing around?
Thanks in advance,
Ajeetha
Dave Nelson <pci_model@nelsim.com> wrote in message news:<pan.2002.10.15.17.15.43.388152.4631@nelsim.com>...
> I have a PCI model for verilog simulators which includes:
> arbiter
> master(s)
> slave(s)
> monitor with GUI
>
> It is designed to interface with PCI designs to exercise them and display
> activity and protocol errors.
>
> If there is interest, I will release this as open-source software for
> free download.
>
> Requirements: Unix/Linux/Solaris system with gcc compiler
> Verilog simulator with PLI interface
>
> Please email me if you would find this useful.
>
> Dave Nelson
> pci_model@nelsim.com
Article: 48348In article <3DAD92AF.187507B4@Xilinx.com>, Goran Bilski <Goran.Bilski@Xilinx.com> wrote: >> I can send you a paper submission and a thesis chapter draft on the >> subject if you want. >> > >Please do. Done. >If you double all the registers in the data pipeline, hasn't you doubled the >pipeline? >Or is all functionality between the pipestages shared? The functions between the pipeline stages remain unchanged, so one is pipelining the computation on a finer grain. This can work fairly well for FPGAs as the ratio of LUTs to FFs is 1/1, but that is usually not the case in logic except for highly agressive designs. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48349
Even on the high data rate DSP stuff we are doing, we are often restricted to around
50 MHz on the I/O because of various reasons. In many of those cases signal integrity
is a PITA because of the high edge rates that are not needed in the application.
FWIW, we've run into signal/power integrity issues on a number of third party boards.
Russell wrote:
> Austin Lesea wrote:
> >
> > Theron,
> >
> > The 2V40, 2V80, and 2V250 are available in the CS144 package, or the fg256
> > package.
> >
> > That is as small (and inexpensive) as it gets. Both packages do quite well with
> > regards to SI and EMC/EMI as they were designed from the bottom up to be good
> > performers.
> >
> > The reason why we abandoned the use of pq/hq packages (in planning Virtex II) is
> > that they provide no good ground plane, and even with the low IO count in these
> > smaller die, the ground bounce due to SSOs can be terrible (if the return path
> > ground inductance is as bad as it gets in the pq/hq lead frame packages).
> >
> > One could cut the SSO budget by half, and then use a pq/hq package, but it would
> > be for a very small market segment.
>
> There is a market vacuum for large scale fpgas in packages like pqfp144-240,
> designed for low power, 5V tolerance, and because they're low power, they
> should have slower edge rates. The edges should be deliberately slower or
> adjustable to avoid ground-bounce. You can do a *lot* of dsp with an fpga
> running at less than 50MHz. If there was such an fpga like this that could
> only do 50MHz, i'd still buy them. Last i looked, the atmel at40k looked
> interesting. Ah, but the tools weren't...easy to get or use. Open source?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z