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"mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote: > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > news:bo6l2c$u39$1@bunyip.cc.uq.edu.au... > > mikegw wrote: > > > a) Will a FPGA co-processor board(s) offer a speed improvement in > running > > > our simulation jobs over using a 'traditional' cluster (mosix/Bewoulf)? > > > Bearing in mind that ours will be the only job on the machine so can we > > > reconfigure our FPGA boards to speed calculation? > > > > To parallel what Jon said earlier - the biggest gotcha that seems to > > bite people is IO bandwidth. It's not necessarily hard to develop > > highly pipelined FPGA designs that will crunch your numbers at 100M > > sample/sec, but can you keep it busy? > > > As we will be stepping time, the data (particle information position etc...) > will be the output of the previous 'step'. The only bit that might be messy > is to calculate the relative distances between particles. > > I think that these devices might be the way to go. To me it seems odd that > we seem to be taking a step back to the old analogue computer days when you > 'built' your program. When using FPGAs instead of CPUs without major changes in your algorithms you could simple build a CPU with improved datapath so you may improve the number of operations per cycle but if you manage to get 6 operations done in the number of cycles a cpu does one, you end up with no gain as a actual cpu will have ~6 times the number of cycles as your fpga [1]. When inventing an algorithm that uses the benefits from an fpga you could end up with magnitutes of speedup. For example when solving SAT, you may create a fpga with exact the formula and a counter which will test one set of variables per cycle instead of speeding up your integer operations. This approach is of course very limited to the size of your fpga. So it doesn't seem 'odd' to me that you have to leave "normal" sequential algorithms and think about complete new ideas. bye Thomas [1] with io limitations like pci this is _very_ optimitic for an fpga.Article: 62701
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> = wrote in message news:3FA66AF0.2000306@amontecDELETEALLCAPS.com... > Steve, >=20 > It will support > - all Xilinx components, FPGA CPLD EEPROM FLASH configuration over = JTAG > (programm + verify, with X devices on the JTAG chain) > - FPGA configuration SLAVE SERIAL MODE > - True I2C generic port for onboard I2C-EEPROM configuration and other > I2C-chip configuration. >=20 > We will add more features in the future. >=20 > I will do notification on the begin of 2004 when our pockeTAG is ready > to use and buy. >=20 > Laurent > www.amontec.com >=20 Not just windows based hopefully ? How about linux support as well ? AlexArticle: 62702
theosib@hotmail.com (Timothy Miller) wrote in message news:<80eae8c5.0311041140.7516de73@posting.google.com>... > I am a user of Nedit (nedit.org) and I do a lot of Verilog coding. > When coding verilog modules, you have a module definition which takes > one form, and you have a module instantiation which takes another > form. Even with columnar copy/paste/search/replace, it can be a > tedious process to convert one to the other. Thus, I humbly offer a > Nedit macro I wrote that converts a module definition (header) to an > instantiation. Make a copy of the module definition header, paste it > where you want it, put the cursor anywhere within the copy, and then > run the macro. > Similar function is provided by other scripts available on the web. You could try invoking these scripts from your editor. for example I use the alias \xemacs -l ~/.emacs.batch -l verilog-mode.el !* -f verilog-auto -f save-buffer --batch To take advantage of the features found in verilog-mode.el in my editor(vim) Regards VijayArticle: 62703
The clue is in the Warnings from your synthesis tool. (You did READ them before you posted them?) This isn't a C compiler - every warning is there for a reason and must be justified. The warnings are telling you that you have a mistake in the Verilog which means sum is never used, and will therefore be optimised away, and that in turn leaves the clock and reset redundent, which are duely deleted by the synthesis tool. Have you tried simulating this design? You should have a free copy of Modelsim with the Xilinx tools. Verilog does not have the increment operators that C does. ie sum++ and sum+=1 do not work in Verilog. Also, sum = +a simply sets sum to a. I think you meant sum = sum + a; Why are you using a 28 bit counter to divide a clock by four? Given that the first 26 bits of 'd67108864 are zero, how about a two bit counter? How about using the Spartan-II DLLs? Do you really want two clock domains? How about clocking everything at 50MHz and use a clock enable? -- Ian Poole, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. "Atif" <atif@kics.edu.pk> wrote in message news:6a0a3f23.0311050119.315cbcef@posting.google.com... > Hello all, > While synthesysing the verilog module to generate clock of 12.5MHz > from the default clock of XSA100 i.e 50MHz in ISE WebPack for > XC2S100-TQ144 Spartan-II FPGA, I am getting an error. I have two > inputs clock and reset and one output out. > Here I go step by step: > > i) Synthesis verilog code > No error but the following warnings: > ========================================================================= > * HDL Synthesis > * > ========================================================================= > > Synthesizing Unit <fulladd28>. > Related source file is ddfs.v. > WARNING:Xst:646 - Signal <sum<26>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<25>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<24>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<23>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<22>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<21>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<20>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<19>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<18>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<17>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<16>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<15>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<14>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<13>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<12>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<11>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<10>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<9>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<8>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<7>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<6>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<5>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<4>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<3>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<2>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<1>> is assigned but never used. > WARNING:Xst:646 - Signal <sum<0>> is assigned but never used. > INFO:Xst:1304 - Contents of register <sum<27>> in unit <fulladd28> > never changes during circuit operation. The register is replaced by > logic. > WARNING:Xst:647 - Input <reset> is never used. > WARNING:Xst:647 - Input <clock> is never used. > Unit <fulladd28> synthesized. > ========================================================================= > > ii) Implement design > works fine. But I am only seeing the signal out and not the clock and > reset in the Pad Reports. > > iii) Constraining the Fit: > Create new Source (by right clicking on the verilog code > file)Implementation constraints file.. > > iv) Open Xilinx Pace by clicking "Assign package pin". It gives a > message > "Top Level Block has pins that are not connected to any signals. Do > you want them to treat them as user I/O?" > I click "Yes" > > v) Then I assign the pins P93 to reset, P88 to clock, P67 to out. And > save it. > > vi) Now when I click "Pad Report" to view the pin Assignment it gives > me the following error; > **************************************************************************** > Annotating constraints to design from file "ddfs.ucf" ... > ERROR:NgdBuild:755 - Line 2 in 'ddfs.ucf': Could not find net(s) > 'reset' in the > design. To suppress this error use the -aul switch, specify the > correct net > name or remove the constraint. > ERROR:NgdBuild:756 - Line 3 in 'ddfs.ucf': Could not find net(s) > 'reset' in the > design. To suppress this error specify the correct net name or > remove the > constraint. > ERROR:NgdBuild:755 - Line 6 in 'ddfs.ucf': Could not find net(s) > 'clock' in the > design. To suppress this error use the -aul switch, specify the > correct net > name or remove the constraint. > ERROR:NgdBuild:756 - Line 7 in 'ddfs.ucf': Could not find net(s) > 'clock' in the > design. To suppress this error specify the correct net name or > remove the > constraint. > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file > "ddfs.ucf". > > Writing NGDBUILD log file "fulladd28.bld"... > ERROR: NGDBUILD failed > Reason: > > Completed process "Translate". > **************************************************************************** *** > > here is the verilog code: > **************************************************************************** *** > `timescale 1ns/1ps > module fulladd28(out,clock,reset); > parameter a=28'd67108864; > parameter w = 28; // bit width of phase accumulator > output out; > input clock, reset; > reg [w-1:0] sum; > always @(posedge clock or posedge reset) > if(reset) > sum <= 0; > else > sum <= +a; > assign out = sum[w-1]; > endmodule file://end of module fulladd28 > **************************************************************************** *** > > > Can anyone please guide me why is the error and how to remove it? > Sorry for bothering such a massy e-mail. > > Thanks and Regards > Atif > Research AssociateArticle: 62704
I meant much more. For a detailed design flow, including code coverage, DFT, physical synthesis, etc. regards, nagaraj Mike Treseler <tres@tc.fluke.com> wrote in message news:<3FA83665.9030100@tc.fluke.com>... > 1. Design entry > Tool1: emacs vhdl-mode, verilog mode > Tool2: Quartus block diagram > 2. Simulation > Tool1: Modelsim > Tool2: Aldec > 3. Synthesis > Tool1: Leo Spec > Tool2: Synplify Pro > Tool3: Quartus > Tool4: XST > 4. Place and Route > Tool1: Xilinx Place & Route + static timing > Tool2: Quartus Place & Route + static timing > > -- Mike TreselerArticle: 62705
Thomas Womack wrote: > Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and > USB2 (480Mbps). These are serial, so you've got incredibly high bit > rates on the incoming pins; significantly higher than the clock rates > of reasonable FPGAs. > > Do there exist chips to convert an 800Mbps serial stream to a 50MHz > stream of 16-bit words, and what are they called? I imagine it's not > impractical to hook a couple of those and a couple of SRAMs to a > single FPGA, stream in the signal and then read out little bits of > it if you need to look in the stream for control signals. > > The proposed application is wire-speed video capture to a Firewire > disc from a Firewire or USB2 camera, using an FPGA in the middle to do > the trivial things like dark-frame subtraction. If you want to implement a firewire compatible interface in a FPGA you should consider using a standard firewire phy chip (search T.I.), which essentially does what you say, i.e. convert a fast serial stream to a stream of bytes. It also handles firewire functions such as bus reset and arbitration which involve analog comparators, PLLs and so forth. The phy to link chip interface is standardized and well documented. With an external phy you would "only" have to implement the link level and maybe some transaction level functions in the FPGA. I am somewhat dissapointed that I have never seen any viable 3rd party FPGA IP for the firewire link function. Does anyone know of any such IP available now or on the horizon? JeffArticle: 62706
code coverage : tool1: v-navigator from transeda DFT : DftAdvisor for ASIC but for fpga ????. fpga has built-in jtag boundary-scan. So you can download bsdl file for your device. altera: http://www.altera.com/support/devices/bsdl/bsdl.html xilinx: http://www.xilinx.com/support/sw_bsdl.htm other : http://www.acculogic.com/ResourceCenter/Index.htm STA: tool3 : PrimeTime from synopsys physical synthesis: what do you mean ? regards, fe "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0311050420.679a7a14@posting.google.com... > I meant much more. For a detailed design flow, including code > coverage, DFT, physical synthesis, etc. > > regards, > nagaraj > > Mike Treseler <tres@tc.fluke.com> wrote in message news:<3FA83665.9030100@tc.fluke.com>... > > 1. Design entry > > Tool1: emacs vhdl-mode, verilog mode > > Tool2: Quartus block diagram > > 2. Simulation > > Tool1: Modelsim > > Tool2: Aldec > > 3. Synthesis > > Tool1: Leo Spec > > Tool2: Synplify Pro > > Tool3: Quartus > > Tool4: XST > > 4. Place and Route > > Tool1: Xilinx Place & Route + static timing > > Tool2: Quartus Place & Route + static timing > > > > -- Mike TreselerArticle: 62707
hi scott, I assume your camera output is 125 fps, non interlace? At the output DVI requires 60 fps, that mean you are dropping 65 frames per second. As other mentioned, you need to make sure to swap the buffers in sync with the camera vsync that makes image integrity. Since you are vertically down-scanning, 2 frame buffers is enough, otherwise you may need more than 2 buffers or the dualport rams. One thing I doubt about 125 frames/s camera non interlace?Article: 62708
Joerg Fischer <jf505@yahoo.de> wrote in message news:<3fa823c6$0$12470$9b622d9e@news.freenet.de>...
> Timothy Miller wrote:
> > I'm not sure what is the best form for providing the macro.
>
> Rather not the way you do. Please write a subroutine (ie
> define function_name {
> }
> )
> and just call it in the menu entry (function_name()).
Where do I put that function? Do I put it directly into a file
somewhere? Or does Nedit have a menu for that? What you say makes
sense, so I think I should do it.
>
> BTW, I only looked quickly on the macro and it looks rather
> complicated. Notice that you probably would better use arrays in
> combination with the split() function. (What NEdit version do you
> have? - latest would be 5.4)
I'm not sure what you think I should use arrays for. Could you be
more specific?
The reason it's somewhat complicated is that I have to have two state
machines capable of parsing text and dealing with a variety of
different possible things that might be found. YACC uses state
machines for parsing, and I have found that to be a good approach even
when coding a parser by hand.
>
> Moreover, for sharing macro functions, coming to nedit.org or Niki
> would be nice, too :-)
Oh, I have done that. The first thing I did was email
develop@nedit.org, but I have no idea if it actually got there. No
responses or anything, so that's why I posted to the usenet.
I'm not sure what Niki is. I could go there, or you could share it
for me if you like.
Thanks!
Article: 62709Hi - On 5 Nov 2003 03:32:50 -0800, ra1brzrufe001@sneakemail.com (vijay) wrote: >theosib@hotmail.com (Timothy Miller) wrote in message news:<80eae8c5.0311041140.7516de73@posting.google.com>... >> I am a user of Nedit (nedit.org) and I do a lot of Verilog coding. >> When coding verilog modules, you have a module definition which takes >> one form, and you have a module instantiation which takes another >> form. Even with columnar copy/paste/search/replace, it can be a >> tedious process to convert one to the other. Thus, I humbly offer a >> Nedit macro I wrote that converts a module definition (header) to an >> instantiation. Make a copy of the module definition header, paste it >> where you want it, put the cursor anywhere within the copy, and then >> run the macro. >> >Similar function is provided by other scripts available on the web. >You could try invoking these scripts from your editor. >for example I use the alias >\xemacs -l ~/.emacs.batch -l verilog-mode.el !* -f verilog-auto -f >save-buffer --batch >To take advantage of the features found in verilog-mode.el in my >editor(vim) >Regards >Vijay I second that; I do the same thing from within my editor (Ultraedit). The point is this: you can use a good deal of the power of Verilog mode for emacs *without ever opening up Emacs*. Automatically generating argument lists, either for modules or their instantiations, is a snap. Bob Perlman Cambrian Design WorksArticle: 62710
Jeff Cunningham wrote: > I am somewhat dissapointed that I have never seen any viable 3rd party > FPGA IP for the firewire link function. Does anyone know of any such IP > available now or on the horizon? Maybe one of these? http://www.google.com/search?q=firewire+link+layer+synthesizable+core+2003 -- Mike TreselerArticle: 62711
I tried the Xilinx support line Case # 503586 and haven't gotten a good answer so though I would try here. I am trying to interface to a ZBT SRAM from a Virtex II and was trying to do like in xapp 136 which used 2 DCM's to generate a internal FPGA and an external board clock using external DCM feedback that are aligned. That configuration in simulation (5.2i sp3) shows the external clock is .5ns delayed from the internal clock. We actually need to use a third DCM FX output to generate the clock for the SRAM. When we do that the external clock is now leading the internal clock by 1 ns. I didn't understand why what clock feeds both DCM's would change the timing and since our timing is tight I need them to be closely aligned. The external clock is output using a DDR FF and I used the DCM wizard which should of put in all the problem bufg/ibufg etc which the V2 users guide says are needed if it is going to compensate for the pad to DCM delay. I also think only 2 DCM's are needed, 1 to generate the internal clock using FX and a second to generate the deskewed external clock. That configuration seems to generate the same timing as the 3 DCM version. Anybody know the correct solution? Also does anybody know an easy way on the board to measure the alignment between an internal and external clock? Bringing the internal clock out to a pin would require knowing the actual loaded buffer delay which I wouldn't think I could get very accurate. If I can accurately measure it and its not a simulation artifact I should be able to tweak the phase shift to make it align. I would think that should then be stable across boards. Couple other questions, has anybody seen the hold time of the V2 IOB flip flops documented? For the DCM is is ok to feed the locked from one into the reset of the next or do we need to hold the reset for at least 3 clocks? Different documentation shows different ways and the direct connection didn't work under 6.1 simulation. Thanks, David GessweinArticle: 62712
scott, input 125 fps, output 60fps. 2 frames sram. write one, read other. write pointer faster read pointer about 2x. need to drop 65 frames per second. sram is not dual port. can't write while reading. got it?Article: 62715
"Scott Connors" <scott.a.connors@boeing.com> wrote in message news:5f825c95.0311041425.58c6ac6e@posting.google.com... > Hello all. > > I am involved in a project where I need to provide a DVI display of a > camera input. Here are the technical specs of the matter: > > I have a 125 Hz frame rate camera coming in to my FPGA. The camera > resolution is 640x480. It has the usual vsync and hsync signals, with > dead time in some spots. A typical camera. > Others have already described methods to ensure that your read and write pointers don't cross. I have a couple of additional comments though. I don't understand why you get a white line when you pan the camera. You should get a horizontal line of horizontal dislocation that moves up or down the screen, but there should not be anything there that is not in the original image. If there is a white line, for example when the image is dark, then you have something else going wrong. The fact the camera is running at 125 Hz suggests someone was concerned about motion. Going down to 60 Hz is going to do nasty stuff to your motion. Most times you will be dropping one input frame, but sometimes you will be dropping two in a row. If the monitor will handle 62.5 Hz, you will get better motion if you lock the output frame rate to the input. Of course, if the monitor also has a frame buffer in it, that defeats the purpose. If I was you I would first make a free-running 62.5 Hz output raster, and generate a video pattern with horizontally moving vertical bars. If this displays without tearing on your monitor, then you can lock the output raster to the input and do the scan conversion. (This also makes your double buffering easier).Article: 62716
Hi, I'm a newbie to FPGA and Linux world. I have a general question concerning both. I have a workstation with Linux installed. A Virtex II Pro FPGA Module is plugged in the backplane of the workstation. I'm wondering if I need to write a device driver for the FPGA module in order for the Linux box to recognize the card? I want a software program running on the Linux machine to be able to poll a few registers on the FPGA module, bascially through memory map. Is this possible without a device driver? Thanks in advance for all the help. MichelleArticle: 62717
I will write a open source arm vhdl model from this month on. I hope to have it ready in approximately 2 months using LeonSoc as a framework and implementing a arm1 integerunit. Anyone that wants to participate is wellcome. Konrad EiseleArticle: 62718
"john jakson" <johnjakson@yahoo.com> wrote in message news:adb3971c.0311042304.43735b02@posting.google.com... [snip much] > I am curious to know what folks think of combining HDL,CSP,C rather > than keeping HW & SW miles apart as in conventional engineering. See Celoxica's products. And observe how they've backed away from a reasonably pure CSP approach like yours, and put more emphasis on the pure-C thing. Software people have an irrational and passionate distaste for fine-grained parallelism. I don't think you have much chance of changing their collective mind. That observation should not distract you from an interesting and (one hopes) ultimately fruitful project. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 62719
> I will write a open source arm vhdl model from > this month on. I hope to have it ready in > approximately 2 months using LeonSoc as a framework > and implementing a arm1 integerunit. Anyone that wants > to participate is wellcome. > Konrad Eisele Many tried, all got kicked in the back by ARM. If you can create something useful, get ready for a contact from one of their lawyers, Andras TantosArticle: 62720
Jon Beniston wrote: > H. Peter Anvin <hpa@zytor.com> wrote in message news:<bo7s6b$ddg$1@cesium.transmeta.com>... > > Hello, > > > > Does anyone happen to know of a stock FPGA prototyping board with (a) > > onboard oscillator, (b) Ethernet and (c) at least 4 MB of SRAM? > > > > I have a need for such a board in a configuration which needs to > > support a very large range of input frequencies, hence I would prefer > > using SRAM; however, most boards seem to have no more than 1 MB SRAM > > and the rest SDRAM... which would have to be supported as an > > asychronous clock domain in order to work correctly at the low end of > > the frequency range. > > > > -hpa > > http://www.xess.com Sorry to say XESS doesn't have any boards right now with this much SRAM. We do have boards with 16 MB of SDRAM, but not SRAM. -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 62721
Is it fair for programmers to work long hours of overtime and not get paid for the work? If you are a programmer who has been working for a while you probably know there can be some issues with not getting paid for overtime. Companies can take advantage of programmers with the long hours needed to complete projects. If you feel you are having difficulty getting paid for what you have done, you are not alone. There are people out there who are willing to lend a hand. Check out this site: http://www.bigclassaction.com/class_action/computer.html You can send them a complaint for free and they pass them along to lawyers for evaluation. This one seems to be specifically for programmers who have worked for Computer Sciences Corporation. There is, however, lots of other info on the site that might be more to what you need, but this is a currently hot subject. I hope this might help somebody out. kr0Article: 62722
"David Gesswein" wrote: > I am trying to interface to a ZBT SRAM from a Virtex II and was trying to > do like in xapp 136 which used 2 DCM's to generate a internal FPGA and an > external board clock using external DCM feedback that are aligned. I don't have any experience with ZBT SRAM, but in general terms I've been using the DDR mechanism to generate outgoing source-synchronous bus clocks and it's worked like a charm for frequencies approaching 200MHz. Of course, careful board layout is a part of this as well. > Also does anybody know an easy way on the board to measure the alignment > between an internal and external clock? Use FPGA Editor to bring the internal clock out to a pin as close to the external clock as you can (to reduce board/layout/measurement errors). FPGA Editor will give you routing delay information. I think it's accurate to the pin. > For the DCM is is ok to feed the locked from one into the reset of the next > or do we need to hold the reset for at least 3 clocks? I think it's OK, but I've never done it that way. I'm paranoid and flip-flops are cheap and plentiful. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62723
Leon Heller wrote: > > The Big Bear wrote: > >> I've got a design for a $40 assembled and tested fpga dev board that is >> on a pci card for use in a standard PC (probably running linux). It would >> have ethernet and some other ports for experimentation, but basically the >> fpga would become a configurable pci device. Possible applications could >> be mpeg encoding/decoding, encryption/decryption, or just plain >> experimentation with fpga technology. I'm debating whether to do a >> production run of these things, but if they won't sell I don't want to >> bother. Would anyone consider buying such a thing? > > What FPGA? XC2S100E 100K gates 2,700 logic cells. It's a Xilinx partArticle: 62724
Hi all, Does anyone know the right steps to make ISE infer DDR registers from a RTL code? I am following the template that ISE suggests in their answer record #15776. Apart from this, I also make sure to set the IOB option during MAP. I still cannot see the dual-data rate flops being used in the map report. However, when I open FPGA editor, I can see that my two flops were mapped to registers that are placed in the same IOB. How do I know for a fact that the IFDDRSE (or a corresponding) primitive is actually being used? Thanks Anil
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