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I don't believe that you'll find a monolithic 16Mx16 SRAM. You'll need multiple devices. You can start your search on QuestLink. There are plenty of 10 ns, x16 asynchronous RAMs out there. There are also some x32, 200 MHz+ synchronous RAMs. http://www.questlink.com/categorySearch_sub.jhtml?type=cat¶m=130700 -- Steve Knapp "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:lEgLb.1476$rt.397@newssvr29.news.prodigy.com... > I'm trying to determine if anyone makes a large/fast static RAM part. 16M > (or more) x 16 bits (or more), 10ns. > > I can't afford the address-to-data-out latency of dynamic RAM. There are > ways around this, of course, but SRAM would be so much simpler. > > Any ideas? > > Thanks, > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 64601
Actually, we have had a number of 1000J's since the beginning of August last year. They are not suppose to last too long in a 3.3V system, but they work great in a few designs we have especially with the new speed files (still needs to be faster though :-). The problem now appears to be getting production parts in volume. I have wanted to place an order for months, but they can't give me a delivery date, so we can't launch the product :-( ricky > Look at the latest Spartan III datasheets (ds099-1.pdf). All devices are > still marked as not released yet. From this group I expect that in the next > weeks a batch of engineering samples (probaly S50/200/400/1000 ?) with get > out to the distributors. Only the S50J is available (without > BRAM/Multipliers).Article: 64602
Martin Euredjian <0_0_0_0_@pacbell.net> wrote: : I'm trying to determine if anyone makes a large/fast static RAM part. 16M : (or more) x 16 bits (or more), 10ns. : I can't afford the address-to-data-out latency of dynamic RAM. There are : ways around this, of course, but SRAM would be so much simpler. 4Mibit Devices are in full production (256kix16). I guess it will take some time until 256MiBit are available. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64603
Check ISSI, they have a 18 Mb (x18,x36,x72), synchronous static ram. Seems they have a very low latency, and support bursts. "Martin Euredjian" <0_0_0_0_@pacbell.net> ha scritto nel messaggio news:lEgLb.1476$rt.397@newssvr29.news.prodigy.com... > I'm trying to determine if anyone makes a large/fast static RAM part. 16M > (or more) x 16 bits (or more), 10ns. > > I can't afford the address-to-data-out latency of dynamic RAM. There are > ways around this, of course, but SRAM would be so much simpler. > > Any ideas? > > Thanks, > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 64604
I see IDT has 1M x 18 ZBT. You are right, 256M is probably far off. I posted on the outside chance that there was an obscure part out there that I didn't come across. These days searching on the net can produce so many links that it is humanly impossible to sort through all of them. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:btk8ac$3ur$1@news.tu-darmstadt.de... > Martin Euredjian <0_0_0_0_@pacbell.net> wrote: > : I'm trying to determine if anyone makes a large/fast static RAM part. 16M > : (or more) x 16 bits (or more), 10ns. > > : I can't afford the address-to-data-out latency of dynamic RAM. There are > : ways around this, of course, but SRAM would be so much simpler. > > 4Mibit Devices are in full production (256kix16). I guess it will take some > time until 256MiBit are available. > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64605
As it is my first time to comp.arch.fpga I will briefly mention that I'm working on a front-end verilog compiler that targets both academic FPGAs as well as Altera's Quartus Flow. I am at a point where I need benchmarks. I have searched the web as well as www.opencores.org, but I need more. The main aspect of the benchmark which would be most useful is both size (actual transistor size) and the existance of multipliers in the design. Thanks, Peter Jamieson PhD. Candidate at the University of TorontoArticle: 64606
A new release of HDLmaker is available at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a Verilog/VHDL higharchical code generator and script generator. It's offered free of charge under a BSD style open source license by Polybus Sytems Corp. HDLmaker has extensive support for all Xilinx FPGAs, Virtex2P and Spartan3 support has been improved in this release. It also supports Altera Stratix devices and ASIC development.Article: 64608
Last year X announced a cool design win using their parts in a new Gibson guitar line. Neat stuff. Couple days ago I see that A has a press release saying they stole the business with NIOS + Cyclone. Today I see X saying S3 is the clear winner and Gibson is using it exclusively. Anyone know what is really going on? Just curious. The Gibson product is kinda cool regardless of who's part is in it. PMArticle: 64609
This is a dual port ram, then you have 2 ports... (duh!) port a and b.
in port a you have:
addra: IN std_logic_VECTOR(8 downto 0);
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
ena: IN std_logic;
wea: IN std_logic;
Where:
addra: is the address where you will store the data.
clka: is the clk
dina: is the data that will be store in the ram on address addra
douta: is the data stored in address addra
ena: enable the ram
wea: write the data DINA in address ADDRA, if asserted, else, read
the data
in address ADDRA and put in DOUTA
If you want write in RAM, you will assert WEA, put the address in
ADDRA, and the data in DINA, all in one clock.
If you want read, you will put the adrees in ADDRA, and read in
DOUTA.
Something this...
you can learn more in
http://direct.xilinx.com/bvdocs/appnotes/xapp173.pdf
Tobias Möglich <Tobias.Moeglich@gmx.net> wrote in message news:<3FFD80FE.9D9E69A4@gmx.net>...
> Hello
>
> I'm using the core generator from Xilinx for installing a true dual port
> RAM
> But I wonder how I can handle it in the VHDL code ???
> Could someone give me an advice??
>
> This is what Iknow already:
> Of course I put a component in the archticture (as I did it in the
> example
> below)
>
> architecture Behavioral of dpram is
> component dpram
> port
> (
> addra: IN std_logic_VECTOR(8 downto 0);
> addrb: IN std_logic_VECTOR(7 downto 0);
> clka: IN std_logic;
> clkb: IN std_logic;
> dina: IN std_logic_VECTOR(7 downto 0);
> dinb: INOUT std_logic_VECTOR(15 downto 0);
> douta: OUT std_logic_VECTOR(7 downto 0);
> doutb: OUT std_logic_VECTOR(15 downto 0);
> ena: IN std_logic;
> enb: IN std_logic;
> wea: IN std_logic;
> web: IN std_logic
> );
> end component;
>
> begin
> -- Verwendung des cores (instantiation of the core)
> dpram_block_1 : dpram -- dpram ist der component_name; dpram_block_1 ist
>
> die Instanz
> port map
> (
> addra => addra,
> addrb => addrb,
> clka => clka,
> clkb => clkb,
> dina => dina,
> dinb => dinb,
> douta => douta,
> doutb => doutb,
> ena => ena,
> enb => enb,
> wea => wea,
> web => web
> );
>
>
> But how can I say where to store the values in the RAM ???
> There must be something possible as described below:
> But if I would use this code, I would not know where in the RAM the
> values
> are stored.
>
> WRITE : process(clkb) -- Daten schreiben ins RAM (data -> ram)
> begin
> if rising_edge(clkb) then
> if (cs_DSP = '0' and IORW_DSP = '1') then
> -- Polarität prüfen
> -- ram(conv_integer(addrb)) <= data_b;
> -- von dinb in den Speicher (hoffentlich blockRAM !!)
> dinb <= data_b;-- after 5 ns;
> -- von dinb in den Speicher (hoffentlich blockRAM !!)
> else dinb <= (others=>'Z'); --after 3 ns;
> end if;
> end if;
> end process;
>
>
> Do you have any example code??
> It would be nice if you could send it to me just to get ahead.
>
>
> MfG, Tobias Möglich.
>
> --
Article: 64610at Thu, 08 Jan 2004 17:42:41 GMT in <lEgLb.1476$rt.397 @newssvr29.news.prodigy.com>, 0_0_0_0_@pacbell.net (Martin Euredjian) wrote : >I'm trying to determine if anyone makes a large/fast static RAM part. 16M >(or more) x 16 bits (or more), 10ns. > >I can't afford the address-to-data-out latency of dynamic RAM. There are >ways around this, of course, but SRAM would be so much simpler. > >Any ideas? > >Thanks, > > The biggest async parts (the classic SRAM, super-simple interfacing) are the 16 Mbit parts from Cypress (CY7C1061AV33) and Toshiba (TC55V16100FT). Sync parts (much more complex interfacing, a bit of a PITA) are the 72 Mbit Cypress CY7C1482V33. Don't expect anything much larger, especially on the async parts, anytime soon. These aren't cheap, either, although you gain an incredible amount, especially with the asynchronous parts, without all the overhead associated with DRAM. Manufacturer interest will depend on your order size. How many are you looking to get? Millions? Or onesy-twosey? If the former, you may get Cypress' attention. If the latter, you'll no doubt have to be satisfied with what's available. -- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com (remove d., .7, not, and .NOSPAM to reply)Article: 64611
Alex Rast <ad.rast.7@nwnotlink.nospam.com> wrote: ... : The biggest async parts (the classic SRAM, super-simple interfacing) are : the 16 Mbit parts from Cypress (CY7C1061AV33) and Toshiba (TC55V16100FT). : Sync parts (much more complex interfacing, a bit of a PITA) are the 72 Mbit At least the Cypress page doesn't sound like instant availability for the 16M asynchronous parts -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64612
Patrick, We are just as puzzled as you. We also saw Altera's press release with Gibson, yet Gibson awarded us the "supplier of the year award" at CES in Las Vegas just moments ago..... http://biz.yahoo.com/prnews/040108/sfth127_1.html Could be they are going to use the "hard-to-copy" program in an attempt to reduce costs, or it could be that a new manager or new consultant has decided that they must "take control" and "make decisions." All very puzzling. It would not surprise me to hear in a few months that Gibson has an ASIC for their guitar from LSI, Toshiba, or IBM.... Austin Patrick MacGregor wrote: > Last year X announced a cool design win using their parts in a new Gibson > guitar line. Neat stuff. > > Couple days ago I see that A has a press release saying they stole the > business with NIOS + Cyclone. > > Today I see X saying S3 is the clear winner and Gibson is using it > exclusively. > > Anyone know what is really going on? > > Just curious. The Gibson product is kinda cool regardless of who's part is > in it. > > PM > >Article: 64613
Let's remember that the original question was for 256 Mbits = 32 MBytes. That's several generations of Moore's Law away. If you figure six transistors per memory bit (plus decoding), that device would be getting close to 2 Billion transistors. Even the largest FPGAs have a factor 4 fewer tightly-packed transistors, and they command a price of >$ 1000. If you really need RANDOM access in 10 ns, this may be impossible today. If there is some structure, predictability etc, then you might be able to do it with DRAMs plus caching (???) Peter Alfke ========== Uwe Bonnes wrote: > > Alex Rast <ad.rast.7@nwnotlink.nospam.com> wrote: > ... > : The biggest async parts (the classic SRAM, super-simple interfacing) are > : the 16 Mbit parts from Cypress (CY7C1061AV33) and Toshiba (TC55V16100FT). > : Sync parts (much more complex interfacing, a bit of a PITA) are the 72 Mbit > > At least the Cypress page doesn't sound like instant availability for the > 16M asynchronous parts > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64614
Ricky Sticky wrote: > Actually, we have had a number of 1000J's since the beginning of August > last year. > > They are not suppose to last too long in a 3.3V system, but they > work great in a few designs we have especially with the new speed > files (still needs to be faster though :-). > > The problem now appears to be getting production parts in volume. > I have wanted to place an order for months, but they can't give > me a delivery date, so we can't launch the product :-( > Maybe you don't want enough ? - This is a press release that seems to be claiming high volume adoption ? -jg #Thursday January 8, 5:43 pm ET #About Xilinx Low Cost FPGAs #Xilinx first shipped the Spartan-3 family in March 2003 as the world's #first and only FPGA utilizing 90nm process technology. The Spartan-3 #platform is the world's lowest cost FPGA with unrivaled price points, #starting at under $2.95*. #<...> This has driven Spartan-3 device adoption further into higher #volume consumer applications and hastened the decline of ASIC designs.Article: 64615
> Patrick MacGregor wrote: > >> Last year X announced a cool design win using their parts in a new Gibson >> guitar line. Neat stuff. >> >> Couple days ago I see that A has a press release saying they stole the >> business with NIOS + Cyclone. >> >> Today I see X saying S3 is the clear winner and Gibson is using it >> exclusively. >> >> Anyone know what is really going on? >> >> Just curious. The Gibson product is kinda cool regardless of who's >> part is >> in it. Austin Lesea wrote: > Patrick, > > We are just as puzzled as you. > > We also saw Altera's press release with Gibson, yet Gibson awarded us > the "supplier of the year award" at CES in Las Vegas just moments ago..... > > http://biz.yahoo.com/prnews/040108/sfth127_1.html Of course, these two do not have to be mutually exclusive... > > Could be they are going to use the "hard-to-copy" program in an attempt > to reduce costs, or it could be that a new manager or new consultant has > decided that they must "take control" and "make decisions." > > All very puzzling. Not really. One of the better ways to get improved supply and price is to have both brands ready to deploy, so you can 'wave the opposition under the rep's nose'. It also does no harm, if you really do intend to move to ASIC, and if there are questions about availability of either vendor's devices, this also makes sound sense. Where is the puzzle here ? -jgArticle: 64616
"B. Joshua Rosen" <bjrosen@polybus.com> wrote: > On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote: > > > Thus, this leads to the question of how to I learn about what modeling > > style will be synthesizable for my particular tools? > > > > The text won't be able to teach me this, since it is just dealing with > > the problem in general. Obviously this must be in the tooll > > documentation, so I would ask: > > > > Is there good modeling style info in Xilinx tools so that one can learn > > how to make synthesizable models for Xilinx tools reliably? > > > > Finally, how to VHDL and Verilog compare in terms of *inherent* > > synthesizability of models, or does the same problem essentially exist > > for both? > > I've never run into anything that synthesized with Synplify and not with > Precision or vice-versa. Synthesis directives are not standardized so they > aren't generally portable although Precision secretly supports a small > subset of Synplify directives. XST is a different story, there are lot's > of things that didn't work the last time I tried it (I haven't > tried the latest rev so it may have improved). > > Synplify has a good user's guide. If you follow it's rules you won't have > any problems with any decent synthesis tool. I can't speak for Verilog, but in VHDL I've seen allready problems to migrate from Synopsys to Synplicity and vice versa. Further there are constructs that may synthesise, but fail in our tool for formal verification. I would say, that's the difference between someone just learning the HDL and an experienced HW-Designer. A good book about synthesis will help. Experience or an experienced tutor will might be the other solution. As I bet there's somenone likely starting to bash on VHDL and telling me that will never happen with Verilog, I would bet anything, the same problem will rise when using Systemverilog (which is intended to replace Verilog in the next years). bye Thomas StankaArticle: 64617
Hi all, trying to follow the advice of one of the regulars on this forum and learn to use the text based version of ModelSim 5.7. However, using the file-find facility I have not been able to find Vsim and Vlib on my installed version of Mentor Graphics on my machine. Is this normal? I figured there was actually meant to be files which could be accessed via the command interface... - KArticle: 64618
Austin, you are probably the right person to answer these questions about Spartan-3: 1. If I use no IOBs of a given Bank at all, can I leave VCCIO of that bank unconnected? 2. Can I still use VCCAUX based IO standards like LVDS? 3. Can I use open collector like outputs without VCCIO connected? (Eg conditionally pull an output to ground) This request might sound strange, but we have a board where VCCIO of two banks is supplied by another board. No a new application was brought up were the second board is not needed except for the generation of VCCIO. SO I would like to get rid of it. Thank you in advance, Kolja SulimmaArticle: 64619
jk wrote: > Hi all, > > trying to follow the advice of one of the regulars on this forum and learn > to use the text based version of ModelSim 5.7. > > However, using the file-find facility I have not been able to find Vsim and > Vlib on my installed version of Mentor Graphics on my machine. Is this > normal? I figured there was actually meant to be files which could be > accessed via the command interface... If you are using ModelSim SE, you may have to compile the libraries yourself. I found some information on how to do this in the Xilinx suport forum. - AndersArticle: 64620
The Institute AIFB at the University of Karlsruhe, Germany, invites applications for a full time research position as part of the DFG research project "Optimization on reconfigurable architectures". Applicants must have a diploma/master in computer science, electrical engineering or a related field. Payment will be according to BAT IIa. Experience in soft computing (evolutionary algorithms / ant colony optimization) and/or reconfigurable architectures (FPGA / rmesh) is a plus. More information about the position can be found at (in German) http://www.aifb.uni-karlsruhe.de/~bes/bes/stellen/optrekbat/DFG-optrek- suche.html Please send your application to Bernd Scheuermann Institut AIFB Universität Karlsruhe (TH) D-76128 Karlsruhe, Germany or e-mail: scheuermann@aifb.uni-karlsruhe.de Please include in your application: - Resumé - CV - references (scanned or photocopy) - certificates (scanned or photocopy)Article: 64621
I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system with external FLASH (and RAM) memory. The Altera FPGA (probably ACEX1K) has a JTAG port so when I get the 1st prototype I can download a configuration using the JTAG. But how can I program the FLASH when it's soldered on the board? I can't find a FLASH with a JTAG interface. I can't preprogram the FLASH since I don't have the code before assembly and probably want to change it even in the field. Any suggestions? Thanks GeorgeArticle: 64622
What's you quantity per year. You could have 16 of the cypress sevices places on a PBC or even die bonded into a module. And that module may even have a market on it's own. THis is what the IC mfgs do when they are stepping up to a larger size device. gmArticle: 64623
Jim, This is true. FPGA business is not usually as tough as the commodity business model you describe, but hey, if you did the design with both vendors, then you can bang them together until the lowest price falls out. I used to do that all the time when I was in the telecom business. Did not like it, but I did it. Only because the phone companies bang the vendors together until the lowest price falls out. Austin jim granville wrote: >> Patrick MacGregor wrote: >> >>> Last year X announced a cool design win using their parts in a new >>> Gibson >>> guitar line. Neat stuff. >>> >>> Couple days ago I see that A has a press release saying they stole the >>> business with NIOS + Cyclone. >>> >>> Today I see X saying S3 is the clear winner and Gibson is using it >>> exclusively. >>> >>> Anyone know what is really going on? >>> >>> Just curious. The Gibson product is kinda cool regardless of who's >>> part is >>> in it. > > Austin Lesea wrote: > >> Patrick, >> >> We are just as puzzled as you. >> >> We also saw Altera's press release with Gibson, yet Gibson awarded us >> the "supplier of the year award" at CES in Las Vegas just moments >> ago..... >> >> http://biz.yahoo.com/prnews/040108/sfth127_1.html > > > Of course, these two do not have to be mutually exclusive... > >> >> Could be they are going to use the "hard-to-copy" program in an >> attempt to reduce costs, or it could be that a new manager or new >> consultant has decided that they must "take control" and "make >> decisions." >> >> All very puzzling. > > > Not really. One of the better ways to get improved supply and price > is to have both brands ready to deploy, so you can > 'wave the opposition under the rep's nose'. > It also does no harm, if you really do intend to move to ASIC, > and if there are questions about availability of either vendor's > devices, this also makes sound sense. > Where is the puzzle here ? > > -jg >Article: 64624
Kolja, Not recommended. If nothing is used, the current consumed is ~ 2mA per bank, so why do you want to leave them disconnected? You do not have to provide bypass caps if they are not used, so there is little penalty. Conencting it up provides the return paths for the ESD protection, etc. Per question 2: I do not understand. Vccaux is 2.5V, so only 2.5V LVDS IOB primitive is supported. Since LVDS is a standard, 2.5V or 3.3V makes no difference at all: a 2.5V powered LVDS buffer receives or drives a 3.3V LVDS buffer. And finally, no, you must connect Vcco is you are to use the IOB at all, for any reason. Austin Kolja Sulimma wrote: > Austin, > > you are probably the right person to answer these questions about > Spartan-3: > > 1. > If I use no IOBs of a given Bank at all, can I leave VCCIO of that > bank unconnected? > > 2. > Can I still use VCCAUX based IO standards like LVDS? > > 3. > Can I use open collector like outputs without VCCIO connected? > (Eg conditionally pull an output to ground) > > This request might sound strange, but we have a board where VCCIO of > two banks is supplied by another board. No a new application was > brought up were the second board is not needed except for the > generation of VCCIO. SO I would like to get rid of it. > > Thank you in advance, > > Kolja Sulimma
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