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> 2. Remember the infamous Verilog vs. VHDL competition that Cooley did > a few years back? See this link: > <http://www.deepchip.com/items/snug99-42.html> > In this contest, not a single VHDL contestant was able to finish the > problem. Not one. > That's the most presuasive reason I've seen for using Verilog! Although I'd like to see an equal number of contestants in both languages. If they redo this contest with a similar outcome, it will definitely be time for me to learn Verilog! -- PeteArticle: 68151
Jim Lewis <Jim@SynthWorks.com> wrote in message
snipping
>
> > Why is everyone saying that VHDL is used more by FPGA designers?
> Because according to marketing statistics it is.
>
That was certainly true in the past but with the collapse in the no of
ASIC design starts, most of those x ASIC guys will probably come over
to FPGAs bringing their prejudices with them. Moi included, infact I
don't know any original FPGA guys except in this NG. How on earth
could FPGAs not have grown with out such an influx of new design
starts. And as FPGAs tackle what ASICs did a few years ago in size,
bigger EDA budgets will follow.
> > Everyone I know (and I know a LOT of FPGA designers) is doing Verilog,
> > with the exception of the aerospace industry (because of military
> > contract requirements).
> All prior measures of Verilog vs VHDL were done with
> marketing statistics which relate to $$$ of EDA tools
> sold and nothing to do with actual user base. First,
> ASIC tools $$$ >>> FPGA tools $, hence, the EDA
> market statistics really only show what the ASIC market
> was doing. Furthermore, for the period that is
> often quoted, a Verilog simulator cost more than VHDL
> simulator.
>
Acording to John Cooley's ESNUG, the available stats are always 2yrs
late.
You would think that Xilinx & Altera have a better picture since they
have to justify EDA support for both, in their tools and in marketing
examples. Anyway nice to see both supported about evenly. If one
vendor dropped my language, I'd drop them.
> What is the user base really at? Based on newsgroup
> traffic (comp.lang.vhdl vs. comp.lang.verilog),
> VHDL usage is 2X that of Verilog.
>
Aha, about as useless as counting the no of HDL textbooks in the local
EE store. But the book writing industry is remote from HW design, they
write what the Universities request. Infact its a wonder Verilog
survived the almost 100% teaching of VHDL in most schools. I rarely
hear of Verilog being tought in any school.
> It would be interesting to see some current market
> statistics that some how measure user base with
> tool cost and number of tools factored out (a lint
> tool is nice to have for VHDL, but a must have for
> Verilog).
>
>
Never used a lint tool, somehow never seemed to need it since the
simulation or synthesis tool will give me the same info and a whole
lot more.
> > Synopsys's CEO all but admitted that because of Systemverilog, they
> > will not be doing add-on work with VHDL in the future. This is HUGE.
> At DesignCon this year, Aart back peddled alot.
> He projected that Synopsys will be supporting VHDL for at
> least another 10 years. This gives us lots of time
> to forget about what he said when he learns he was
> wrong.
>
Well the big $ for Synopsys has always been Verilog & ASICs, you can
understand why they hate 2 languages for 1 task. No wonder they are
nowhere in FPGAs.
> What was Aart's motivation? He bought the company that
> originated SystemVerilog. He needs to justify the purchase.
> He has good market share in Verilog and neglible market
> share in VHDL, so little supprise that he is trying to convince
> the market to move to SV.
>
The ASIC biz is moving to SV, they love all the improvements, they
hated all the other also rans whatever the language.
> Besides, Aart's prediction may be the doom of SV. After all
> just a short while ago, he was promoting SystemC.
>
Poppycock!
SystemC is a different beast, not intended for ASIC or FPGA design at
the grunt level, great for system modelling though. Another tool that
brought in 0 $ for Synopsys, why not let it go open, see if it flies
by itself, about time it had its own NG.
>
> > Verilog has a lot in common with C. If you already are
> > familiar with C, then learning Verilog will go much faster.
> Well lets be honest.
> Verilog and C are similar WRT C's operators and C's if statement.
The similarities are massively overstated for sure and limited to just
expression syntax, but that is good IMNSO.
> For all other parts there are significant differences (no switch
> statement in Verilog, no "{" and "}" instead they are replaced
> with "begin" and "end" - talk about verbosity).
> As one who did a significant amount of programming in C in
> college, the one big thing I hated about C was the operators -
> it is much easier to understand VHDL's and, or, xor operators.
Each to his own taste, I love the Verilog concisenes when expressing
nets and logic, very difficult to do in C without resorting to shifts
and masks that hides the meaning. In fact in the C compiler I am
working on parttime, I am adding Verilogs expression syntax to C but
only some of the other heavy duty stuff.
>
>
> entity ShiftMxN is
> generic (
> depth : integer := 4 ;
> width : integer := 8
> ) ;
> port (
> Clk : In std_logic ;
> ShiftIn : In std_logic_vector ( width-1 downto 0) ;
> ShiftOut : Out std_logic_vector ( width-1 downto 0)
> ) ;
> end ShiftMxN ;
> architecture RTL of ShiftMxN is
>
> type RegBankType is array(Depth - 1 downto 0) of
> std_logic_vector(Width-1 downto 0) ;
> signal ShiftReg : RegBankType ;
> begin
>
> ShiftReg <= ShiftReg( (Depth - 2) downto 0) & ShiftIn when rising_edge(Clk) ;
> ShiftOut <= ShiftReg( Depth - 1) ;
>
> end RTL ;
>
>
Aha, its that damned std_logic_vector all over the place that turns me
right off, not forgetting the horrible choice of words like entity.
Not much of a fan for Verilogs growing awefull dictionary either now
well past 100 keywords.
regards
johnjakson_usa_com
may the logic be correct and synthesizeable, and where is NWirth when
we really need someone to do it with elegance!
Article: 68152petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0403271536.76667f34@posting.google.com>... > > 2. Remember the infamous Verilog vs. VHDL competition that Cooley did > > a few years back? See this link: > > <http://www.deepchip.com/items/snug99-42.html> > > In this contest, not a single VHDL contestant was able to finish the > > problem. Not one. > > > > That's the most presuasive reason I've seen for using Verilog! > Although I'd like to see an equal number of contestants in both > languages. > > If they redo this contest with a similar outcome, it will definitely > be time for me to learn Verilog! > > -- Pete The contest was so trivial that it was really more like a gaming event for quick responses. It was a counter that counts up by 3 or down by 5 plus 1 or 2 other details. Nobody seemed to notice that any competant EE should be able to do that in TTL schematic in 5mins on back of envelope. They had 2hrs I think. The VHDL guys were more plagued with SW and lib setup issues than not being able to do the design. The Verilog guys had less stuff to get in the way. If I were running such a contest I would make sure both setups were really ready to go and for a much much larger project maybe more in line with a few 1000 or 1000 gate equiv. Wouldn't that be a design fest. regards johnjakson_usa_comArticle: 68153
"Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c44v4t$6fup7$1@hades.csu.net>... > "paris" <malaka@email.it> wrote in message > news:c43le0$20va$1@avanie.enst.fr... > > what i dont understand is why does "Verilog has a lot in common with C" is > > so important? > > if you want programmets to write Verilog, then i'd understand, but i would > > have thought that people doing hardware, would be hardware people, > > electrical engineering people. I just dont understand this "common with C" > > thing. > > I agree with you! In fact, I will avoid thinking like C while designing in > Verilog. Verilog is not C, or any other programming languages for that > matter. We use Verilog to describe a hardware, not to program a computer. > So, thinking like C while writing Verilog code will most likely get one in > trouble, as I have experienced myself! > > Hendra It seems to be politically correct right now for HW guys to trash any reasonable conversation about computing in general esp when there are some real similarities between HW & SW for some problems. Since many HW designs are single clock domains this is esp irksome. Most every HW I have ever designed has been first simulated in C (or Pascal or whatever going wayback). When that model works properly in a cycle fashion, then I can spend more expensive HDL cycles duplicating the test runs with far fewer logic problems to work out. I am currently doing a cpu in both Verilog and C. I cut n paste the assigns and always contents into C functions (of the same name) and adjust the syntax issues. There is now a 1 to 1 correspondence. The HDL has to be written in a certain way for this to work, ie limited hierarchy, and always contents in reverse timing dependant order but the payoff is huge. A cpu can run in C simulation close to 0.1Mips in real time. In the fastest HDL simulator it would be 100s slower. A few milion cpu cycles is a few mins. There are tools to help do this, but the manual method is not that bad. Infact most all commercial cpu designs do this but with different teams replicating the work. This would be harder to do with VHDL but I am sure its doable. When my C compiler gets done (thanks to Hanson & Fraser LCC), it will have a nice subset of Verilog right inside making C+V HW design a whole lot easier. regards johnjakson_usa_comArticle: 68154
Xilinx tools will port it for him... but I agree with you, why bother in the first place. "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:c44um5$6gao7$1@hades.csu.net... > "ted" <edaudio2000@yahoo.co.uk> wrote in message > news:c54bf83f.0403270552.266bbebb@posting.google.com... > > How does AHDL (Altera's own HDL language) compared with Verilog or VHDL? > > AHDL only works for Altera hardware. I will avoid using proprietary language > like that. It makes your design not portable. You can't migrate your design > to Xilinx or ASIC. Why not join the masses by using either Verilog or VHDL? > > Hendra > >Article: 68155
Hello,
I have been trying to use distributed ram on a Spartan 3. I get an
error from XST with with this simple example from the docs
error:
Analyzing Entity <RAM16x1S> (Architecture <low_level_definition>).
ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default
binding for component: <RAM16X1S>. Generic <INIT> is not on the
entity.
-- This example shows how to create a
-- RAM using xilinx RAM16x1S component.
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VComponents.all;
entity myRAM is
port (
o : out std_logic;
we : in std_logic;
clk : in std_logic;
d : in std_logic;
a0,a1,a2,a3 : in std_logic
);
end myRAM;
architecture xilinx of myRAM is
component RAM16x1S is
generic (INIT : string := "0000");
port (
O : out std_logic;
D : in std_logic;
A3, A2, A1, A0 : in std_logic;
WE, WCLK : in std_logic
);
end component;
begin
U0 : RAM16x1S
generic map (INIT => "FFFF")
port map (O => o, WE => we, WCLK => clk, D => d,
A0 => a0, A1 => a1, A2 => a2, A3 => a3);
end xilinx;
--------------------------------------------------------------------
Am I missing something?
Thanks
Patrick
Article: 68156"John_H" <johnhandwork@mail.com> escribió en el mensaje news:BUY8c.22$V4.337@news-west.eli.net... > "paris" <malaka@email.it> wrote in message > news:c3vtbb$1n1a$1@avanie.enst.fr... > > well i cant go into deep math details to prove it cause as i said, i did > > that a long time ago, and im sure you can find the maths in the internet, > > like in the link i posted (ok, the link is not so detailed, but it was one > > of the first results of google) > > [enormous snip] > > I was trying to point out that your approach was fundamentally flawed. I > was hoping that - when looking to answer me - you'd realize that the duty > cycle is formed with even harmonics of the 500MHz signal in addition to the > center frequency and odd harmonics typically associated with clocks. The > baseband that's mixed back down to 50 MHz will contain phase, amplitude, and > frequency variations of the center frequency translated to the 50MHz; > unfortunately, the duty cycle is none of these factors. Duty cycle > modulation (without considering a fixed duty cycle) will show up mostly as > modulation of the harmonics, not as modulation of the 500 MHz "carrier." > The 1000 MHz second harmonic will not translate to 100 MHz. The 1500 MHz > third harmonic will not translate to 150 MHz. > yes you're right, thanks for pointing out the mistake. > The analog techniques that can deal with duty cycle measurement could > include 1) a charge pump with the imbalance in the current source and sink > controlled to reach equilibrium - the imbalance gives a measure of the duty > cycle and can be matched with the same imbalance on the regenerated clock, > and 2) detection of phase crossing with I/Q sampling of the center signal > allowing the phase of the clock edges to be determined relative to a > sinusoid reference (the filtered 1st harmonic from the clock). The DC > levels from the two clocks were suggested by others and is similar to the > charge pump idea with errors introduced by the very fast 500 MHz input > clock. The I/Q method can deliver accurate results to some pretty high > frequencies. > >Article: 68157
Hi, > I have to develop a big FPGA core, organized like in the figure below. > There is a big synchronous system working with the 40MHz clock. > However there is also a subsystem which uses the big combinational > network with propagation time ca. 75 ns. (It is almost impossible > to assure efficient pipelining in this network :-( ). > It is not a problem because the Reg.1 and Reg.2 register are > enabled only every fourth clock pulse, so I have 100ns to propagate > the data through the Comb.1 subsystem. for Xilinx devices, one solution to your problem is to create timing constraints in a .ucf file to specify the maximum acceptable propagation delay between reg1 and reg2. As an example: NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 25 ns HIGH 50 %; NET "reg1<*>" TNM_NET = "reg1"; NET "reg2<*>" TNM_NET = "reg2"; TIMESPEC "TS_reg1_to_reg2" = FROM "reg1" TO "reg2" "TS_clk" * 4; This kind of constraints are easily created using the "Xilinx Constraints Editor" in the ISE tool chain. Regards, Laurent FoubeArticle: 68158
I'm not sure exactly what is wrong in this case but I really recommend inferring the RAM in your source code. You can probably find an example by looking up "inferring ram" in your synthesizer help files. Your problem here might be that you need to include a different library for synthesis. The "unisim" library is normally only for simulation. -Kevin "Patrick Robin" <circaeng@hotmail.com> wrote in message news:1c77d44b.0403272022.24c1a7e@posting.google.com... > Hello, > > I have been trying to use distributed ram on a Spartan 3. I get an > error from XST with with this simple example from the docs > > error: > > Analyzing Entity <RAM16x1S> (Architecture <low_level_definition>). > ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default > binding for component: <RAM16X1S>. Generic <INIT> is not on the > entity. > > > > -- This example shows how to create a > -- RAM using xilinx RAM16x1S component. > library IEEE; > use IEEE.std_logic_1164.all; > > library UNISIM; > use UNISIM.VComponents.all; > > entity myRAM is > port ( > o : out std_logic; > we : in std_logic; > clk : in std_logic; > d : in std_logic; > a0,a1,a2,a3 : in std_logic > ); > end myRAM; > architecture xilinx of myRAM is > component RAM16x1S is > generic (INIT : string := "0000"); > port ( > O : out std_logic; > D : in std_logic; > A3, A2, A1, A0 : in std_logic; > WE, WCLK : in std_logic > ); > end component; > begin > U0 : RAM16x1S > generic map (INIT => "FFFF") > port map (O => o, WE => we, WCLK => clk, D => d, > A0 => a0, A1 => a1, A2 => a2, A3 => a3); > > end xilinx; > > -------------------------------------------------------------------- > > > Am I missing something? > > Thanks > > PatrickArticle: 68159
I had a "similar" problem once with a different core. I was just wanting to test the core and so I was just mapping the core's input and outputs to a I/O pin and nothing else. I couldn't get it to synthesize even with an exact replica of the example code. The problem was that I needed to at least use some dummy logic in between even if I didn't need it (I'm not just guessing, I was told this by the tech. support people of my FPGA vendor). So, I'm not sure if your case is the same in that you are not using any more logic than the core itself, if it is maybe try mapping the outputs of your RAM to some other dummy logic. Good luck. It basically was that I needed to at least use circaeng@hotmail.com (Patrick Robin) wrote in message news:<1c77d44b.0403272022.24c1a7e@posting.google.com>... > Hello, > > I have been trying to use distributed ram on a Spartan 3. I get an > error from XST with with this simple example from the docs > > error: > > Analyzing Entity <RAM16x1S> (Architecture <low_level_definition>). > ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default > binding for component: <RAM16X1S>. Generic <INIT> is not on the > entity. >Article: 68160
you are missing an attribute command you the following after architecture and before begin stmt. attribute INIT : string; attribute INIT of U0 : label is "0001"; bye RamArticle: 68161
Patrick Robin wrote: > I have been trying to use distributed ram on a Spartan 3. I get an > error from XST with with this simple example from the docs > ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default > binding for component: <RAM16X1S>. Generic <INIT> is not on the > entity. > Am I missing something? Perhaps the meaning of the error message. To get a default binding, the component and library entity must have not only the same name, but matching ports and generics. Try commenting out the generic maps. I agree with Kevin, that inferring this ram would be much less trouble. -- Mike TreselerArticle: 68162
Hi All, I'm working on the design which needs to be implemented in radiation tolerant Actel chips. Unfortunately I have only remote access to the machine with the Actel Designer installed, so it is painfully slow. Is it possible to compile the design from the command line? Where can I find info about using the Actel tools from CLI instead of GUI? -- TIA & Regards, Wojtek ZabolotnyArticle: 68163
> If you already are > familiar with C, then learning Verilog will go much faster. C is a procedural language, while Verilog is a hardware description language. They are utterly different things, and while syntactic analogies may be comforting, they may also cause novice hardware designers to make the fatal error of thinking "hey cool, this is just like C"... but fundamentally it's absolutely nothing like C! In transitioning from software design to hardware design, it is the semantic differences that are really important (sequential program code vs hardware description). Syntax is just the means to express it. Obscuring that fact is not going to be helpful in the long run. The point has already been made that a good designer could be productive in any number of ways. But that's not what the original poster was talking about... Regards, JohnArticle: 68164
On 27 Mar 2004 18:44:47 -0800, johnjakson@yahoo.com (john jakson) wrote: >petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0403271536.76667f34@posting.google.com>... >> > 2. Remember the infamous Verilog vs. VHDL competition that Cooley did >> > a few years back? See this link: >> > <http://www.deepchip.com/items/snug99-42.html> >> > In this contest, not a single VHDL contestant was able to finish the >> > problem. Not one. >> > >> >> That's the most presuasive reason I've seen for using Verilog! >> Although I'd like to see an equal number of contestants in both >> languages. >> >> If they redo this contest with a similar outcome, it will definitely >> be time for me to learn Verilog! >> >> -- Pete > >The contest was so trivial that it was really more like a gaming event >for quick responses. It was a counter that counts up by 3 or down by 5 >plus 1 or 2 other details. Nobody seemed to notice that any competant >EE should be able to do that in TTL schematic in 5mins on back of >envelope. They had 2hrs I think. > >The VHDL guys were more plagued with SW and lib setup issues than not >being able to do the design. The Verilog guys had less stuff to get in >the way. It only took me a few minutes to complete the task (in VHDL AND Verilog, with no significant difference between them except for the XOR reduce operator in Verilog). I wondered why so many "experts" couldn't do it in two hours. Then I read the fine print: they had to use unfamiliar tools and an unfamiliar target. I also found it amusing that one of the Verilog solutions was functionally incorrect, yet was still counted as "successful". Regards, Allan.Article: 68165
On Sat, 27 Mar 2004 14:35:09 GMT, Jan Panteltje <pNaonSptaemltje@yahoo.com> wrote: >On a sunny day (Sat, 27 Mar 2004 07:07:03 +0000 (UTC)) it happened Larry >Doolittle <ldoolitt@recycle.lbl.gov> wrote in ><slrnc6aa0m.7c9.ldoolitt@recycle.lbl.gov>: > >>In article <smt9609qub8etdrak9ajkvij0nukmljheg@4ax.com>, Phil Hays wrote: >>> (tbiggs) wrote: >> >>I am also enamored with Icarus Verilog for system simulation, >>and I know of no comparable quality libre tool for VHDL. > >Yes I use Iverilog too, it is fast, clean, and Linux command line. Fast? It was about ten times slower than Modelsim, the last time I ran a benchmark. I notice you didn't mention "correct". For me, correctness is the most important attribute of a simulator. Regards, Allan.Article: 68166
On 27 Mar 2004 15:25:22 -0800, petersommerfeld@hotmail.com (Peter Sommerfeld) wrote: >> What is the user base really at? Based on newsgroup >> traffic (comp.lang.vhdl vs. comp.lang.verilog), >> VHDL usage is 2X that of Verilog. > >Twice the traffic at comp.lang.vhdl is not a meaningful statistic. It >could be that VHDL users require twice as much help sythesizing their >designs. c.l.vhdl has many more newbie questions, indicating (IMO) that VHDL is used more in schools. Take out the newbie posts, and both c.l.vhdl and c.l.verilog have very little real traffic. For me, one of the significant differences between those two newsgroups is the answer to the FAQ "why does my tool do this?" c.l.vhdl, the answer is "The LRM says /this/. Your tool is correct / incorrect." c.l.verilog, the answer is "The LRM says /this/. Tool1 does /that/, tool2 does /something else/, tool3 does /something else again/." This is a consequence of the history of the two languages. VHDL was standardised early, and Verilog was standardised late in its development. Regards, Allan.Article: 68167
On 26 Mar 2004 09:00:05 -0800, spanchag@yahoo.com (spanchag) wrote: >Hi everybody, > >A quick question on implementing deserialization logic in Xilinx and >Altera. >I know Altera has SERDES circuitry built in their Stratix devices >where the max factor is 10. Xilinx doesn't have dedicated circuitry. > >Has anybody used Altera for deserialization with a factor more than 10 >using logic cells ? If so at what speed were using it ? How well does >it work ? > >What about Xilinx ? Any help appreciated here. Try XAPP622. I have a similar design working at 622Mbps per pin in a Xilinx FPGA in my current design. Regards, Allan.Article: 68168
After trying everything I could think of including all suggestions in this thread, it still didn't work. Then I decided to try RAM32X1S, that worked fine, then I tried RAM64X1S, that worked fine also. So I don't know why RAM16X1S won't synthesis properly when taken straight from the Xilinx example vhdl files and Xilinx app note 464. I won't research this further since ultimately, what I need is RAM64X1S . Initially, I tried RAM16X1S to start small and work my way up. Thanks for all suggestions. Patrick mike_treseler <mike_treseler@comcast.net> wrote in message news:<jNSdnYFqD-oXsPrdRVn-gw@comcast.com>... > Patrick Robin wrote: > > > I have been trying to use distributed ram on a Spartan 3. I get an > > error from XST with with this simple example from the docs > > > ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default > > binding for component: <RAM16X1S>. Generic <INIT> is not on the > > entity. > > > Am I missing something? > > Perhaps the meaning of the error message. > To get a default binding, > the component and library entity > must have not only the same name, but matching > ports and generics. Try commenting out the > generic maps. > > I agree with Kevin, that inferring this ram > would be much less trouble. > > -- Mike TreselerArticle: 68169
Hi all, I am trying to apply timing constraints in my UCF file for a Xilinx RPM design. My design contains a logic cloud (all non-synchronous elements) and the output is being registered. I have turned off I/O pad generation in XST sysnthesis options. Now I want to constraint the path from logic cloud input to the ffs using the FROM TO timing constraints. I am using the TPSYNC grouping constraint to group the input bus and TNM to group the ffs. NET "A*" TPSYNC = "group1"; INST "N*" TNM = "group2"; TIMESPEC "TS01" = FROM group1 TO group2 4 ns; This does not work and I get the following warning messages: WARNING:XdmHelpers:849 - No valid pins were found for TPSYNC property on signal "A<4>". A signal must have a valid driver in order for a TPSYNC propert to be used. As a result the translate process fails since my FROM TO constraint does not find a valid starting group. How do I go about constraining a design like this ? Thanks JoshArticle: 68170
Somebody sent me an email about this issue but unfortunately yahoo placed the email in the bulk mailbox and I hit 'empty' at the same time I glanced the email titles. Please send me email again if it is important. Thank you. vax,3900 wrote: > I am using a CPLD(XC95144) in my board and since it is my first time to > play CPLD, I have the question when to assign pins. The CPLD will have a > 22 bit parallelly loadable counter and two state machines. I need to know > when is the right time to assign pins. Do I assign pins after the content > is designed and tested, or before? How flexible are CPLDs about assigning > pins? Thank you. > > vax, 3900Article: 68171
Jeff_n_Moz Hint: You have _two_ counters. One is a synchronous loadable counter. But where does it get its load value from ? Do you intend to build a working model ? If so, what device are you targeting ? And for my own curiosity, which college are you at ? Regards, -rajeev- ---------------- pllproject@yahoo.com (jeff_n_moz) wrote in message news:<90a9c67c.0403260927.5e07bfaa@posting.google.com>... > hi there, > > we are final year engineering students from india. we are currently > working on a fpga project and are stuck at a counter design. if any of > you could help us out, it would be great. > > we have to design an increment decrement counter. it is more of a > divider though. the ports are as follws: > input: inc,dec,clock,reset > output: f0 > > the counter is synchronous with an asynchronous reset.it should start > from producing a pulse for every 8 input clock pulses. it has 2 other > inputs, "inc" and "dec". on recieving a pulse at the inc port, on the > falling edge of pulse, it should start producing higher frequency, ie > divide by lesser.similiarly on reciving a pulse at the dec port, it > should decrement output frequency, i.e. increase the limit for count. > the highest frequency divide should be 16 and lowest as 1. > > we have been trying to get this done using VHDL, but have run into > multiple driver problem etc. we are unfamiliar with verilog but are > now learning it. > if any of you could spare some time for us, please mail us at the > above address with any sugestions or code(either VHDL or verilog). > > we thank all for their interest.Article: 68172
In article <n3re60dh0tg7hkms19vi78un1tlbs7ogqj@4ax.com>, Allan Herriman wrote:
> On Sat, 27 Mar 2004 14:35:09 GMT, Jan Panteltje
><pNaonSptaemltje@yahoo.com> wrote:
>
>>On a sunny day (Sat, 27 Mar 2004 07:07:03 +0000 (UTC)) it happened Larry
>>Doolittle <ldoolitt@recycle.lbl.gov> wrote in
>><slrnc6aa0m.7c9.ldoolitt@recycle.lbl.gov>:
>>
>>>In article <smt9609qub8etdrak9ajkvij0nukmljheg@4ax.com>, Phil Hays wrote:
>>>> (tbiggs) wrote:
>>>
>>>I am also enamored with Icarus Verilog for system simulation,
>>>and I know of no comparable quality libre tool for VHDL.
>>
>>Yes I use Iverilog too, it is fast, clean, and Linux command line.
>
> Fast? It was about ten times slower than Modelsim, the last time I
> ran a benchmark.
I only recently got to try Modelsim, and yes it appears faster
than Icarus Verilog. When I can recompile Modelsim from sources
for all my present and future computers without paying a license
fee, I'll consider it for mainstream use.
> I notice you didn't mention "correct". For me, correctness is the
> most important attribute of a simulator.
I agree. While I am not a language lawyer, and my usage probably
passes for simple, I haven't seen any incorrect answers from Icarus
for a long time.
If anyone notices an incorrect result from Icarus,
it normally goes into the (published) test suite.
The bug database for Icarus is unfortunately polluted with
historical, incorrect, or irreproducible bug reports.
If anyone has time to volunteer to sift through them for
real bugs, I'm sure Steve would be happy to accept the help.
- Larry
Article: 68173Hello Group! Has anybody else had problems with getting C++ Runtime Errors, when trying to navigate within the RTL Viewer in the ISE6.2i WebPack under Windows XP...? The errors seem to relate to the "mfc42.dll" file. In the ISE5.xx versions, special folders for holding copies of such types of files for XP and Win2K resided under the Xilinx installation directory itself in \.xinstall\config\redist\... But no such folder tree exist anymore, so I believe that ISE6.2i relies on the already installed versions, and that might be the problem, if those are too old... Other clues, please...? Thanks in advance and best regards, Jesper Kristensen.Article: 68174
Hi Przemek, > I realize now what you were doing wrong. In the command line help for > logiclock back-annotate it says: > > "-routing: Back-annotate the LogicLock region's routing. Must use > -lock, -no_demote_lab. Must not use -no_contents" > > So when you want to back annotate routing, you should type: > > logiclock_back_annotate -routing -lock -no_demote_lab -region > my_region_name Yes! That finally worked and now I have an .rcf file. So the basic problem before was I hadn't any on-line help on the logiclock_back_annotate command... So, I believe now I have a fairly good starting point with the TCL logiclock flow. When I consolidate it, I will post the final complete scripts so that others might find it useful. So long and thanks for all the help, Spyros > Now for your question about export. Yes export generally does very > little to the ESF. However, in cases where the project has multiple > ESFs then export will merge them all into one. However, export does > make significant changes to the RCF. The exported RCF is different > from the back annotated RCF. The back annotated one is suitable in a > flow where you are trying to preserve routing within a project. While > the exported RCF is more suitable to an export/import flow. The > differences are due to VQMs and routing to and from IO pins. > > Unfortunately, there is not specific TCL guide to using LogicLock. I > would recommend: > > 1) read the handbook. (I believe you said you already did) > 2) go to www.altera.com and search for TCL. There are some general > TCL guides here but nothing specific to LogicLock > 3) quartus_sh --qhelp is the official help. > > The TCL interface is geared towards the advanced user, so the help is > really meant for the GUI user. > > Please continue asking questions here in the newsgroup, and I will try > to answer them for you. > > Thanks > > > Przemek Guzy > Altera Corp.
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