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Messages from 68600

Article: 68600
Subject: Re: Problem using EDK tutorial for Memec board with Synplicity.
From: Paulo Dutra <paulo.dutra@xilinx.com>
Date: Thu, 08 Apr 2004 19:44:42 -0700
Links: << >>  << T >>  << A >>
For user IPs, there are multiple ways you can
achieve this as part of XPS flow.

1. Pre-synthesize the IP using 3rd party synthesis tool
and import it as a black-box module (use MPD+BBD) in EDK.

2. User Export-To-ProjNav flow. Do not synthesize the IP.
XPS will add the HDL files related to the IP to your projnav
project. You can synthesize 3rd party synthesis tool in
ProjNav, run ISE implementation tools and import back
the bitstream

3. Use XPS's user makefile feature. Do not synthesize the
IP, but mark it as IMP_NETILST=FALSE. PlatGen will create
a wrapper HDL for user IP, but will not synthesize it.
In XPS--> Project Options, specify a user make file to be
used -- say mymakefile.make. Copy XPS generated system.make
into mymakefile.make. Create a file, say mysynthesis.sh.
Make a call to the batch mode of your favorite synthesis
tool to synthesize user IP. In the target where XPS calls
synthesis.sh, replace it with mysynthesis.sh.

4. Send email to hotline@xilinx.com for assistance

Brijesh wrote:
> Was going through the Documentation. Buried deep within I found this
> 
> "Currently, Platform Generator only supports XST (Xilinx Synthesis 
> Technology)."
> 
> Guess Iam stuck. Unless there is a tutorial that does not use the 
> Platform Generator. Is there a way to change the Synthesis tool option 
> once the project is generated using the Platform Generator.
> 
> Or more basic question does EDK support Synplicity at all?
> 
> Thanks
> brijesh
> 
> 
> Brijesh wrote:
> 
>> Hi,
>>
>> My set up is
>> EDK 6.1
>> ISE 6.1 (no XST)
>> Synplicity
>> Memic VitexII Pro Dev board P4 FG 456
>>
>> The tutorial expects you to use Xilinx synthesis tool XST. During 
>> initial XPS wizard didnt give me an option to choose the synthesis 
>> tool.  The Drop down menu had only one option "None".
>>
>> I went ahead with the steps and managed to export the project to ISE 
>> project Navigator. Had to manually add the system.vhd and other files.
>> Then I had the following problems.
>>
>> 1) The bus format in the UCF files had to be changed from <> to ().
>> 2) Got stuck with this error messages
>>
>> ERROR:NgdBuild:704 - The BRAM instance
>>    'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0' 
>> could not be found in the netlist. Please verify the instance name in 
>> the BMM file and the netlist.
>>
>> ERROR:NgdBuild:604 - logical block 'system_dcm' with type 
>> 'system_dcm_wrapper' could not be resolved. A pin name misspelling can 
>> cause this, a missing edif or ngc file, or the misspelling of a type 
>> name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.
>>
>> The "synthesis" folder does have the file 
>> "system_dcm_wrapper_xst.srp". I guess the last _xst is for XST 
>> specific. Do I just rename the file? or  how do I move ahead with the 
>> tutorial using Synplicity for my synthesis.
>>
>> Any clues on how to proceed would be appreciated.
>> Thanks
>> brijesh


-- 
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
/ /    2100 Logic Drive                    http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA


Article: 68601
Subject: Re: Problem using EDK tutorial for Memec board with Synplicity.
From: Ken McElvain <ken@synplicity.com>
Date: Fri, 09 Apr 2004 04:31:16 GMT
Links: << >>  << T >>  << A >>

Look up "syn_edif_bit_format" in the Synplicity help file.  It will
tell you how to match the <> in your UCF files.

There is also a Xilinx program that will generate the interface files
needed by EDK.  Basically, EDK needs an extra file describing the
ports and generics of a "peripheral".  This file is generated from
the top level verilog module or VHDL entity of your peripheral.
I don't remember the name of the program, but I will ask around.

- Ken McElvain


Brijesh wrote:

> Was going through the Documentation. Buried deep within I found this
> 
> "Currently, Platform Generator only supports XST (Xilinx Synthesis 
> Technology)."
> 
> Guess Iam stuck. Unless there is a tutorial that does not use the 
> Platform Generator. Is there a way to change the Synthesis tool option 
> once the project is generated using the Platform Generator.
> 
> Or more basic question does EDK support Synplicity at all?
> 
> Thanks
> brijesh
> 
> 
> Brijesh wrote:
> 
>> Hi,
>>
>> My set up is
>> EDK 6.1
>> ISE 6.1 (no XST)
>> Synplicity
>> Memic VitexII Pro Dev board P4 FG 456
>>
>> The tutorial expects you to use Xilinx synthesis tool XST. During 
>> initial XPS wizard didnt give me an option to choose the synthesis 
>> tool.  The Drop down menu had only one option "None".
>>
>> I went ahead with the steps and managed to export the project to ISE 
>> project Navigator. Had to manually add the system.vhd and other files.
>> Then I had the following problems.
>>
>> 1) The bus format in the UCF files had to be changed from <> to ().
>> 2) Got stuck with this error messages
>>
>> ERROR:NgdBuild:704 - The BRAM instance
>>    'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0' 
>> could not be found in the netlist. Please verify the instance name in 
>> the BMM file and the netlist.
>>
>> ERROR:NgdBuild:604 - logical block 'system_dcm' with type 
>> 'system_dcm_wrapper' could not be resolved. A pin name misspelling can 
>> cause this, a missing edif or ngc file, or the misspelling of a type 
>> name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.
>>
>> The "synthesis" folder does have the file 
>> "system_dcm_wrapper_xst.srp". I guess the last _xst is for XST 
>> specific. Do I just rename the file? or  how do I move ahead with the 
>> tutorial using Synplicity for my synthesis.
>>
>> Any clues on how to proceed would be appreciated.
>> Thanks
>> brijesh


Article: 68602
Subject: Unsupported feature error:access type is not supported
From: neetu_garge@yahoo.com (NEETU GARG)
Date: 9 Apr 2004 01:46:13 -0700
Links: << >>  << T >>  << A >>
hello;
i m trying to run this vhdl code for reading .cmd file...while i m
trying to compile the code on the altera's max plusII software(student
software),it is showing error
File d:\maxw\code\93vhdllib\std\textio.vhd:Unsupported feature
error:access type is not supported
in d drive, i m not installing that software, i have this software
installed in c drive.....
can somebody can help me in this matter....please reply soon.....
-- -------------------------------------
--   Reads std_logic values from a file 
-- -------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use work.txt_util.all;


entity FILE_READ is
  generic (
           stim_file:       string  := "sim.cmd"
          );
  port(
       CLK              : in  std_logic;
       RST              : in  std_logic;
       Y                : out std_logic_vector(4 downto 0);
       EOG              : out std_logic
      );
end FILE_READ;

 
-- I/O Dictionary
--
-- Inputs:
--
-- CLK:              new cell needed
-- RST:              reset signal, wait with reading till reset seq
complete
--   
-- Outputs:
--
-- Y:                Output vector
-- EOG:              End Of Generation, all lines have been read from
the file
--
   
   
architecture read_from_file of FILE_READ is
  
  
    file stimulus: TEXT open read_mode is stim_file;


begin



-- read data and control information from a file

receive_data: process

variable l: line;
variable s: string(y'range);
   
begin                                       

   EOG <= '0';
   
   -- wait for Reset to complete
   wait until RST='1';
   wait until RST='0';

   
   while not endfile(stimulus) loop

     -- read digital data from input file
     readline(stimulus, l);
     read(l, s);
  --   Y <= to_std_logic_vector(s);
     
     wait until CLK = '1';

   end loop;
   
  -- print("I@FILE_READ: reached end of "& stim_file);
   EOG <= '1';
   
   wait;

 end process receive_data;



end read_from_file;

Article: 68603
Subject: I2C bus and tristate interface for V2pro
From: Mancini Stephane <nospam@nospam.nospam>
Date: Fri, 09 Apr 2004 12:25:15 +0200
Links: << >>  << T >>  << A >>
Hi everybody,
I've just downloaded the i2c controller from opencores.org and I was
wondering how to use it within my system.
Indeed, I've a xilinx V2PRO connected to a video encoder SAA7127 to be
configured thru an i2c interface.
Can I directly connect the I2C interface of the SAA7127 and declare a
tristate I/O pad on the V2Pro, being connected internally to the i2c core
? 
Thanks a lot for your help

Stphane

Article: 68604
Subject: Spartan-3 LC Development Kit from Insight with USB 2.0 Port
From: Dave <postmaster@localhost>
Date: Fri, 09 Apr 2004 20:03:46 +0930
Links: << >>  << T >>  << A >>

In January there was a discussion about the Spartan-3 LC kit from Memec.
(http://www.memec.com/Memec/iplanet/link1/Spartan3LC_3.pdf)
I'm wondering if anyone has purchased the kit and has any comments?

In particular Im interested in the USB 2.0 Interface. We are
speculating that it uses a USB2.0 High Speed transceiver and hence
requires a USB2.0 SIE core to be implemented in the Spartan. Is this a
correct assumption? Does anyone know what percentage of the device does
the USB 2.0 High Speed SIE core use?

We are weighting it up with other boards which has an onboard Cypress
EZ-USB FX2 2.0 Full Speed USB Controller and hence once 
configured/enumerated we can just clock the data into this device and it 
can deal with in leaving the Spartan III for other things.





Article: 68605
Subject: regardinng static timing annalysis
From: prasadkdnvs@rediffmail.com (K PRASAD)
Date: 9 Apr 2004 03:46:16 -0700
Links: << >>  << T >>  << A >>
hi 

Can any body explain me abt the static timing analysis
clearly what is the inndustry standard tools for that 
what is the input to STA tool and what is the output.

thank u

regards
prasad

Article: 68606
Subject: Re: XAPP662 readframe and writeframe functions.
From: "tk" <tokwok@hotmail.com>
Date: Fri, 9 Apr 2004 19:38:36 +0800
Links: << >>  << T >>  << A >>
I think it's hard to help if you just describe what you get without telling
the detail of
what you do .....

tk

"Jonathan Debrouwere" <jdebrouw@student.fsa.ucl.ac.be> glsD
:c5353g$4m8$1@ail.sri.ucl.ac.be...
> Hi,
>
>
>
> I have problem using the XAPP662 readframe and writeframe functions.
>
>
>
> First I read a frame, then I write some byte of the frame and after I read
> it again to see the change.
>
> The problem is that when I try to write the frame, there is only the pad
> frame that get updated, the data frame is not modified and I don't
> understant why.
>
>
>
> Thanks in advance.
>
>
>
> Jonathan
>
>



Article: 68607
Subject: Re: Problem using EDK tutorial for Memec board with Synplicity.
From: Brijesh <brijesh_xyz@cfrsi.com>
Date: Fri, 09 Apr 2004 09:58:20 -0400
Links: << >>  << T >>  << A >>
Paulo and Ken,
Thanks for the reply.

This was first time I even fired up the EDK application. To keep things 
simple I installed evaluation version of the XST and finished the tutorial.
I will look into your suggested flow, once I get comfortable with the 
design flow and figure out some more things.

This is for information if anybody else if trying out the tutorial.
I did observe one more thing, the P&R reported had 4 errors.

--------------------------------------------------------------------------------
* PERIOD analysis for net "system_dcm/syste | 10.000ns   | 13.255ns   |0
   m_dcm/CLK0_BUF" derived from  NET "bufgp_ |            |            | 

   83/IBUFG" PERIOD =  10 nS   HIGH 50.00000 |            |            | 

   0 %                                       |            |            | 

--------------------------------------------------------------------------------
* PERIOD analysis for net "system_dcm/syste | 3.333ns    | 4.282ns    |0
   m_dcm/CLKFX_BUF" derived from  NET "bufgp |            |            | 

   _83/IBUFG" PERIOD =  10 nS   HIGH 50.0000 |            |            | 

   00 %                                      |            |            | 

--------------------------------------------------------------------------------

I just went ahead and tried it out inspite of this one. It seemed to 
work, I did get required output on the terminal screen.

Thanks again.

Brijesh wrote:

> Hi,
> 
> My set up is
> EDK 6.1
> ISE 6.1 (no XST)
> Synplicity
> Memic VitexII Pro Dev board P4 FG 456
> 
> The tutorial expects you to use Xilinx synthesis tool XST. During 
> initial XPS wizard didnt give me an option to choose the synthesis tool. 
>  The Drop down menu had only one option "None".
> 
> I went ahead with the steps and managed to export the project to ISE 
> project Navigator. Had to manually add the system.vhd and other files.
> Then I had the following problems.
> 
> 1) The bus format in the UCF files had to be changed from <> to ().
> 2) Got stuck with this error messages
> 
> ERROR:NgdBuild:704 - The BRAM instance
>    'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0' 
> could not be found in the netlist. Please verify the instance name in 
> the BMM file and the netlist.
> 
> ERROR:NgdBuild:604 - logical block 'system_dcm' with type 
> 'system_dcm_wrapper' could not be resolved. A pin name misspelling can 
> cause this, a missing edif or ngc file, or the misspelling of a type 
> name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.
> 
> The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp". 
> I guess the last _xst is for XST specific. Do I just rename the file? or 
>  how do I move ahead with the tutorial using Synplicity for my synthesis.
> 
> Any clues on how to proceed would be appreciated.
> Thanks
> brijesh

Article: 68608
Subject: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
From: qlyus@yahoo.com (qlyus)
Date: 9 Apr 2004 09:45:19 -0700
Links: << >>  << T >>  << A >>
It is a Multirate application.  The data is coming directly from an
ADC chip running at over 1GHz sampling rate, 4x upsampled, then pass
through multiple stages of FIR filters to have various rates in
output.  Because of the data rate, we have to build multiple filters
in parallel.  190 multipliers are used for only 8 93-tap filers in
parallel in one stage.

I tested one of the designs in ISE 6.2.  It was just one stage block
of such filtering, flip-flops for data pipeline, multipliers,
pipelined adders.  ISE started in edif file without timing and LOC
constraints.  The design had a single clock domain.  The PAR in 6.2
took a half to one hour to finish.

ISE 6.1 ran only about 5 minutes, even with 150MHz clock constrained.

Anyway, I stay with ISE 6.1 until 6.2 sp#2 comes out to try.

May I ask you a question not related to this topic, Austin?  Some of
the LVCMOS25 inputs in Virtex-II Pro are driven by 3.3V LVTTL signals
from other devices.  We have noticed that the clamp diodes in these
LVCMOS25 inputs are activated and the voltage levels have ramp started
at ~2.7V and are clamped at 3.0V.  It seems these 3.3V drivers are not
strong ones (like line driver with +/- 24mA capability) since their
datasheeds specify Voh/Vol only at Io=0.5mA or so.  But we have no way
to figure out how much the exact current is driving into the diodes. 
Are these inputs of Virtex-II Pro safe in a long time?  Thanks.

-qlyus


Austin Lesea <austin@xilinx.com> wrote in message news:<c54bpi$d5t2@cliff.xsj.xilinx.com>...
> qlyus,
> 
> If you get such a degraded performance result, you should open a case. 
> That is an indication that something is not right.  Either your style is 
>   using the wrong features, or the software is.  We certainly like to know.
> 
> Any individual design can easily vary 2:1 in performance on either 
> toolset, so just as one error does not define a rate, one result does 
> not define performance.
> 
> Just curious, what do you use 190 multipliers for, and what is the 
> market for that?
> 
> Austin
> 
> qlyus wrote:
> 
> > I agreed.  I was in Altera web seminar.  I asked "Stratix is only
> > comparable to Virtex-II, not -Pro" and did not get answer.
> > 
> > I do not have comments on the performance comparison materials.  But
> > my designs required 190 16x16 multipiliers in each of three FPGAs in a
> > row.  Stratix had no way to do it.  Stratix-II, too later.
> > 
> > I really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70%
> > over 4.x ..... were jokes.  I was seeing -1000% 6.2 over 6.1.
> > 
> > -qlyus
> > 
> > 
> > Austin Lesea <austin@xilinx.com> wrote in message news:<c51n66$d5r1@cliff.xsj.xilinx.com>...
> > 
> >>Sander,
> >>
> >>I apologize if I have offended.  Just wanted to be sure to balance the 
> >>scales.
> >>
> >>Austin

Article: 68609
Subject: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
From: Steve Lass <lass@xilinx.com>
Date: Fri, 09 Apr 2004 10:57:54 -0600
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

>I sometimes see small gains for 6.2 if the design has one clock domain.  For designs with
>multiple clock domains however, I have been having considerable difficulty meeting timing on all
>the clock domains on designs that met timing without trouble under 5.2, even with the effort
>level cranked up on 6.2.   Apparently, the software is now focusing on what it figures to be the
>clock domain with the tightest timing and failing the others as a result.
>
The place and route tools work with timing paths and don't distinguish 
between whether they are in the same clock domain or not.
Minimizing clock skew could have an effect on timing within a clock 
domain and could possibly make timing between domains
worse, but we'd have to look at the design to see if that's the case here.

>  Time to compile means
>nothing if the result is garbage.
>
>qlyus wrote:
>
>  
>
>>I really think Xilinx's claims ISE 6.2 40% over 6.1
>>
We never said that.  6.2i results are an average of 2% faster than 
6.1i.  The 40% was V2Pro over Stratix.

>> 50% over 5.2 70%
>>over 4.x ..... were jokes.
>>
I'm not sure where these numbers came from.  Usually, we get around a 
15% average increase each year.
Sometimes we also report a number like "map -timing can get you up to 
40% better results".  In this case,
map -timing doesn't help much unless the design is full and packing 
unrelated logic, so reporting an average
would be less useful.

>>  I was seeing -1000% 6.2 over 6.1.
>>
We ran hundreds of designs on 6.2i and never saw anything worse than 
-5%.  Please send the design
to our hotline and we'll take a look at it.

Steve

>>
>>    
>>
>
>--
>--Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email ray@andraka.com
>http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
>  temporary safety deserve neither liberty nor safety."
>                                          -Benjamin Franklin, 1759
>
>
>  
>


Article: 68610
Subject: Re: how to get XST to infer 8:1 mux or just hard code it?
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Fri, 09 Apr 2004 17:03:25 GMT
Links: << >>  << T >>  << A >>
Ray,
I'm sure it's a valuable design technique.  I think it just reminded me of
the meta-FPGA which worked in a similar fashion.  Some guy made a meta-FPGA
that sat on top of a Xilinx.  You'd load his meta-FPGA, which had all the
SRLs connected together in a big JTAG-like chain, and then you could program
the meta-FPGA with your own design by loading a serial stream into all the
LUTs.  Some LUTs were used as LUTs and some for routing.  I can't remember
exactly why it was useful except that you could write your own open-source
router, which apparently was an appealing prospect to somebody.
-Kevin

"Ray Andraka" <ray@andraka.com> wrote in message
news:4075E12A.BF19B52@andraka.com...
> Kevin, I presume you meant to say #3, not #2 'sounds a little weird.  #2
is very
> straight forward, and not much different than #1 or #4.  #3 is more like a
poor
> man's reconfiguration of only the LUTs involved.  I suppose you can call
it self
> modifying, but it only modifies specific LUTs with one of 5 specific sets
of
> bits.  The fact is, it gets you a 4:1 mux in one level of LUTs, and it is
> spacewise efficient for word-wide data paths.
>
> Kevin Neilson wrote:
>
> > Ray,
> > OK, I'll grant that in special cases there are other possible
structures.
> > #2 sounds a little weird, like self-modifying code.  Don't forget #5:
one
> > can set the contents of a blockRAM so that the address lines can be used
for
> > mux control and data.
> > -Kevin
> >



Article: 68611
Subject: Re: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Fri, 9 Apr 2004 15:38:30 -0400 (EDT)
Links: << >>  << T >>  << A >>
I think i am having the same problem.  Can someone clarify these
instructions a little more on how to fix this issue.

Thanks

Matt

On Wed, 7 Apr 2004, Peter Ryser wrote:

> You need to add both PPC in your device to JTAGPPC as documented on pg.
> 117ff in the "PowerPC 405 Processor Block Reference Guide".
>
> - Peter
>
>
> qudhs wrote:
> > Hi!
> > I am using a Virtex2PV20, and one PPC core is used in my design.
> > I drag a PPC Jtag controller core into the design in order to debug my
> > SW code. however, I failed to program the device with the generated
> > bitstream. iMPACT reports the DONE pin doesn't go high. In Bitgen, Jtag
> > clock has been explicitly specified. I think the main reason of
> > programming failure is that some wrong options were selected in Bitgen
> > phase due to the fact that I am not familiar with how JTAG works. could
> > someone guide me how to work out the problem?
> > thank you!
> > BRs.
> > --yang
> >
>
>

Article: 68612
Subject: Re: Fatal error mappin 2v1000 in ISE 6.2
From: Davis Moore <davisDOTmoore@UNSpAMxilinx.com>
Date: Fri, 09 Apr 2004 13:01:43 -0700
Links: << >>  << T >>  << A >>
Hi Wolfgang,

There is no immediate method to evaluate the root cause
for a possible workaround. You should open a Hotline case
for this problem.

Regards,
Davis Moore

wolfgang wrote:

> hi!
>
> does anybody know how to handle this error?
>
> it occurred when implementing a design in a 2v1000 -5 with ise 6.2.01i:
>
> ************************************************************************
> Running related packing...
> FATAL_ERROR:Ncd:basncsignal.c:283:1.39.8.2 - Could not find a bel for a
> signal
>    on pin BYOUT of comp
>    i_top_mainpath_i_channelengine_RPF2_INTPOL_BETRAG_i_sctb1_low/BU77/G.S0.
> Its
>    current programmed state is : F:#RAM:D=0x0000 G_ATTR:DUAL_PORT
> DIG_MUX:ALTDIG
>    DIF_MUX:ALTDIF SLICEWE0USED:0 F_ATTR:DUAL_PORT BYOUTUSED:0
> G:#RAM:D=0x0000
>    BYINVOUTUSED:0 SLICEWE1USED:0 WF1USED:0 WF2USED:0 WF3USED:0 WF4USED:0
>    WG1USED:0 WG2USED:0 WG3USED:0 WG4USED:0 BXOUTUSED:0 BXINV:BX CLKINV:CLK
>    SRINV:SR   Process will terminate.  To resolve this error, please consult
> the
>    Answers Database and other online resources at http://support.xilinx.com.
> If
>    you need further assistance, please open a Webcase by clicking on the
>    "WebCase" link at http://support.xilinx.com
>
> Design Summary
> --------------
> Number of errors   :   1
> Number of warnings :  19
> ERROR: MAP failed
> Process "Map" did not complete.
>
> Mapping Module top_shell . . .
> MAP command line:
> map -intstyle ise -p xc2v1000-bg575-5 -cm
> speed -detail -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off -o
> top_shell_map.ncd top_shell.ngd top_shell.pcf
> Mapping Module top_shell: failed
> ************************************************************************
>
> checking the answer database from xilinx support was not very helpful.
>
> kind regards
>
> wolfgang


Article: 68613
Subject: help with constraint, please
From: "Brannon King" <bking@starbridgesystems.com>
Date: 09 Apr 2004 17:18:00 EDT
Links: << >>  << T >>  << A >>
I have below a cut from the twr file for a V2. What constraint do I add to
the UCF file such that the rising edge (of my OFDDRTCPEs) is forced to
happen before 7.5 and the falling edge before 15? ISE seems to get it right
without constraints for faster (-6) chips, but I need it to work right for
my slower (-4) chips as well. Thanks for any help.


Clock N180761_CLKPad to Pad
----------------------+------------+------------------------+--------+
                      | clk (edge) |                        |  Clock |
Destination           | to PAD     |Internal Clock(s)       |  Phase |
----------------------+------------+------------------------+--------+
N260336_OFDDRTCPE     |   10.624(R)|Transport73_pcix_lc_inst|   0.000|
                      |   16.327(F)|Transport73_pcix_lc_inst|   7.500|
N260337_OFDDRTCPE     |   11.003(R)|Transport73_pcix_lc_inst|   0.000|
                      |   16.638(F)|Transport73_pcix_lc_inst|   7.500|
N260586_OFDDRTCPE     |   10.907(R)|Transport73_pcix_lc_inst|   0.000|
                      |   16.599(F)|Transport73_pcix_lc_inst|   7.500|
N260591_OFDDRTCPE     |   11.665(R)|Transport73_pcix_lc_inst|   0.000|
                      |   16.547(F)|Transport73_pcix_lc_inst|   7.500|


You may need to change to a fixed-width font for the chart to line up
correctly.



Article: 68614
Subject: Re: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Fri, 09 Apr 2004 15:29:14 -0700
Links: << >>  << T >>  << A >>
Matthew,

answer record 4582 provides some more information and even design 
examples for different EDK versions. See
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=4582

- Peter


Matthew E Rosenthal wrote:
> I think i am having the same problem.  Can someone clarify these
> instructions a little more on how to fix this issue.
> 
> Thanks
> 
> Matt
> 
> On Wed, 7 Apr 2004, Peter Ryser wrote:
> 
> 
>>You need to add both PPC in your device to JTAGPPC as documented on pg.
>>117ff in the "PowerPC 405 Processor Block Reference Guide".
>>
>>- Peter
>>
>>
>>qudhs wrote:
>>
>>>Hi!
>>>I am using a Virtex2PV20, and one PPC core is used in my design.
>>>I drag a PPC Jtag controller core into the design in order to debug my
>>>SW code. however, I failed to program the device with the generated
>>>bitstream. iMPACT reports the DONE pin doesn't go high. In Bitgen, Jtag
>>>clock has been explicitly specified. I think the main reason of
>>>programming failure is that some wrong options were selected in Bitgen
>>>phase due to the fact that I am not familiar with how JTAG works. could
>>>someone guide me how to work out the problem?
>>>thank you!
>>>BRs.
>>>--yang
>>>
>>
>>


Article: 68615
Subject: Re: Unsupported feature error:access type is not supported
From: "Simon Peacock" <nowhere@to.be.found>
Date: Sat, 10 Apr 2004 12:31:53 +1200
Links: << >>  << T >>  << A >>
The Altera Simulator doesn't support file IO.  Its quite basic in that I
don't believe you can give it a stimulus file either.  All you can give it
is a waveform, all you can get is a waveform.

You might want to consider downloading the free Xilinx Simulator.  It
doesn't know about LPM's but if you stick to VHDL code you get all the
features of a real VHDL simulator.  And a simulation without timings on any
FPGA is the same.

Simon


"NEETU GARG" <neetu_garge@yahoo.com> wrote in message
news:23335919.0404090046.172d1a43@posting.google.com...
> hello;
> i m trying to run this vhdl code for reading .cmd file...while i m
> trying to compile the code on the altera's max plusII software(student
> software),it is showing error
> File d:\maxw\code\93vhdllib\std\textio.vhd:Unsupported feature
> error:access type is not supported
> in d drive, i m not installing that software, i have this software
> installed in c drive.....
> can somebody can help me in this matter....please reply soon.....
> -- -------------------------------------
> --   Reads std_logic values from a file
> -- -------------------------------------
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use std.textio.all;
> use work.txt_util.all;
>
>
> entity FILE_READ is
>   generic (
>            stim_file:       string  := "sim.cmd"
>           );
>   port(
>        CLK              : in  std_logic;
>        RST              : in  std_logic;
>        Y                : out std_logic_vector(4 downto 0);
>        EOG              : out std_logic
>       );
> end FILE_READ;
>
>
> -- I/O Dictionary
> --
> -- Inputs:
> --
> -- CLK:              new cell needed
> -- RST:              reset signal, wait with reading till reset seq
> complete
> -- 
> -- Outputs:
> --
> -- Y:                Output vector
> -- EOG:              End Of Generation, all lines have been read from
> the file
> --
>
>
> architecture read_from_file of FILE_READ is
>
>
>     file stimulus: TEXT open read_mode is stim_file;
>
>
> begin
>
>
>
> -- read data and control information from a file
>
> receive_data: process
>
> variable l: line;
> variable s: string(y'range);
>
>



Article: 68616
Subject: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
From: davidg@altera.com (Dave Greenfield)
Date: 9 Apr 2004 17:35:18 -0700
Links: << >>  << T >>  << A >>
Austin,

To your comment: "Just wanted to be sure to balance the scales."
What exactly were you looking to balance?
The only related post was John Hu's posting that was a completely
technical reply (i.e. no marketing data or performance comparison
whatsoever) to a request for information comparing Virtex II with
Stratix. John also provided a pointer to where the user could get
information if he was interested.
Your post seemed like a bit of a preemptive strike against content in
a net seminar  not information on this site.

And "just can't stand it when others post "PM" so I feel obligated 
to balance it out". 
While I don't know what "PM" means, there was no applicable follow-up
post here whatsoever. Don't confuse a net seminar (where some degree
of marketing is generally acceptable) with a post here.

Altera will respond to technical issues on this newsgroup (ideally
Altera's increased activity over the past 18 months has positively
contributed to this group). We will generally refrain from providing
marketing information here  though we may point requesters to a
location where they can get marketing data. However, we will
selectively respond with marketing information where it is warranted
(i.e. when responding to direct competitive questions, incorrect
information, or competitor's claims).

And this certainly applies to postings from any individual who
consistently uses a cloak of being just a technical person while
regularly dishing marketing data.

Dave Greenfield
Altera Product Marketing


Thanks, I just can't stand it when others post "PM" so I feel
obligated
to balance it out.

I do try to place some really useful and practical bits in the post, 
however.

Austin

Article: 68617
Subject: Does IBUFDS_DIFF_OUT with -DT option exist?
From: qlyus@yahoo.com (qlyus)
Date: 9 Apr 2004 18:01:47 -0700
Links: << >>  << T >>  << A >>
IBUFDS_DIFF_OUT is a differential input clock buffer with differential
outputs.  It is exampled in xapp622 for Virtex-II device.  I would
guess the same primitive exists in Virtex-II Pro.  But I want to use
it with -DT differential terminate.  Does it exist?  if yes, what is
the symbol name and how to use it (if different from the example in
xapp622)?

Thanks.

-qlyus

Article: 68618
Subject: Re: I2C bus and tristate interface for V2pro
From: "Nitro" <nitro-57@no_spam_please_usa.net>
Date: Fri, 09 Apr 2004 21:15:01 -0400 (EDT)
Links: << >>  << T >>  << A >>

I did not look at the core but I have played with I2C on the Pro.  On th=
e
V2pro I think you need to use the tristate control as data out and tie t=
he
tristate driver in to gnd.  This gives you the open collector output mod=
e. 
You will need to add the pullup resistors on CLK and DATA if the board/p=
art
you are driving does not have them (about 3K for the 100KHz bus.)  There=
 was
an answer on the Xilinx page on using the V2pro I/O in open drain mode. =
 I
used the bidi tristate pin and had the input point return to the logic t=
o
sense the bus levels.
 
Good luck,
   Nitro

On Fri, 09 Apr 2004 12:25:15 +0200, Mancini Stephane wrote:

>
>
>Hi everybody,
>I've just downloaded the i2c controller from opencores.org and I was
>wondering how to use it within my system.
>Indeed, I've a xilinx V2PRO connected to a video encoder SAA7127 to be
>configured thru an i2c interface.
>Can I directly connect the I2C interface of the SAA7127 and declare a
>tristate I/O pad on the V2Pro, being connected internally to the i2c co=
re
>? 
>Thanks a lot for your help
>
>St=E9phane





Article: 68619
Subject: rocket IO MGT location constraint?
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Fri, 9 Apr 2004 21:59:49 -0400 (EDT)
Links: << >>  << T >>  << A >>
I am using a memec 2Vp20 board and I want to know which LOC constraint i
should use to be able to use rocket IO ports #6 and 7 or MGT # 19 and 21.
I have looked around and been unable to find any documents correlating
these port numbers or MGT numbers to actual LOC style constraint
any help would be appreciated

thanks

Matt

Article: 68620
Subject: Re: Spartan-3 LC Development Kit from Insight with USB 2.0 Port
From: "Antti Lukats" <antti@case2000.com>
Date: Fri, 9 Apr 2004 22:00:10 -0700
Links: << >>  << T >>  << A >>

"Dave" <postmaster@localhost> wrote in message
news:40767be7_1@news.chariot.net.au...
>
> In January there was a discussion about the Spartan-3 LC kit from Memec.
> (http://www.memec.com/Memec/iplanet/link1/Spartan3LC_3.pdf)
> I'm wondering if anyone has purchased the kit and has any comments?
>
> In particular Im interested in the USB 2.0 Interface. We are

S3LC uses Silabs serial to usb converter chip CP2101
www.silabs.com/products/pdf/CP2101_Short.pdf

Antti
http://xilinx.openchip.org



Article: 68621
Subject: Re: [OT] Is anyone alive at Opencores.org?
From: "Antti Lukats" <antti@case2000.com>
Date: Fri, 9 Apr 2004 22:10:52 -0700
Links: << >>  << T >>  << A >>
Hi Steve,

there are people alive at opencores, but their PCI core is not the only one
that is free, there was a posting here about some other options to get free
PCI cores.

I also have looked at opencores PCI, but it looks very BIG and not so easy
to integrate if you only need minimal PCI functionality. I have written
myself some minimal PCI cores that are FPGA tested, unfortunatly they are
not ready to be released as I had some problems and no time to fix those
problems. The cores was so small that would fit XC9572 !

antti
http://xilinx.openchip.org

"Stephen Williams" <spamtrap@icarus.com> wrote in message
news:e5679$4075e579$40695902$21077@msgid.meganewsservers.com...
>
> I'm planning an FPGA design that will use the wb_pci core at
> Opencores, but I've been unable to subscribe to the list there.
> Does anybody know if their mailer/list manager is broken or
> somesuch?
>
> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>



Article: 68622
Subject: Problems installing ISE 6.2 under Linux
From: "Arthur Sharp" <arthur@nospam.com>
Date: Sat, 10 Apr 2004 16:13:21 +1000
Links: << >>  << T >>  << A >>
Hi,
I'm trying to install the ISE 6.2 update under Linux.
My current version is 6.1 with no updates,
straight from the CDs.

I get the following message :
"Xilinx Service Pack 6.2.01i Setup cannot be installed over Xilinx install
versions older than 6.2i."

Since I have 6.1, this shouldn't happen.

I found the following in the answer database :
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=18151

but it doesn't really help as it should be already fixed and, besides, the
$$XILINX
variable seems to be set ok.

I tried the obvious things mentioned in other answers like killing
the wind processes and deleting .windu*, to no avail.

I'm stuck, can anyone help ?
Maybe I need to install other 6.1 updates before 6.2?

Thanks,

Arthur



Article: 68623
Subject: Re: Problems installing ISE 6.2 under Linux
From: "Arthur Sharp" <arthur@nospam.com>
Date: Sat, 10 Apr 2004 19:54:35 +1000
Links: << >>  << T >>  << A >>
I installed 6.1.03 without problems, but 6.2 still refused to install giving
the
same message as before.

Arthur
"Arthur Sharp" <arthur@nospam.com> wrote in message
news:407790b6$0$25655$afc38c87@news.optusnet.com.au...
> Hi,
> I'm trying to install the ISE 6.2 update under Linux.
> My current version is 6.1 with no updates,
> straight from the CDs.
>
> I get the following message :
> "Xilinx Service Pack 6.2.01i Setup cannot be installed over Xilinx install
> versions older than 6.2i."
>
> Since I have 6.1, this shouldn't happen.
>
> I found the following in the answer database :
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
> 1&getPagePath=18151
>
> but it doesn't really help as it should be already fixed and, besides, the
> $$XILINX
> variable seems to be set ok.
>
> I tried the obvious things mentioned in other answers like killing
> the wind processes and deleting .windu*, to no avail.
>
> I'm stuck, can anyone help ?
> Maybe I need to install other 6.1 updates before 6.2?
>
> Thanks,
>
> Arthur
>
>



Article: 68624
Subject: problems iwth I/O pins
From: johnong99@hotmail.com (john ong)
Date: 10 Apr 2004 07:58:53 -0700
Links: << >>  << T >>  << A >>
I have been working on XCS10 Spartan series Xiinx FPGA. This is the
first time I try programming the chip using JTAG pins.  I did the
necessary connections like pulling up the INIT pin during
configuration. Connect all Vcc and GND pins. Grounding the MODE pin as
my board only have one FPGA. I tied the Din and Dout pins together.
But after I flash the code into the chip all the I/O pins are still
pag at 5V. Does anyone know what may be causing the problem?

John



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