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Our company has figured out how to install Foundation 2.1 / 3.1 in Windows XP SP2. Please contact me for further information. paul@customdesignsolutions.comArticle: 76976
"Symon" <symon_brewer@hotmail.com> wrote in message news:32gjgiF3lb586U1@individual.net... > Hi John, > What I'm thinking is, if the input to the circuit is the phase step, > effectively frequency in this case, you have to calculate "2^27-100M plus > the phase step" somewhere in the circuit each time the frequency changes. > This needs another adder, yes? Can you fit all the stuff into 1 lut per bit? > Cheers, Syms. You can have either a separate adder or (as I did it before) two different phase values supplied by software: the raw phase and the adjusted phase. If you want an adder to calculate the adjusted phase value, register the value and the timing doesn't suffer. Just a reminder that the duty cycle will be (2^26/100M)/(1-2^26/100M) or 67.1%/32.9% on average unless you'd care to adjust whenever the MSbit toggles.Article: 76977
I am looking for some material about the various clock synchronization techniques, their advantages etc. Thanks NeilArticle: 76978
cdsipjp wrote: > Our company has figured out how to install Foundation 2.1 / 3.1 in Windows > XP SP2. Please contact me for further information. > paul@customdesignsolutions.com While Any Foundation software may works on Windows XP, beware that part of the program, the Impact, that is used to download the bitstream to the FPGA board may not work. If you want to use the software to download the bitstream to the FPGA board with Windows XP, you must use Xilinx ISE 5.1i or above. HendraArticle: 76979
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:32g6taF3kks5aU1@individual.net... > Hmmm, maybe not smaller as you need a subtraction as well as an > accumulation. I need to think about that when I get time. But certainly more > accurate.... Why not use a xtal with a power of two frequency?? We telecom guys do this regulary. Regards FalkArticle: 76980
Hello Gerd, Thanks for the reply. Could you provide me with any information you have obtained with regard to the amount of time in terms of clock cycles it takes to read/write 1. single CLB column 2. single BRAM column Also could you share your experinece in using the HWICAP module Thanks HarishArticle: 76981
does it mean that a target only PCI device can be master as well as slave? master when initiating data trasnfer and slave when on the receiving end?Article: 76982
Hi, I am also trying to use a digilent board together with the coregen fft. You are saying the fft does not work. can you elaborate? Would you be willing to share your code with me so that I have an example of a working implementation? Thank you very much for your time, Jan Beck Tonny wrote: > Hello, > > > I plan to buy digilent combo board DIO2 combo. Does anybody know if a > > download cable will be included in the package? also, do they provide > > the software like foundation or webpack? > > Yes, the cable is included. But you need dowload de webpack from > xilinx's site. > > > I plan to implement some work of dsp, like FFT, FILTER. Hope this > > spartan II (200k gates) FPGA on this board helps. Has anybody tried > > that on digilent's board either? > > I'm doing a OFDM in my D2-DIO2 combo, that have a IFFT. > > I'm using the FFT from www.opencores.org, because de FFT from Coregen > don't work properly in Spartan-2.Article: 76983
I appreciate the responses. I'll look at them to finish this. One person emailed me asking why I am using CUPL. As I'm new to programmable logic, I decided it'd be best to start with a CPLD. I obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery, I went trolling for a piece of software to use to program them, thus WinCUPL. The email suggested ABEL, and I'll give that a shot as well. Another person suggested I dload WebPack or Xilinx's offering, draw the schematic, and export as a VHDL file, load into WinCUPL, and go from there. I dloaded WebPack, drew my schematic (I'm a software developer, but I am struggling with VHDL. Schematics, OTOH, I can draw very easily). I managed to get the schematic to compile on Quartus (with warnings about my inout pins being tied to VCC or something, so I suspect I've done something wrong), so I exported as VHDL (looks nasty, like decompiled C code), and imported into WinCUPL. No go. Reading the newsgroup for a few weeks, I am obviously not in the same league as most who frequent here, but it just seems very hard for a new entrant to programmable logic to get a CPLD going. I'd love to go straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so an FPGA and an EPROM seems overkill. Am I going about this the wrong way? Should I avoid CUPL like the plague? Is ABEL my best bet for CPLD design, or is there a reasonable VHDL tool that will give me files I can program into a 750 or 1504, or industry std PAL/GALs? I sense the VHDL versus Verilog discussion is like the VI versus EMACS discussion, how does a newbie like me, decide which to pick to learn first? Google didn;t turn up a FAQ for this newsgroup, but I'd assume some of these questions would be in a FAQ... The online helps are very targeted, but none seem to answer the above questions. As an outsider looking in, I've noticed the Altera/Xilinx discussion is another pseudo-religious war, but I often see the voice of "reason" suggest that people simply need to load their model into both design tools, see who handles the model better, and choose designs based on that information. I think that's wise advice, but it doesn't help people like myself who know neither tool well, and are just starting out. Newcomers, like myself, typically have small designs, low speed, and need lots of help while using the tool initially. For that type of user, is it possible for me to ask for recommendations without triggering a war? I know not everyone's taste is the same, but right now, best is defined to me as easiest to succeed at. Jim, still trying to figure out how to tie into output enable on inout pins on his schematic, Brain -- Jim Brain, Brain Innovations brain@jbrain.com http://www.jbrain.com Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times!Article: 76984
>does it mean that a target only PCI device can be master as well as >slave? master when initiating data trasnfer and slave when on the >receiving end? target == slave the end that responds to a read/write from someplace else initiator == master -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76985
Jim Brain wrote: > I appreciate the responses. I'll look at them to finish this. > > One person emailed me asking why I am using CUPL. As I'm new to > programmable logic, I decided it'd be best to start with a CPLD. I > obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery, > I went trolling for a piece of software to use to program them, thus > WinCUPL. > > The email suggested ABEL, and I'll give that a shot as well. Another > person suggested I dload WebPack or Xilinx's offering, draw the > schematic, and export as a VHDL file, load into WinCUPL, and go from there. > > I dloaded WebPack, drew my schematic (I'm a software developer, but I am > struggling with VHDL. Schematics, OTOH, I can draw very easily). I > managed to get the schematic to compile on Quartus (with warnings about > my inout pins being tied to VCC or something, so I suspect I've done > something wrong), so I exported as VHDL (looks nasty, like decompiled C > code), and imported into WinCUPL. No go. If you look at the REPORT files from Altera, or Xilinx tools, you will see Boolean Eqn formats, and that is quite close to CUPL. > > Reading the newsgroup for a few weeks, I am obviously not in the same > league as most who frequent here, but it just seems very hard for a new > entrant to programmable logic to get a CPLD going. I'd love to go > straight to FPGAs, but the entire circuit is a 5 FF, 20 gate design, so > an FPGA and an EPROM seems overkill. It is. A SPLD/CPLD is the best solution. > > Am I going about this the wrong way? Should I avoid CUPL like the > plague? No, CUPL is pretty much the only currently supported flow for the ATF750/SPLDs. ABEL is no longer generically available, since Xilinx took over, but it (or a close variant) is still offered by some vendors. > Is ABEL my best bet for CPLD design, or is there a reasonable > VHDL tool that will give me files I can program into a 750 or 1504, or > industry std PAL/GALs? VHDL has a much greater learning curve, than CUPL. CUPL is simpler, ( rather like structured Assembler vs Java ), and you use the DOT extensions [.CK, .D, .OE, .IO etc ) to 'create the circuit' you would have drawn on paper. You also KNOW exactly what PLD resoutce it will use, at the time you write the code. CUPL can also create test vectors that any good device programmer can run after PGM, to verify the actual silicon operation. These test vectors also allow you to verify and identify secured devices - eg in a field return : Is the PLD still OK, and what version is it ? CUPL is a good fit for ATF16V8/ATF22V10/ATF750/ATF1502/ATF1504 SPLD/CPLD, but you would not design a soft-cpu using CUPL. You could also look at ICT's PEEL SPLD/CPLD, and their WinPLACE. I prefer the command line nature of CUPL, but you may like the graphical nature of WinPLACE. See http://www.anachip.com/eng/product/pld.php -jgArticle: 76986
On Sat, 18 Dec 2004 06:05:07 GMT, Jim Brain <brain@jbrain.com> wrote: >I appreciate the responses. I'll look at them to finish this. > >One person emailed me asking why I am using CUPL. As I'm new to >programmable logic, I decided it'd be best to start with a CPLD. I >obtained 2 from Digikey, an ATF750 and a Atmel 1504AS. After delivery, >I went trolling for a piece of software to use to program them, thus >WinCUPL. As Jim G noted, CUPL (or the currently available and free (always nice) WinCUPL) is a good fit for smaller PLDs. Devices like the 22V10 are great for learning, being fairly inexpensive and are also available in DIP form-factors with 5 V supplies -- handy to be able to "make something" without having to spin a board for a TQFP footprint. When you start reaching beyond SPLD-land, you probably should bite the bullet and learn VLDH or Verilog. Take a look at both. If you're already comfortable in C then Verilog may feel more comfortable to start with. Once you know either, though, learning the other isn't too bad. -- Rich Webb Norfolk, VAArticle: 76987
Hi all, Can someone help me?Article: 76988
Hi everybody, I want to program a embedded microcontoller to load a configuration bitstream using the slave select MAP mode of virtex II. Are there any command words to be issued to commence programming or just read the bitstream byte by byte and write it into the select MAP data pins.Article: 76989
"Ray Andraka" <ray@andraka.com> wrote in message news:dUAwd.1205$Tf5.139@lakeread03... > Symon wrote: > >>Hal, >>Make the accumulator overflow at 100,000,000 rather than at 134217728. >>HTH, Syms. >> > No, that doesn't work. The phase accumulator depends on modularity of the > number system, and by truncating the count like that you destroy the > modularity. The way to get there is to extend the width of the > accumulator and select the appropriate constant based on the accumulator > width. > Ray - I agree for a general-purpose synthesizer with a phase accumulator addressing a SINE look-up table. But if you don't need a general-purpose synthesizer (i.e., you only need to generate one output frequency) then can't you pick any modulus you need and create the SINE LUT to match that modulus? And if you just need a digital (1-bit) output clock then you should always be able to pick whatever accumulator modulus you want and use the MS bit of the accumulator as the output clock. The only requirements are that Fout = Fin * (M/N), where M and N are both integers and M/N <= 1/2. N becomes the modulus of the accumulator and M is the phase value. For the example being discussed, 1Hz = 100e6Hz*(1/100e6). The modulus is 100e6, and the phase value is 1. (When the phase value is 1 like this you can use a counter instead of an accumulator.) If output duty cycle matters then you also need to center the truncated accumulator range in the center of the full binary range of the accumulator. In this example you want the accumulator to cover the range (2^27)/2 -500e6 to (2^27)/2 + 500e6 - 1. The MS bit will then be a perfect 50% duty cycle 1Hz clock. Any holes in all this? Bob S.Article: 76990
I'm looking to do some experiments with FPGAs, but I work solely on my Mac PowerBook laptop and I don't really have an easy place to keep an exposed FPGA development board lying around (I live on a sailboat). So it would be nice if I could find a simple FPGA experimentation kit. My PowerBook has a PCMCIA slot that I'm not using, so I thought that there must be some FPGA with at least 8MB of SDRAM packaged as a Type I PCMCIA card that I could use. I've searched high and low for what seems to me to be an obvious product to no avail. So, my question is, has anyone seen such a thing? If so, where can I find one? thanks, -gregArticle: 76991
Uwe Mattheyer wrote: > Hi all, > Can someone help me? If it is one of the smaller 20/24 pin ones, and you cannot read the contents, you can reverse engineer. Start with the circuit (which you wil have, right?), and determine which are IPs and outputs, then get a good device programmer that supports IC testing, and write a set of tests for the PLD. 15-150 lines is typical, and when you have all plausible IPs testing OK, write the boolean eqns in something like ABEL/CUPL and compile, and re-test a NEW programmed GAL against the vectors, and also in-circuit. -jgArticle: 76992
I am trying to achieve something that probably thousand have done before me. I want to program a sram module that is attached to my fpga (xc2s300). I have a parallal cable programmer that is compatible with imPact. Now i am wondering what do you use (software/hardware) to program ram by jtag. There must be an easy way !? Michel Bieleveld.Article: 76993
Hi there, currently i have been working on a project involving developement of a simple PCI target for data acquisition. all that i want is a "simple" target device that will get detected and will work properly as a target, i.e. cause data transfer from the PCI card to the PC when requested. i need to keep the cost at bare minimum. i cannot use the readymade kits/cards like the one from PLX. i m going to use spartan2 fpga. again i m pretty an inexperienced person in this regard. hence i have some doubts regarding the PCB developement that i will have to undertake - will a two layer PCB suffice for this purpose? are plated through holes are necessory? any alternative? what will be the approximate cost for a PCB with plated through holes? can i hand solder the PQFP/TQFP packages to the board? any extra precautions to take while doind that? can you recommend me a good soldering gun assembly (of course low cost) for that purpose? any suggestions, recommendations regarding further references, books that i should read for this kind of PCB developement, softwares that can be useful, tools of the trade, and any other thing that may be useful, will be greately appreciated; as they are you people whom i m banking on for guidance, in this critical project. Seriously. TIA, Shreyas KulkarniArticle: 76994
I don't know about PCI, but for cheap board fabrication I know this combination works: pcb.sourceforge.net and barebonespcb.com. You get plated through holes by default, minimum quantity ONE, and fast service too. You'll have to do some cutting to make it fit into a PCI slot though, as they only do rectangles with that service (4pcb can do ANYTHING, but their barebones deal doesn't allow it). A 4x6 board is $48.20 ($35 to set up, $13.20 per board).Article: 76995
Hi all!
I wrote an hard macro by using the FPGA Editor and I want to use it in a
design for a Spartan2. But when I launch the Implementation process,
several errors occur :
ERROR:Pack:1195 - Symbol "rules_gen_11_rule_comp_rule_macro" has no
output pin
connections.
ERROR:Pack:1195 - Symbol "rules_gen_8_rule_comp_rule_macro" has no
output pin
connections.
ERROR:Pack:1195 - Symbol "rules_gen_19_rule_comp_rule_macro" has no
output pin
connections.
Nevertheless, this macro seems to be correct. I've defined external
output pins and all these pins are reachable. I definitely don't
understand what gets wrong.
Grégory Mermoud
gregory.mermoud@epfl.ch
P.S. : I get these messages before the errors. I don't understand them :
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_1_rule_comp_rule_macro
untyped for FragLib.ltl
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_2_rule_comp_rule_macro
untyped for FragLib.ltl
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_3_rule_comp_rule_macro
untyped for FragLib.ltl
Article: 76996
Hi all!
I wrote a hard macro for a Spartan2 and I want to use it in my design.
But my implementation process fails with these errors :
ERROR:Pack:1195 - Symbol "rules_gen_11_rule_comp_rule_macro" has no
output pin
connections.
ERROR:Pack:1195 - Symbol "rules_gen_8_rule_comp_rule_macro" has no
output pin
connections.
ERROR:Pack:1195 - Symbol "rules_gen_19_rule_comp_rule_macro" has no
output pin
connections.
Nevertheless, my macro seems to be correct. It includes external output
pins and they are reachable. I don't understand what gets wrong... Have
you ever encountered such a problem ? Do you know what this error means ?
Grégory Mermoud
P.S: Here is the messages that I get just before the errors, but I don't
understand them.
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_1_rule_comp_rule_macro
untyped for FragLib.ltl
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_2_rule_comp_rule_macro
untyped for FragLib.ltl
Ldm_View: branch
/inference/FRAGCOVERED/inference/rules_gen_3_rule_comp_rule_macro
untyped for FragLib.ltl
Article: 76997In article <1103414414.755056.267120@f14g2000cwb.googlegroups.com>, Shreyas Kulkarni <shyran@gmail.com> wrote: >will a two layer PCB suffice for this purpose? I made (at home, even) a 2 layer PCB which worked, but it's probably not a good idea. There are cheap board places that will make a 4 layer board where the interior layers are limited to gnd/vcc for not that much more than a 2 layer board. You can see my board at: http://ben.com/minipci/ >are plated through holes are necessory? any alternative? You will have to have vias (there are necessary signals on both sides) but you can do it with wires if necessary (like you would at home). >what will be the approximate cost for a PCB with plated through holes? There are places you can check like expresspcb, pcbexpress (yes, they're different), olimex. You'll probably be stuck cutting your own registration slots, though. Not many places cut outlines with notches that small. >can i hand solder the PQFP/TQFP packages to the board? Yes, it's not hard. Use a lot of flux, tack the corner pins and then you can 'wipe' the solder on. Use solder wick to correct bridges. Or you can order (fairly expensive) solder paste and reflow in your toaster oven (google it). >can you recommend me a good soldering gun assembly (of course low cost) >for that purpose? You don't want a gun for fine work. Get a quality solder station with a fine tip. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 76998
There is a list of FPGA board at http://www.fpga-faq.com/FPGA_Boards.shtml (Thanks Philip.) The only mention of PCMCIA is Annapolis Micro Systems http://www.annapmicro.com/ You have another set of problems. Where are you going to get software that runs on a Mac? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76999
In PCI, masters are called initiators and slaves are called targets. A target only device can never initiate a transfer on the bus. It may be read or written by other initiators. A PCI device can be both a master and a slave but it wouldn't be called 'target only'.
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Compare FPGA features and resources
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