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Hi everybody. I want to start experimenting with fpga hardware. I have experience with simulating RISC processors in modelsim. I want to know which dev board would be a good starting point. There seem to be many boards out there but i want one with pci interface. Do spartan3 boards come with pci ?Article: 76476
colin wrote:
> Guys
>
> We have just laid out a board and want to put the thermal analysis to
> bed (it's conduction cooled so not much room for error). If the xilinx
> estimator says we are going to use 25 watts does anyone know the best
> way to code an FPGA so that it will get nice and hot.
>
> The estimator is just that, but is there a more accurate way of
> writing some code so that a particular clock input will generate a
> particular amount of heat. A 2000 D type serial chain where every flip
> flop is toggling every clock which blinks an LED is obviously one way
> but doesn't seem very ellegant.
>
If your goal is just to generate heat, use all the LUTs as SRL's, make
use of all the BRAM's, and drive all the I/O's with a nice high current
drive strength.
Marc
Article: 76477Jon, Yes, the Mars Mission Landers' uses scrubbing once every 12 hours. No redundancy. Turns out SEU's on Mars are not a big deal. Not as bad as even here on earth! 12 V1000's per rover. Controls wheels and some arm functions (or so I'm told). The lander FPGA that fired the squibs for the parachute was a different matter: fully TMR AND scrubbed continuously (reprograms while operating). It also had three processors that were voting on the firing -- and if they failed to instruct, the FPGA would take over (or so I'm told). Applications in space have outgrown the fuse technology FPGAs (they are just too small), and Xilinx FPGAs are being applied like crazy to space missions. And our FPGAs have no 'power on surge', no funny long term fuse failure issues, and have well behaved IO's on power up and down (they stay tristate). I am told that the next Mars lander walks around faster than a person does due to increased compute power from our newest FPGAs (rather than crawling about at a snail's pace). That is how much more power there is from Virtex 1000 .22 micron to Virtex II Pro 130 nanometer 2VP100 (roughly ten times the logic, at four times the speed, not to mention the 405PPC, etc.). Our Mil/Aero/Automotive Group handles all the work for this area. Did you know that under the hood of a car is a more hostile environment than low earth orbit? (totally random interjection) Fully triple modular redundant designs are now trivial to do with the Xilinx XTMR tool. Select those modules that you wish to triplicate, and after your design is done, tested, and verified, XTMR it, and do a final verification. http://www.xilinx.com/products/milaero/tmr/index.htm The remaining issue is single event functional interrupts (SEFI) which are upsets that reset the entire device. The cross section for that single point failure is very tiny, but for space applications (and others) all single points of failure must be accounted for (even if they are a once in a million year event). All devices (ASIC, FPGA, uC) will have some SEFI cross section, as there is at least one node somewhere that when hit will upset the whole design (like the reset line). Contact one of our Mil/Aero/Automotive FAE experts to get all the details. AustinArticle: 76478
Coiln, Just make a huge shift register, or all DFF's toggling, and then just vary the clock input (or the shifted data input pattern from ....000001, to 101010....etc). That is what we do. Austin colin wrote: > Guys > > We have just laid out a board and want to put the thermal analysis to > bed (it's conduction cooled so not much room for error). If the xilinx > estimator says we are going to use 25 watts does anyone know the best > way to code an FPGA so that it will get nice and hot. > > The estimator is just that, but is there a more accurate way of > writing some code so that a particular clock input will generate a > particular amount of heat. A 2000 D type serial chain where every flip > flop is toggling every clock which blinks an LED is obviously one way > but doesn't seem very ellegant. > > We have wired up the internal temp sense diode to take a look at the > result (and yes we know how noisy and innacurate they are). > > Any experiences? > > ColinArticle: 76479
"colin" <colin_toogood@yahoo.com> wrote in message news:885a4a4a.0412030423.4f6b7e7c@posting.google.com... > We have wired up the internal temp sense diode to take a look at the > result (and yes we know how noisy and innacurate they are). > > Any experiences? > Well, I've found the diode isn't particularly noisy nor especially inaccurate! It gives repeatable and consistent (between parts) results, certainly good enough for your application. You have routed its connections together and away from big switching currents, I presume?! I use copper sheet to move heat to where I can get rid of it. Cu is 400 W/m/K, about twice as good as Aluminium. Don't use copper alloys. Very useful if you've got boards stacked closely together, you can get the heat out from between the boards. I've never tried heat pipes, but they're meant to be very good indeed. Finally, you'll find that the FPGAs work at elevated temperature for a long time. I recall a thread on CAF all about FPGAs down boreholes where they were running for weeks at 175C. You might be enlightened by a quick trawl of CAF in Google Groups. So, what's the lifetime of your product? How long will you be working for that company? All part of the engineering compromise!! Good luck, Syms.Article: 76480
In article <f4e089e0.0412030721.aec0769@posting.google.com>, Dan <dan.costin@gmail.com> wrote: >I must connect bkend_dat[31:0] on the fifoin_dat[31:0]. But fifos >don't have address lines. What shoud I must to do with bkend_ad[31:0] >address lines?? (Put its on high-z ???) Impossible to say without knowing more about your PCI interface. However, if you're using non-addressable memory, what do you expect to do with the address line? Does it decode one register that you read repeatedly for data? Or does it act like a 'seek' on the fifo? > 2. If my pci target doesn't meet pci tsu<7ns and tco<11ns it is >posible to work??? Yes, for experimentation purposes. Especially if you put the card in the slot closest to the PCI bridge chip. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 76481
"Austin Lesea" <austin@xilinx.com> wrote in message news:coq35v$af14@cliff.xsj.xilinx.com... > Did you know that under the hood of a car is a more hostile environment > than low earth orbit? (totally random interjection) > Depends if the engine's running or not and whether you're wearing a spacesuit or not.Article: 76482
Brian, >>> http://toolbox.xilinx.com/docsan/xilinx6/help/floorplanner/floorplanner.htm >> > > It doesn't work very well ... yet. I have a couple of webcases open on > that, and hopefully Xilinx are working to fix some of the problems. Hmm, I'll just have to see in that case. >>The only thing missing is annotating the EDIF file directly with the >>constraints generated by the Floorplanner in UCF format. I think I can >>probably manage writing a tool to do this though. > > This MAY be possible. The floorplanner writes an UCF for the RPM, and > (assuming that UCF works) can invoke "NGCbuild" to back-annotate the > placement information into the proprietary NGC file from the XST > synthesis tool. > There is an "NGC2EDIF" tool which I have used to verify that the > resulting NGC tool contained valid placement info from the above process > - its EDIF output did - while trying to debug the above approach. > > So if you can convert from EDIF to NGC in the first place, there is the > basis for a loop. I haven't tried the EDIF flow so can't comment, though > it's interesting that NGC2EDIF is present but NGD2EDIF is now > unsupported. That could certainly save me some effort, so I'll investigate this. Thanks, - JakeArticle: 76483
qizhang@kth.se (kevin) wrote in message > what interest me more now is the algorithms and principles of simulation and > synthesizing, and i really want to make a tiny simulation tools(like > simili) or synthszing tools, > that's what i want :-). Are you saying that you want to make your own simulator and your own synthesis tool? Well, I don't know anything about that! Perhaps the LRM (Language Reference Manual) from IEEE may help you, because it is made more for the developer who makes the simulator and synthesis tool, rather than for the engineers who just use it. HendraArticle: 76484
>So, what's the lifetime of your product? How long will >you be working for that company? All part of the engineering compromise!! ROFL !! thanx for the chuckle - Mike TArticle: 76485
"John" <placename@remove_fpga_people.co.uk> wrote in message news:<1102069745.41459.0@iris.uk.clara.net>... > I have been running a shift register design through a web version of Quartus > 4.1 (SP2). Depending on the size of shift register either the tools don't > complete (I waited 30 mins and gave up) or on smaller shifts of 720 I get a > design that is a large size and it takes a long time to implement. > > Has anyone else seen this problem ? Or know of any tool switches that need > set to solve this ? > > I have selected large enough Cyclone part and before anyone asks I am > running a reasonable machine. An Athlon64 3000 with 512 MByte of memory for > those that want the detail. I have run the same design (large version) on > Spartan-3 / ISE and it less than 3 minutes to do the same. > > John John, We would like to investigate this further and help you. It would help if you would send me the source that you used or post it here. Thanks - Subroto Datta Altera Corp.Article: 76486
Hello from Gregg C Levine Regarding those boards, or even that one, if your don't need it, I'll take it. Write me away from the list for my address. -- Gregg C Levine landocalrissian atsign att dot net "This signature owns a starship." In article <e3fd5378.0411231034.47399196@posting.google.com>, ccon67@netscape.net says... > >Martin Kellermann <Martin.Kellermann@nospam.xilinx.com> wrote in message news:<41A2F1BD.6030103@nospam.xilinx.com>... >> Hi Lars, >> >> last winter I also found two boards with XC3000s on them. What I did >> with them was to de-populate them and make them into key-holders. >> >> Now they are hanging on the wall in my flat and do a proper job. Appart >> from that, if you want to do any FPGA-things: those things are ancient.... >> >> Cheers, >> >> Martin >> >> >> >> Lars Helgeson wrote: >> > Hello guys, I have a ISA-card with a xilinx xc3030 on it that i >> > understand is something you know what it is.. >> > >> > http://hem.bredband.net/b222911/thecard.jpg >> > >> > I looked in all my drawers and found this one that was given to me a >> > couple of years ago, does anyone know what it is, and what can be done >> > with it? >> > >> > If sellable, what is reasonable to ask for this card? >> > >> > Thanks in advance! :) >> > >> > //Lars > >haha, I had a XC4010 as key-holder too, but i though it's not lead >free so I dont want to keep it anymore. If sellable, what is >reasonable to ask for this keyhold? :)Article: 76487
I must to do some actions that are slowest that pci_clk and for that I use a fifo where I store temporary data. I use fifo_full and fifo_empty signals for make transactions between pci-target and fifo. I defined that fifo like a memory space with a base_address_register, and when a have a base_adr_hit for this space I must to write in the fifo (practicaly I must to write at the same address because fifo has no address lines). Regards,Article: 76488
In article <f4e089e0.0412032309.43fef68b@posting.google.com>, Dan <dan.costin@gmail.com> wrote: >I must to do some actions that are slowest that pci_clk and for that I >use a fifo where I store temporary data. I use fifo_full and >fifo_empty signals for make transactions between pci-target and fifo. So you are using the fifo to buffer for a memory interface that's not synchronous with the PCI bus? Then the base address would have to be stored where you're going to need it to determine where to put the output side of the fifo. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 76489
Johnson wrote: > Hi there, > > I am a newbie and I do not know how to subscribe to the newsgroup > listed in the following website. Could anybody let me know what is the > server name for the newsgroup? I need it to fill the "Server > Information" of my "Microsoft Outlook Newsreader"? > > http://jupiter.sun.csd.unb.ca/usenet/comp.html > > Thanks. > > Johnson free newgroup server One thing you might like to try is typing "Free newsgroup server" in a google search engine and from the result decide if any of the services are good enough for your use. http://www.teranews.com/ seems to offer a free service with a daily download limit of 50MB. However as I do not use their service I cannot vouch for them.Article: 76490
"Victor Schutte" <victors@mweb.co.za> wrote in message news:col2k1$g63$1@ctb-nnrp2.saix.net... > Does anyone out there have any IP and documents on how to use SD cards ? > > > Victor Victor, the answer to your question is "Yes". But that's was obvious, isnt it? If you want that somebody replies to you and says: "here you go please take free IP for your commercial product" - then that answer usually do not get. Even if there is free IP, using it may take more support than you save. SD is little different from MMC so plain MMC IP will not work for SD, there was supposed to be MMC IP at opencores but the project creator never uploaded any files and project was deleted later. AnttiArticle: 76491
Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote > > Classical approaches teach logic elements and logic minimation, but this is > counterproductive. Why does the academic community still teach methods that are not used in the industry, such as K-Map? HendraArticle: 76492
720 stages shift register need 45 Xilinx CLBs; but how many Altera LEs ? Walter. "Subroto Datta" <sdatta@altera.com> a écrit dans le message de news:ca4d800d.0412031630.2e98268a@posting.google.com... > "John" <placename@remove_fpga_people.co.uk> wrote in message news:<1102069745.41459.0@iris.uk.clara.net>... > > I have been running a shift register design through a web version of Quartus > > 4.1 (SP2). Depending on the size of shift register either the tools don't > > complete (I waited 30 mins and gave up) or on smaller shifts of 720 I get a > > design that is a large size and it takes a long time to implement. > > > > Has anyone else seen this problem ? Or know of any tool switches that need > > set to solve this ? > > > > I have selected large enough Cyclone part and before anyone asks I am > > running a reasonable machine. An Athlon64 3000 with 512 MByte of memory for > > those that want the detail. I have run the same design (large version) on > > Spartan-3 / ISE and it less than 3 minutes to do the same. > > > > John > > John, > We would like to investigate this further and help you. It would > help if you would send me the source that you used or post it here. > > Thanks > - Subroto Datta > Altera Corp.Article: 76493
Nicholas Weaver <nweaver@soda.csua.berkeley.edu> wrote: > Before I go through and build my own state machine compiler out of > python hack-scripts or Excel macros, does someone already have such a > compiler available? if you are using xilinx devices, picoblaze could be a smart solution for (medium) complex state machines... VHDL source and some (mostly DOS/Win32 based) assemblers are avaiable (for free). Just take a look at: <http://www.xilinx.com/products/design_resources/proc_central/grouping/picoblaze.htm> WD --Article: 76494
"Antti Lukats" <antti@case2000.com> wrote in message news:corsiq$17j$00$1@news.t-online.com... > SD is little different from MMC so plain MMC IP will not work for SD IIRC SD is a superset of MMC. An SD card is an MMC card with a few extra pins, access modes and a security scheme. I heard the latter was soon cracked, but the keepers of the spec behave as if it were not. That is, you have to pay to see it. Which is a bad sign: security should be ensured by keys, not knowledge of the locking mechanism. After all, anyone can find out how Chubb locks work, but it won't tell you which key you need for a particular lock. In short you have an MMC card with the option of faster access modes. These shouldn't be too hard to add if you already know MMC. The security features are not worth bothering with, IMHO.Article: 76495
kevin wrote:
> But what you said seems how to use vhdl/verilog to do fpga design, but
> in fact, these are what i have been doing for years, and what interest
> me more now is the algorithms and principles of simulation and
> synthesizing, and i really want to make a tiny simulation tools(like
> simili) or synthszing tools,
> that's what i want :-).
It's good to know what you want, but the playing field is large,
so consider exploring a bit. Simulation attempts to answers the question:
"How can I predetermine that the hardware described by my HDL
or netlist text will function as I expect without actually
building and testing it."
http://www.google.com/search?q=digital+hardware+description+simulation+theory
I expect that you will find that software tools like Simili are not
as tiny as they might look.
Synthesis attempts to answer the question
"How can I build a physical logic circuit that will function
exactly as predicted by the simulation of my hardware description text"
http://www.google.com/search?q=digital+hardware+synthesis+theory
Good luck.
-- Mike Treseler
Article: 76496Personaly: I think the first step for a eda tools must be a compiler which translate our vhdl or verilog codes to some intermediate format(like the binary format in modelsim), and then use some simulate and schedule algorithm and policy to do analysis and calucate, then get the result. So, I think they are the key to success. this is just my personal opinion :-)Article: 76497
Viktor Steinlin wrote:
> Hello,
> I'm about to design a frame grabber where I need high memory bandwidth.
> Does anybody has already implemented a design with Xilinx Virtex-II PRO and
> DDR2 SDRAM. Have you encountered major problems with DDR2 controller
> provided by Xilinx EDK? Some design hints?
>
> What about Rocket IO. Did you encounter problems on connecting two FPGAs
> over short (50cm) cable? Or does it work on first try, if the layout is
> done properly?
Howdy Viktor,
I can't help you with the DDR2 SDRAM controller, but for as long as
it has been out, I'd be surprised if there were any serious problems
with using it.
As for the Rocket I/O over cable, what kind of cable are you going to
use? Over what distance? At what speed? With which Xilinx part?
Good luck,
Marc
Article: 76498"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:xmksd.112$8v3.36@newsfe5-gui.ntli.net... > "Antti Lukats" <antti@case2000.com> wrote in message > news:corsiq$17j$00$1@news.t-online.com... > > > SD is little different from MMC so plain MMC IP will not work for SD > > IIRC SD is a superset of MMC. > > An SD card is an MMC card with a few extra pins, access modes and a security > scheme. yes and no. if you have IP core that supports MMC then inserting SD card would yield the card to not be recognized at all. its mostly similar, but in order to support MMC/SD there is some additional things required to make both work. the basics sure are the same Antti PS MMC spec ver 4 adds 8bit - per clock mode and 52MHz max clock so the max transfer rates are getting higher! MMC_ver4 uses 6 more pins in addition to the SD card pinsArticle: 76499
In article <colg9a$aeo1@cliff.xsj.xilinx.com>, Jim Wu <nospam@nospam.com> wrote: >picoblaze might be a good fit. Picoblaze is probably significantly slower and larger: The core of the state machine needs to be at 125 MHz. But thanks for the suggestion. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
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