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Johnson, If your IT department blocks access to news servers at the company firewall, your task is somewhat tricky. You typically need to set up a news server connection on TCP port 119 and it sounds as though this port is blocked in your company. Judging from your posts so far, I'd guess you're not considering setting up a proxy server on your home Linux box and tunnelling through the IT firewall. But all is not lost, try social engineering. Buy the IT manager a beer or two. Cheers, Syms. p.s. When they say "NNTP access may leave your computer exposed to viruses" they're bullshitting you. It's no more dangerous than email access, provided they set something up to filter the incoming messages. I guess they're too 'busy' to do this. "Johnson" <gpsabove@yahoo.com> wrote in message news:b1ac2406.0411301627.2d01d19b@posting.google.com... > Thanks for the reply. > > I contacted our IT department, and they said that we do not have > access to NNTPserver, and NNTP access may leave your computer exposed > to viruses. In a word, they would not setup it for me. > > However, I still want to read it in my Outlook Newsreader. Does > anybody know a NNTP server for "public" so I can log on? I know > Microsoft provides "public" server for their own news groups, but I do > not know who can provide a NNTP server for comp.* groups. > > Thanks in advance. > > Johnson >Article: 76451
Does anyone know any FP FPGA core IPs are avaiable for Xilinx Vertex-II Pro? Thanks, JamesArticle: 76452
how to start with development of eda tools(e.g simulation tools and synthesizing tools): what knowledge should i know and where i can find the informations(tutorial, guides or something else) thanks! brArticle: 76453
rickman wrote:
>
> erjs wrote:
> >
> > Hi,
> > I'm working on some AES code.
> > I've declared the values of a particual register in one of the blocks
> > to be a constant.
> >
> > [snip]
> > 4'h0: rcon_func=32'h01_00_00_00;
> > [snip]
> >
> > When synthesizing the design,the bits {23:0] are being trimmed and
> > it's leading to cutting out a whole buncgh of mappings .essentially a
> > useless synth output.
> >
> > Any suggesteions on how to work around this latch trimming and force
> > the ISE not to trim latches/ff? or is there a better way to declare
> > values?
>
> If your logic is being trimmed, it is because it is not doing anything.
> The signals either have a fixed value or are never assigned a value and
> remain at "unknown". When I have this problem and I can't figure out
> what is causing it, I run a simulation and it will show you the logic
> error you have made.
Oh yeah, it will also be trimmed if the logic is not used anywhere. :)
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 76454Hello, I'm about to design a frame grabber where I need high memory bandwidth. Does anybody has already implemented a design with Xilinx Virtex-II PRO and DDR2 SDRAM. Have you encountered major problems with DDR2 controller provided by Xilinx EDK? Some design hints? What about Rocket IO. Did you encounter problems on connecting two FPGAs over short (50cm) cable? Or does it work on first try, if the layout is done properly? Thanks for all infos. Viktor Steinlin --- Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.802 / Virus Database: 545 - Release Date: 11/26/2004Article: 76455
Bret, > A different approach would be to use the Floorplanner feature which > generates a reusable RPM core. You have the option of generating UCF > constraints or a fully annotated core in NGC format (a binary file > similar to the NGO file). Then as Ray mentioned you can add RLOCs > throughout the hierarchy to further manipulate the relative placement. > > http://toolbox.xilinx.com/docsan/xilinx6/help/floorplanner/floorplanner.htm Yes! this seems to be what I want to do thanks. The only thing missing is annotating the EDIF file directly with the constraints generated by the Floorplanner in UCF format. I think I can probably manage writing a tool to do this though. Thanks, - JakeArticle: 76456
Rickman, > I honestly don't understand your constraints. How do you plan to > express your relative constraints if you don't want to put them in the > EDIF file? What is your input format? Are you saying that you don't > want to add the RLOCs, but rather you want the Xilinx tools to do it and > then reproduce your original EDIF file with the RLOCs? > > Perhaps you could explain your intended tool flow more clearly. Like > Denzel Washington said in "Philadelphia", "explain it to me like I'm a 6 > year old". :) My problem was that I _do_ want the constraints in the EDIF file, but I wanted this automated for an arbitrary EDIF design which came with no RLOCs. So perhaps to clarify further what I really wanted was: EDIF (no RLOCs) -> Map & Place -> EDIF (with RLOCs) I can then use the EDIF with RLOCs in JHDL to place other components in a high-level/abstract way relative to the pre-placed design that was in the EDIF. It looks like Bret Wade has now given me the missing link I need to achieve this in the form of the Xilinx floorplaner (See rest of the thread). Thanks, - JakeArticle: 76457
Jacob Bower wrote: > Bret, > > >>A different approach would be to use the Floorplanner feature which >>generates a reusable RPM core. You have the option of generating UCF >>constraints or a fully annotated core in NGC format (a binary file >>similar to the NGO file). Then as Ray mentioned you can add RLOCs >>throughout the hierarchy to further manipulate the relative placement. >> >>http://toolbox.xilinx.com/docsan/xilinx6/help/floorplanner/floorplanner.htm > > > Yes! this seems to be what I want to do thanks. > > The only thing missing is annotating the EDIF file directly with the > constraints generated by the Floorplanner in UCF format. I think I can > probably manage writing a tool to do this though. > > Thanks, > - Jake I'm glad you liked the idea. I'm not yet clear on why the RLOCs need to be annotated back into the EDIF netlist. An easier option would be to just copy the UCF constraints to an NCF file with the same name as the EDIF file. From a Xilinx tool perspective, that is identical to the constraints being in the netlist. BretArticle: 76458
James, http://tinyurl.com/6v8p8 is the link to the Floating Point Unit for a Micro Blaze uC. There are 18 other floating point cores listed on the IP web page http://tinyurl.com/3psf7 Go to the search page, and select the families, and type floating point in the search phrase. Austin James wrote: > Does anyone know any FP FPGA core IPs are avaiable for Xilinx Virtex-II Pro? > > Thanks, > > JamesArticle: 76459
Hey all I get the following error message. Can someone explain why is that? Error: port is driven by a source less connector I have added an GPIO to my XPS and my userIP. GPIO_IO and input port of my userIP are connected internally together by same net name. Error message is given to both of the Ports Thankx in Advance ShakithArticle: 76460
qizhang@kth.se (kevin) wrote in message news:<b5c1b76d.0412021157.360a7def@posting.google.com>... > how to start with development of eda tools(e.g simulation tools and > synthesizing tools): what knowledge should i know and where i can find > the > informations(tutorial, guides or something else) > > thanks! > br 1. Review your digital logic design. Especially the combinational, synchronous sequential and state machine design. I say this because using the tools wouldn't make sense if you don't know the theory. 2. You should have experience of building simple circuits with TTL chips. This will get you a physical feeling with gates, decoder, mux, flipflop etc. 3. Buy an FPGA board. Get Spartan 3 kit (sold directly from Xilinx) or other FPGA boards from third party vendors such as Digilent or Xess. 4. Start using your EDA tools, such as Xilinx Webpack. I would say you should start from Schematics first, then move to HDL. Don't start directly with HDL because it may misguide you to think that HDL is just like C. Doing schematics first also force you to think in term of hardware, not software. This will help later when you do your project with HDL. 5. Learn either Verilog or VHDL. The book that I read to learn Verilog is Verilog HDL by Samir Palnitkar. It is the best Verilog book for beginner. I recommend Verilog because it is much easier to learn. VHDL is Very Hard and Difficult to Learn :-) 6. Go back to your EDA tools and start using Verilog with the tools. Some Useful URLs: www.xilinx.com/ise/webpack : Free Xilinx EDA tools. Comes with simulator and synthesis tool. www.digilentinc.com: FPGA board vendor www.xess.com : Another FPGA board vendor www.xilinx.com/products/spartan3/s3boards.htm : Spartan 3 Starter Kit www.engr.sjsu.edu/crabill : This website has some HDL projects to work with. xup.msu.edu : Xilinx University website. It has links to the EDA tutorials along with projects to work with your EDA tools. Have fun! HendraArticle: 76461
Riccardo Fregonese <ricky.f@libero.it> wrote in message 368b8c2e.0412020249.43429c42@posting.google.com... > Hello, I'm Ricky, an Italian student in eln eng. > I'm working with a Xilinx Spartan3, I've designed a project that > calculate a 12bit fft. The core reads data (in serial mode) from the > ISSI 1M RAM block, calculates the fft, and then writes the results in > an other zone of the memory. > My problem is to put the initial data into the memory (from my pc) and > read them at the end, to verify if the fft works! Hi Riccardo, to solve this problem you have at least two options: 1) you can add an UART and a simple controller to your design, so you can download data in the SRAM, start/stop the FFT module, and read back the results. 2) you can create a separate configuration for reading and writing the SRAM, and reconfigure the FPGA with it before and after you use the FFT configuration. During reconfiguration data is retained into the external SRAM. (Xess boards use a similar method). If you decide to use the RS232 interface you need just the Windows Hyperterminal program to communicate. A.D.Article: 76462
Hi *, I noticed that now the Xilinx Memory Interface Generator is available from http://www.xilinx.com/memory . This should be very useful... On the page it says "Generate your Virtex-4, Virtex-II Pro and Spartan-3 memory interface", but in fact the tool you can download there only supports Virtex-4. Will Virtex-II Pro be supported in the near future or will MIG concentrate purely on Virtex-4? cu, SeanArticle: 76463
"John_H" <johnhandwork@mail.com> wrote > If you can't get the information or don't want to set up within Outlook's > Newsreader, consider groups.google.com or - perhaps -groups.yahoo.com (you > have a yahoo email account but I can't reach groups.yahoo.com from work). I think groups.yahoo.com is only for yahoo discussion group, not for newsgroups. While yahoo do have FPGA discussion groups, it is different from comp.arch.fpga HendraArticle: 76464
Hendra wrote: > 3. Buy an FPGA board. Get Spartan 3 kit (sold directly from Xilinx) or > other FPGA boards from third party vendors such as Digilent or Xess. > 4. Start using your EDA tools, such as Xilinx Webpack. I would say you > should start from Schematics first, then move to HDL. Don't start > directly with HDL because it may misguide you to think that HDL is > just like C. Doing schematics first also force you to think in term of > hardware, not software. This will help later when you do your project > with HDL. I agree, today students think more in software than in hardware. Therefore hardware has to be introduced. But only three points have to be respected, to *start* with HDLs: - loops have to be expressed by the "process"-statement in VHDL (AFAIK "always" in Verilog) - one bit is stored in a signal, assignments happen on a clock edge - results of logic functions are assigned to signals, within the "process"-statement Classical approaches teach logic elements and logic minimation, but this is counterproductive. Today you should think in logic functions (LUts) and not in gates, in vectors and not in shift registers. Bye Tom.Article: 76465
mitrusc1980-newsgroup@yahoo.com.br (Marcio A. A. Fialho) wrote > Does anyone knows if Actel still manufactures obsolete and > legacy rad-hard (or rad-tolerant) parts like RT1460A or > RT54SX16 ? I think these parts would suit or needs. > I will ask Actel about this. At least there should be devices deliverabel. Never tried to get one of them, but RH1020 are still in stock (RT1020 are out of order). > Thomas Stanka (usenet_10@stanka-web.de) wrote: > > ... > > What to you mean with "user gates"? 2input-NAND? 4 input LUT > > When an RH1020 is to small you need an RT54SX32S. But be aware, > > there's currently a relability problem when using the RT54SX-S > > devices. > > > What reliability problem is this related to the RT54SX-S devices? There's a problem due to the possibility of having weak fuses which might increase the delay of a path in your design. This antifuse might be stable for up to 2100h before showing this delay. Try starting with klabs.org to get more details, as this problem is very new, there are a lot of "uncertain" informations. > Does this reliability problem affects RTSX-SU devices? No, only the availability of UMC-Parts *g*. > Actel told me that RT54SX-X and RTSX-SU are based in the > same design. The difference is that RT54SX-X parts are > manufactured by MEC and RT54SX-SU are produced at UMC. Yes thats right. The basic difference is that UMC-Parts use an other fuse design. A second point is, that the inrush-current issue due to power cycling is solved in UMC-parts. > > > P.S: ASICs (Field Gate Arrays) would be OK, provided it cost less than > > > US$10,000.00 and takes less than a month or two to be fabricated. In > > > case we opt for an ASIC, only around 3-5 units would be produced. > > > > I know no alternative when spending 30-50k$ for that number. AFAIK > > there are Actel fpgas above 10k$ per device. > > It seems that an ASIC is indeed very expensive. Anyone has a value for the > cheapest rad-tolerant ASICs (around 1k 2input NAND-gates) ? Well the price depends on many factors like quantity, flow and so on. The cheapest device suitable for long term missions should be the RH1020 with ~2000 NAND2-gates. The RT54SX32S device in B-Flow should be quite cheaper, in E-Flow a bit more expensive than the RH1020. bye ThomasArticle: 76466
u1000393@email.sjsu.edu (Hendra) wrote in message news:<3ef7b4ba.0412021721.47c30cc9@posting.google.com>... > qizhang@kth.se (kevin) wrote in message news:<b5c1b76d.0412021157.360a7def@posting.google.com>... > > how to start with development of eda tools(e.g simulation tools and > > synthesizing tools): what knowledge should i know and where i can find > > the > > informations(tutorial, guides or something else) > > > > thanks! > > br > > 1. Review your digital logic design. Especially the combinational, > synchronous sequential and state machine design. I say this because > using the tools wouldn't make sense if you don't know the theory. > 2. You should have experience of building simple circuits with TTL > chips. This will get you a physical feeling with gates, decoder, mux, > flipflop etc. > 3. Buy an FPGA board. Get Spartan 3 kit (sold directly from Xilinx) or > other FPGA boards from third party vendors such as Digilent or Xess. > 4. Start using your EDA tools, such as Xilinx Webpack. I would say you > should start from Schematics first, then move to HDL. Don't start > directly with HDL because it may misguide you to think that HDL is > just like C. Doing schematics first also force you to think in term of > hardware, not software. This will help later when you do your project > with HDL. > 5. Learn either Verilog or VHDL. The book that I read to learn Verilog > is Verilog HDL by Samir Palnitkar. It is the best Verilog book for > beginner. I recommend Verilog because it is much easier to learn. VHDL > is Very Hard and Difficult to Learn :-) > 6. Go back to your EDA tools and start using Verilog with the tools. > > Some Useful URLs: > www.xilinx.com/ise/webpack : Free Xilinx EDA tools. Comes with > simulator and synthesis tool. > www.digilentinc.com: FPGA board vendor > www.xess.com : Another FPGA board vendor > www.xilinx.com/products/spartan3/s3boards.htm : Spartan 3 Starter Kit > www.engr.sjsu.edu/crabill : This website has some HDL projects to work > with. > xup.msu.edu : Xilinx University website. It has links to the EDA > tutorials along with projects to work with your EDA tools. > > Have fun! > > Hendra Hi Hendra: Thanks for your reply! But what you said seems how to use vhdl/verilog to do fpga design, but in fact, these are what i have been doing for years, and what interest me more now is the algorithms and principles of simulation and synthesizing, and i really want to make a tiny simulation tools(like simili) or synthszing tools, that's what i want :-). Thank you again br kevinArticle: 76467
Patrick Kulle wrote: > Kolja Sulimma wrote: > >>[...] Running XPower gives the following >>results per event: >>DFF - 353fJ >>SR16 - 4853fJ >>RAMLut - 653fJ >>LUT+carry - 2756fJ >>[...] > > > Hellp Kolja, > > thanks for your post, now it gets clearer for me. Could you please tell > me, where I can find the results per event you gave above? I went to the WebPower Site and entered a row for 10000 DFF at 100 MHz with 100% toggle rate and multiplied the result by 1ps. I build similar row for the other parameters. Kolja SulimmaArticle: 76468
I have been running a shift register design through a web version of Quartus 4.1 (SP2). Depending on the size of shift register either the tools don't complete (I waited 30 mins and gave up) or on smaller shifts of 720 I get a design that is a large size and it takes a long time to implement. Has anyone else seen this problem ? Or know of any tool switches that need set to solve this ? I have selected large enough Cyclone part and before anyone asks I am running a reasonable machine. An Athlon64 3000 with 512 MByte of memory for those that want the detail. I have run the same design (large version) on Spartan-3 / ISE and it less than 3 minutes to do the same. JohnArticle: 76469
Bret, > I'm glad you liked the idea. I'm not yet clear on why the RLOCs need to > be annotated back into the EDIF netlist. An easier option would be to > just copy the UCF constraints to an NCF file with the same name as the > EDIF file. From a Xilinx tool perspective, that is identical to the > constraints being in the netlist. My goal is to place some macro-blocks of logic near some other logic components, and I want to do this in a programmable/abstract way. In JHDL I can do this using an intuitive sounding function called place(). So I can do: place(a, IN_THE_MIDDLE_OF, b) for example. But in order to implement this, the JHDL system has to know the bounding boxes for a and b. The only way it can know this, is if a and b are already relatively placed. One way to achieve this would be to write everything in JHDL by hand and do all the placements for a and b (and their sub components) manually, but this would be tedious and restricts me to only using logic elements written entirely in JHDL. Fortunately JHDL has an EDIF parser which will load in an EDIF file and turn it into JHDL logic. So this way I can make use of the Xilinx tools to do a thorough and reasonable job of placing all the large pieces of logic I can't be bothered to place manually, but still use the JHDL placement stuff. Then when I'm done with my complete system with the autogenrated RLOCs and the ones which I inserted manually (using place()), I can then get JHDL to spit out another EDIF which I can then turn into a FPGA bitfile. So I need to annotate the EDIF file with the UCF file, as the JHDL EDIF parser does not support external annotations from a UCF file, and won't be able to do the relative placements if it doesn't have these details represented internally. To be even more precise, having looked at the source code, it doesn't look like JHDL interprets the RLOCs either. But hopefully I can add this functionality, or I might even just get it to read the UCF and then annotate the JHDL representation of the logic anyway. - JakeArticle: 76470
Guys We have just laid out a board and want to put the thermal analysis to bed (it's conduction cooled so not much room for error). If the xilinx estimator says we are going to use 25 watts does anyone know the best way to code an FPGA so that it will get nice and hot. The estimator is just that, but is there a more accurate way of writing some code so that a particular clock input will generate a particular amount of heat. A 2000 D type serial chain where every flip flop is toggling every clock which blinks an LED is obviously one way but doesn't seem very ellegant. We have wired up the internal temp sense diode to take a look at the result (and yes we know how noisy and innacurate they are). Any experiences? ColinArticle: 76471
kevin wrote: > u1000393@email.sjsu.edu (Hendra) wrote in message > news:<3ef7b4ba.0412021721.47c30cc9@posting.google.com>... > > > Hi Hendra: > > Thanks for your reply! > > But what you said seems how to use vhdl/verilog to do fpga design, but > in fact, these are what i have been doing for years, and what interest > me more now is the algorithms and principles of simulation and > synthesizing, and i really want to make a tiny simulation tools(like > simili) or synthszing tools, > that's what i want :-). start from http://www.geda.seul.org/ ? vax, 9000 > > Thank you again > br > > kevinArticle: 76472
On Thu, 2 Dec 2004 22:20:50 +0000 (UTC), Jacob Bower <jacob.bower@gmail.com> wrote: >Bret, > >> A different approach would be to use the Floorplanner feature which >> generates a reusable RPM core. You have the option of generating UCF >> constraints or a fully annotated core in NGC format (a binary file >> similar to the NGO file). Then as Ray mentioned you can add RLOCs >> throughout the hierarchy to further manipulate the relative placement. >> >> http://toolbox.xilinx.com/docsan/xilinx6/help/floorplanner/floorplanner.htm > It doesn't work very well ... yet. I have a couple of webcases open on that, and hopefully Xilinx are working to fix some of the problems. >The only thing missing is annotating the EDIF file directly with the >constraints generated by the Floorplanner in UCF format. I think I can >probably manage writing a tool to do this though. This MAY be possible. The floorplanner writes an UCF for the RPM, and (assuming that UCF works) can invoke "NGCbuild" to back-annotate the placement information into the proprietary NGC file from the XST synthesis tool. There is an "NGC2EDIF" tool which I have used to verify that the resulting NGC tool contained valid placement info from the above process - its EDIF output did - while trying to debug the above approach. So if you can convert from EDIF to NGC in the first place, there is the basis for a loop. I haven't tried the EDIF flow so can't comment, though it's interesting that NGC2EDIF is present but NGD2EDIF is now unsupported. - BrianArticle: 76473
mitrusc1980-newsgroup@yahoo.com.br (Marcio A. A. Fialho) wrote in message news:<394351c1.0411251428.49ebc1ee@posting.google.com>... > I'm looking for a rad-tolerant, non-volatile (preferably programmable > at once) FPGA or CPLD, for a new project (a satellite instrument). > > After searching the Web, I've found out that Actel manufactures micro > antifuse FPGAs. These would be fine, but I would like to know if are > there any other alternatives besides Actel FPGAs. > > The device should have around 2500 user gates or more. > > Reliability is a concern to us, and availability of a similar or > equivalent, in System Programmable (ISP), part would be a plus. > > Any single chip solution (preferably non-reprogrammable, to avoid > unintentional program changes, due to radiation) would be fine, > including CPLDs. > > P.S: ASICs (Field Gate Arrays) would be OK, provided it cost less than > US$10,000.00 and takes less than a month or two to be fabricated. In > case we opt for an ASIC, only around 3-5 units would be produced. > > If you are willing to help, you can e-mail me directly: > maaf _att_ dea.inpe.br (replace the _att_ by an @) > > Best Regards, > Marcio > --------------------------------------------------- > Marcio Afonso Arimura Fialho > Junior Electronic Engineer > DEA - Divisão de Eletrônica Aeroespacial > INPE - Instituto Nacional de Pesquisas Espaciais (Brazilian National > Institute for Space Research). I knew a Nasa engineer who also designed satellite instruments, he was personally horified at the idea of FPGAs rushing into space, but I am sure I heard that the mars missions had them anyway. Search google groups for past posts on this. Perhaps they get reconfigured regular to limit soft changes. If it wasn't for the rad hard issue and your schedule I'd suggest using something like the MOSIS or EUROPRACTICE shuttle services and do a small ASIC. The cost sharing on an old technology device would give you low cost in a few months and the performance would certainly match FPGA. Ask them about RAD as well. regards johnjakson_usa_comArticle: 76474
1. On a pci target a have on the pci bus signals pci_ad[31:0] and on the backend interface a have bkend_data[31:0] (for data r/w) and backend_adr[31:0] (for address r/w). If I interface a fifo 512x32bits I must connect bkend_dat[31:0] on the fifoin_dat[31:0]. But fifos don't have address lines. What shoud I must to do with bkend_ad[31:0] address lines?? (Put its on high-z ???) 2. If my pci target doesn't meet pci tsu<7ns and tco<11ns it is posible to work??? Thanks,
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