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I'm having difficulty making RPMs in the floorplanner (Webpack, 6.3i) as
follows.
I can load a synthesised/translated design (.ngd) into the floorplanner,
recreate its hierarchy (using "group by"), place it nicely, and save the
design.
Took a while to realise that I had to have "write BEL" set in
"Edit/Preferences" to preserve the location of LUTs, FFs, within an
individual slice, but I got there...
"Write RPM as UCF" usually crashes.
("FATAL_ERROR:GuiUtilities:WinApp.C:657:$Revision This application has
discovered an exceptional condition from which it cannot recover")
Seems to be less likely if all I do is load a floorplan in and write it
out, but still it crashes more often than not, for me. However it's not
impossible to edit "LOC= Slice_XnYm" into RLOC properties, so carry on.
Back annotating the RLOCs into the .ngc file seems OK, (though searching
support.xilinx.com for "ngcbuild" yields ... nothing!) ... anyway
ngc2edif confirms it's doing roughly the right thing.
Now I'm getting a bit stuck.
I want to read the new design back into the floorplanner. Easy, you
might think ... simply "translate" and read in the .ngd.
Except that the BEL information has disappeared, and LUTs, FFs and even
carries are randomly swapped around within a slice! All those nice
straight connections are randomly crossed, and the bus is wired as
0,1, 2,3, 5,4, 7,6, 9,8, 10,11 etc. If the MSB of a chain is the only
one in a slice, odds are it's isolated with a gap between it and its
fellows.
Place and route seems to work, and I can load the above mess and
straighten it out by "constrain from placement" ... except that I need
this RPM as a component at higher levels, which I also want to
floorplan.
Am I missing something simple, or am I expecting too much of the
floorplanner?
One curiosity ... I tried the old (XC4000!) style of constraint in the
UCF, for some FFs (INST myFF RLOC="XnYm.FFX" ) and the floorplanner
appeared to accept it. But of course the mapper didn't...
Any ideas?
- Brian
Article: 76076
Rather than reentering those commonly used parts time and
again, create
them as a separate entity/architecture then instantiate them
when you need
them. Keep those commonly used parts in a directory where you
can use
them in future designs. As you do it more, you'll find
things that can be
parameterized to handle similar designs with minor variations
such as
port widths and so on. This approach also has the advantage
in testing,
since you only need to test the component once. Keep a
testbench for the
component with the component so that you can verify later
that it was
tested.
Nial Stewart wrote:
> I'm a hardware design engineer with 10years background in
> FPGA design. To date all my design entry and simulation
> has been with VHDL but I seem to keep having to type
> similar (but not identical) ram instantiations/ state
> machines/ clock domain re-synch processes etc. This
> ends up a bit tedious and I've been wondering how
> to circumvent the tedium.
>
> I've been looking at the grahical state machine entry
> facility of Modelsim Design and wondering if it's any
> good and would end up saving any time. I suspect not
> or the software industry would have adopred this sort
> of design entry method years ago.
>
> This started me wondering what the favourite design entry
> optomisation methods of our experienced comp.arch.fpga
> contributors are? Has anyone had any success with
> graphical entry?
>
> Nial
>
> ------------------------------------------------
> Nial Stewart Developments Ltd
> FPGA and High Speed Digital Design
> Cyclone Based 'Easy PCI' proto board
> www.nialstewartdevelopments.co.uk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 76077On Tue, 23 Nov 2004, Nju Njoroge wrote: > On Tue, 23 Nov 2004, Andi wrote: > > > Do you have SP2 for Wxp installed? Did you uninstalled everything xilinx 6.2 and edk 6.2 with all service packs? > > > No, I don't have SP2 installed (I heard it had some issues, so I didn't > instal it). To my knowledge, I uninstalled all previous versions of EDK > and ISE. I actually installed ISE 6.3 before EDK 6.3 because > we received it first. ISE 6.3 works, before and after EDK 6.3i > installation. I also installed the new ISE SP and the updates for EDK > 6.3. I got it to finally work. I had to un-install both ISE and EDK 6.3. After the un-installations, I re-installed EDK 6.3 and then ISE 6.3. This somehow fixed the "entry point" issue.Article: 76078
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<SLLod.7202$3U4.200703@news02.tsnz.net>... > just saw this > > http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=TDU3YDUKFOWG4QSNDBCSKHSCJUMEKJVN?articleID=54200060 > > 0.18u/40V/ OTP and MTP IP "without additional process steps" > > Imagine the CPLD you could ship with that process ?. > > Coolrunner or Lattice like devices without the voltage ceiling pains... > > -jg Ok these devices like many previous 40V process probably use the LDD (lateral drain device) type structure which really just means that some IO devices can be made very high V tolerant ie open drain needed for LCD type panels. These are not .18u at all, more like several microns long underneath the field oxide which is way thicker than gate oxide and also acts as a thick field gate oxide. Usually you don't want any signals above the ordinary field oxide to be high enough V to make unwanted transister effect under "plain wiring" hence signals also have to be limited to low V (<<5V) within the chip core. Not sure I'd expect to see this in any CPLD/FPGA though. regards johnjakson_usa_comArticle: 76079
There have been several posts recently concerning FPGA development boards. DO NOT use Nu Horizons as a supplier under any circumstances. They make promises that they don't deliver on. When they do deliver the product may be defective (I was shipped a board that had a tag attached listing the defects). I have been in the business in excess of 30 years and Nu Horizons is, easily, the worst vendor I have ever delt with. Use these guys AT YOUR OWN RISK!!!!Article: 76080
hello all, i have been reading a lot about performance comparisons between leading FPGA chip makers on hteir web-sites. both claim improvement upon the other by metrics of 20 - 40 % .... though none has ever described what exactly was compared. are there resources available on the net, which compare different architecture in detail (and also impartially) .. !! ?? -- Varun.Article: 76081
This would happen if you have different EDK and ISE versions installed on the same machine. Make sure the $PATH environment variable points to same (compatible) version of EDK and ISEArticle: 76082
Varun Jindal wrote:
> i have been reading a lot about performance comparisons between
> leading FPGA chip makers on hteir web-sites. both claim improvement
> upon the other by metrics of 20 - 40 % .... though none has ever
> described what exactly was compared.
>
> are there resources available on the net, which compare different
> architecture in detail (and also impartially) .. !! ??
Brand A and X are roughly equivalent.
Use the vendor that gives you the best service
and distribution.
-- Mike Treseler
Article: 76083
Brian Drummond wrote:
> On Mon, 22 Nov 2004 15:23:17 -0800, "Brad Smallridge"
> <bradsmallridge@dslextreme.com> wrote:
>
>
>>What are the procedures for adding signals to the simulation? I have been
>>going to the SIGNALS pane, and clicking on add to wave signals in design.
>>Then, since that seems to give me everything, I start deleting most of them.
>
>
> Select the ones you want in "Signals" before clicking "Add".
>
> - Brian
>
You can also type
add wave *
in the command window, and it will add all signals from your testbench.
cheers
Roman
Article: 76084Hi,all I am designing a simple pci to ide (PIO mode) interface with FPGA. There is a problem, how should I connect the IDE's Interrupt pin with PCI's INTA? It's OK to do PIO transfer without interrupt. But the device driver I used will try to probe the interrupt, without interrupt, it wouldnt work. Thanks a lot! RegardsArticle: 76085
"Jack// ani" <nospam4u_jack@yahoo.com> wrote in message news:86040da6.0411200551.6609a567@posting.google.com... > Hi all, > > I'm new to FPGA and CPLD. Had just started learning VHDL, I'm keen to > implement my design on real Xilinx FPGA. Buying a professional > development board is really a costly affair, so I'm interested to > build my own FPGA board for learning purpose! > > Can anybody provide please provide me some help, where should I start > or suggest some pointer? > > All I know about FPGA board is; FPGA board is similar to > microcontroller board, and you have to download the bits into it. And > you have download cable for this purpose, whose schematic is available > at Xilinx's site. > > And finally which FPGA should I select? It should be SRAM, so I can > reprogram it again and again, and should be cheap though. > > Thanks in advance Like Leon pointed out Xilinx spartan3 starter kit for US$99 https://digilent.us/Sales/Product.cfm?Prod=S3BOARD also coolrunner2 starter kit for US$49 http://www.digilentinc.com/XC2XL.html?Prod=xc2xl both are made by digilentinc for xilinx. Digilent also make addon boards like ethernet and usb(to connect to pc) https://digilent.us/Sales/System.cfm system boards https://digilent.us/Sales/Peripheral.cfm peripheral boards Xess make some boards www.xess.com As do lots of others www.fpga4fun.com Jean sells some boards www.burched.com Tony Burch Altium Livedesign boards US$99 www.altium.com/livedesign can be programs from either inside protel or from the fpga vendor tools lots of others out there AlexArticle: 76086
Austin, Thanks for your prompt reply. I understand the rationale behind it, but the way it was announced is very misleading. One can interprete as the Spartan3L being a separate product. And yes, the trick (I'm sorry for the wording) with switching off the power supply is not an option for me. Regards, Luc On Tue, 23 Nov 2004 15:27:15 -0800, Austin Lesea <austin@xilinx.com> wrote: >Luc, > >Sorry you are disappointed. > >There are two modes, one the devices are selected for low quiescent >current. We have many customers who appreciate this, and are willing to >pay a small premium for it. Because they asked for it, we figured out >how to offer it. Very similar to speed grades, or in this case, leakage >grades. > >The other mode, is that the device is also tested to be able to be >externally switched on and off with its supplies. It may seem like a >trick to you, but it is most certainly not. All the IOs and internal >logic are well behaved, and the supplies can be switched on and off >without any glitching or funny behavior. We also had customers wishing >to use the devices in this way. > >To test and grade devices from the larger population for special >applications is not free. To specify and stand behind those >specifications allows a wider application of S3 without spending what it >would take to make another product line. > >Customer wins, we win. > >Again, sorry it did not meet your needs, > >Austin > >Luc wrote: >> I was looking to the Spartan 3L for use in a low power design that >> will start up soon. >> Browsing through the datasheet I found however that there is no real >> difference between the 3 and 3L. >> Switching of Vccint to safe power? I assume that when you do this, you >> lose the configuration too. >> I don't understand why Xilinx tries to mislead customer with the so >> called 'low power' FPGA. >> I'm very disappointed about this approach that I will certainly not >> use S3 for my future product, and I really hope that other potential >> customers feal the same about this marketing trick for selling >> vaporware. >> >> Regards, >> >> LucArticle: 76087
On Tue, 23 Nov 2004 21:13:49 -0000, "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote: >I'm a hardware design engineer with 10years background in >FPGA design. To date all my design entry and simulation >has been with VHDL but I seem to keep having to type >similar (but not identical) ram instantiations/ state >machines/ clock domain re-synch processes etc. This >ends up a bit tedious and I've been wondering how >to circumvent the tedium. [...] > >This started me wondering what the favourite design entry >optomisation methods of our experienced comp.arch.fpga >contributors are? Has anyone had any success with >graphical entry? I have to admit I'm a fan of Renoir, or "HDL Designer" as it's now called. I also prefer VHDL, despite its verbosity - I rarely see the verbosity, certainly don't have to type much of it. I can't say that graphical entry provides much optimisation, but IMO it makes visualisation, navigating and maintaining a complex hierarchy a relatively easy task. If "Modelsim Design" is Renoir/HDL designer (block and state diagrams) packaged together with Modelsim, then it gets one vote here. - BrianArticle: 76088
I see that Micron SDRAMs are claimed to support Concurrent auto precharge. Is this a common feature amongst SDRAMs? I'm using a sample of a ICSI SDRAM at present and this feature isn't mentioned in the data sheet. Is it safe for me to presume it doesn't support Concurrent auto precharge? I am trying to write and read blocks of 4 words and don't really want to extend the buffering to accommodate an 8 word burst!Article: 76089
Luc, Marketing. Not my 'thing'. Austin Luc wrote: > Austin, > > Thanks for your prompt reply. I understand the rationale behind it, > but the way it was announced is very misleading. One can interprete as > the Spartan3L being a separate product. > And yes, the trick (I'm sorry for the wording) with switching off the > power supply is not an option for me. > > Regards, > > Luc > > On Tue, 23 Nov 2004 15:27:15 -0800, Austin Lesea <austin@xilinx.com> > wrote: > > >>Luc, >> >>Sorry you are disappointed. >> >>There are two modes, one the devices are selected for low quiescent >>current. We have many customers who appreciate this, and are willing to >>pay a small premium for it. Because they asked for it, we figured out >>how to offer it. Very similar to speed grades, or in this case, leakage >>grades. >> >>The other mode, is that the device is also tested to be able to be >>externally switched on and off with its supplies. It may seem like a >>trick to you, but it is most certainly not. All the IOs and internal >>logic are well behaved, and the supplies can be switched on and off >>without any glitching or funny behavior. We also had customers wishing >>to use the devices in this way. >> >>To test and grade devices from the larger population for special >>applications is not free. To specify and stand behind those >>specifications allows a wider application of S3 without spending what it >>would take to make another product line. >> >>Customer wins, we win. >> >>Again, sorry it did not meet your needs, >> >>Austin >> >>Luc wrote: >> >>>I was looking to the Spartan 3L for use in a low power design that >>>will start up soon. >>>Browsing through the datasheet I found however that there is no real >>>difference between the 3 and 3L. >>>Switching of Vccint to safe power? I assume that when you do this, you >>>lose the configuration too. >>>I don't understand why Xilinx tries to mislead customer with the so >>>called 'low power' FPGA. >>>I'm very disappointed about this approach that I will certainly not >>>use S3 for my future product, and I really hope that other potential >>>customers feal the same about this marketing trick for selling >>>vaporware. >>> >>>Regards, >>> >>>Luc > >Article: 76090
Varun, Your best bet is to contact the FAE (Field Applications Engineers) for both campanies, and have them explain exactly what their claims are based on. What speed grades were compared (e.g. their fastest with our mid-grade)? What were the settings of the synthesis tools (e.g. their default vs our default -- we default for speed of synthesis, theirs for a compromise of performance)? What effort was made to use device specific features (e.g. theirs a lot, ours a little)? What choice of device was made (e.g. their only one choice, versus our three options to best fit: LX for logic, SX for DSP, and FX for networking and comms)? Or, you could do like the other posters' suggest: IGNORE IT and do your own benchmark by examining specifications and trying out some intended critical logic, and/or examining the offering of IP from each company (and its perfomance). Who is to say which device is 'better'? Only after careful study, and use of specific features that may offer an improvement can one make a decision. And that decision only holds for that one (type of) design! The "speed superiority" claims appeared three days after we announced the availability of three V4 parts as engineering samples.....compared to their unavailability. Hey it ain't fun when your foundry can't supply the parts to you, is it? Our 90nm offerings are succeeding because we did engage early with our fab partners, and did shake the process out. If you wait until the process is stable, you will wait forever. If you don't want the process, you are dependent on other larger customers of the fab.....and maybe they are making 130nm ASICs and are perfectly happy to wait until someone else has paid for the 90nm wafer starts to shake out the new process. And who will use the triple oxide process for reduce leakage and power on currents? No one but an FPGA vendor. No process, no performance. Our fabs like us for our willingness to be full partners in the development of a new advanced process. I think our customers understand that sometimes there will be rough spots in a new introduction of a new product on a new process, but overall we continue to offer superior products (in my opinion). Austin Varun Jindal wrote: > hello all, > > i have been reading a lot about performance comparisons between > leading FPGA chip makers on hteir web-sites. both claim improvement > upon the other by metrics of 20 - 40 % .... though none has ever > described what exactly was compared. > > are there resources available on the net, which compare different > architecture in detail (and also impartially) .. !! ?? > > -- Varun.Article: 76091
"Ray Andraka" <ray@andraka.com> wrote in message news:41A3E0C8.A03D2965@andraka.com... > Rather than reentering those commonly used parts time and > again, create > them as a separate entity/architecture then instantiate them > when you need > them. Keep those commonly used parts in a directory where you > can use > them in future designs. As you do it more, you'll find > things that can be > parameterized to handle similar designs with minor variations > such as > port widths and so on. This approach also has the advantage > in testing, > since you only need to test the component once. Keep a > testbench for the > component with the component so that you can verify later > that it was > tested. The downside of this approach is that you can disguise the functionality of what's going on with multiple sub-component instantiations. I suppose it's swings and roundabouts, simpler more easily decipherable design files or a reduction in time spent on design entry. Nial.Article: 76092
Hi there, Is there a straightforward way of passing the values of VHDL generics to the xst executable when operated in command line mode? I have searched the web but to no avail. Many thanks. RiyazArticle: 76093
Hi all - I'm using an Actel AX250-2 (Axcelerator) in a new design which uses several phased clocks at about 250MHz. The phase relationship is important and one of the reasons for the Actel choice. They have a very fine adjustment for the PLLs and a low jitter measurement number. I tried to get the AX250-3 part but they are having trouble with the manufacture process. The -2 is fully capable of operation at 250MHz, though. Is there a better/as good solution from some other manufacturer that anyone has experience with? Is there anything available in FLASH that anyone has experience with? Any positive or negative experiences would be appreciated. TIA DaveArticle: 76094
Varun Jindal wrote: > i have been reading a lot about performance comparisons between > leading FPGA chip makers on hteir web-sites. both claim improvement > upon the other by metrics of 20 - 40 % .... though none has ever > described what exactly was compared. There are different metrics, and each design has different needs. Even so, it is possible for each to be 20-40% improved over the other. That is why geometric mean is preferred for benchmarks. Say you have two benchmark programs. Machine A runs the first in 1 minute, the second in two. Machine B runs the first in two seconds, the second in one. Machine A runs the first 2 times as fast and the second 0.5 times as fast, the average then is (2+0.5)/2 or 1.25 so machine A runs, on the average, 1.25 times as fast as machine B. If you do it the other way, you find machine B is 1.25 times as fast as machine A. Be very careful when you read benchmark numbers, and always use geometric mean. -- glenArticle: 76095
Does anyone know of any MIL-Qualified RTOS to run on uBlaze or Nios2? I normally work with uCLinux, but in this case the MIL contractor/customer needs something that has gone through a MIL qualification process to pry them away from single-board x86 computers. Does anyone have any experience in this?? ThanksArticle: 76096
Hi,
I have a simple program which reads a file from the systemace CF
device on vertex II board.
#include "xparameters.h"
#include "xutil.h"
#include "sysace_stdio.h"
char *Filename = "winter.jpg";
int main (void) {
FILE *fp;
printf("starting....\r\n");
if ((fp = fopen(Filename, "r")) == NULL) {
printf("\r\nCan't open file: %s \r\n", Filename);
return 0;
}
}
Everything goes fine except the program freezes at the "fopen...."
line. I use XMD software debugger to trace into the code, and found
actually it runs into indefinitely loop at the following line in the
driver "sysace.c":
while ((Result = XSysAce_Lock(&Ace, XFALSE)) != XST_SUCCESS);
That means the systemace device is always busy and can't be locked for
exclusively reading. That's why it keeps running the "while" loop
there.
Anybody could help me to figure out the reason why the device is
always busy? Or am I missing some pre-configurations or parameters to
the device?
Thanks in advance.
-Yongjie
Article: 76097Hi! I encounter a strange problem that I haven't been able to solve for several days of hard work. I'm using a Spartan2 in order to achieve dynamic partial reconfiguration, but my design doesn't work even if it passes through all the steps successfully. I think that the problem comes from my bus macro (released by Xilinx with XAP 290) that it isn't correctly included in my design after the very first mapping. My design includes two modules and therefore only two bus macro (one for each direction), but one of them is divided in two part (two wires are mapped in respect of the macro, but the two others are mapped in another position). Grégory Mermoud gregory.mermoud@epfl.ch Master Student Computer Science Departement I&C Faculty Swiss Federal Institute of Technology - LausanneArticle: 76098
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:41a4b50a$0$1072$db0fefd9@news.zen.co.uk... > > "Ray Andraka" <ray@andraka.com> wrote in message > news:41A3E0C8.A03D2965@andraka.com... > > Rather than reentering those commonly used parts time and > > again, create > > them as a separate entity/architecture then instantiate them > > when you need > > them. Keep those commonly used parts in a directory where you > > can use > > them in future designs. As you do it more, you'll find > > things that can be > > parameterized to handle similar designs with minor variations > > such as > > port widths and so on. This approach also has the advantage > > in testing, > > since you only need to test the component once. Keep a > > testbench for the > > component with the component so that you can verify later > > that it was > > tested. > > > The downside of this approach is that you can disguise the > functionality of what's going on with multiple sub-component > instantiations. > > I suppose it's swings and roundabouts, simpler more easily > decipherable design files or a reduction in time spent on > design entry. > > > Nial. > > Hi Nial, When Ray posted I thought he was stating the bleeding obvious; apparently not! Maybe I'm missing something, but are you saying you've been doing HDLs for 10 years and you don't have a bunch of useful entities that you reuse? I don't see how this approach disguises the functionality. They're certainly the most tested and best documented parts of my code. The hierarchy improves readability. As Ray says, when something new comes up that's close to what you did before, I add stuff so the new block does both old and new. Generics are especially useful here. Ah well, each to his own. Cheers, Syms.Article: 76099
What? Did you mix up minutes and seconds in there? Don't you just add the times to see which one is quicker? And take into account which type of program you run most often? Cheers, Syms. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:co2ip8$in0$1@gnus01.u.washington.edu... > There are different metrics, and each design has different needs. > > Even so, it is possible for each to be 20-40% improved over > the other. That is why geometric mean is preferred for benchmarks. > > Say you have two benchmark programs. Machine A runs the first > in 1 minute, the second in two. Machine B runs the first in > two seconds, the second in one. > > Machine A runs the first 2 times as fast and the second 0.5 > times as fast, the average then is (2+0.5)/2 or 1.25 so machine > A runs, on the average, 1.25 times as fast as machine B. > > If you do it the other way, you find machine B is 1.25 times > as fast as machine A. > > Be very careful when you read benchmark numbers, and always > use geometric mean. > > -- glen >
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